2 * Copyright (C) 2014-2015 ROCKCHIP, Inc.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 #include <dt-bindings/clock/rockchip,rk3228.h>
18 compatible = "rockchip,rk-clocks";
21 ranges = <0x0 0x110e0000 0x1000>;
24 compatible = "rockchip,rk-fixed-rate-cons";
27 compatible = "rockchip,rk-fixed-clock";
28 clock-output-names = "xin24m";
29 clock-frequency = <24000000>;
34 compatible = "rockchip,rk-fixed-clock";
36 clock-output-names = "xin12m";
37 clock-frequency = <12000000>;
41 hdmiphy_out: hdmiphy_out {
42 compatible = "rockchip,rk-fixed-clock";
43 clock-output-names = "hdmiphy_out";
44 clock-frequency = <594000000>;
48 usbphy0_480m: usbphy0_480m {
49 compatible = "rockchip,rk-fixed-clock";
50 clock-output-names = "usbphy0_480m";
51 clock-frequency = <480000000>;
55 usbphy1_480m: usbphy1_480m {
56 compatible = "rockchip,rk-fixed-clock";
57 clock-output-names = "usbphy1_480m";
58 clock-frequency = <480000000>;
62 jtag_clkin: jtag_clkin {
63 compatible = "rockchip,rk-fixed-clock";
64 clock-output-names = "jtag_clkin";
65 clock-frequency = <0>;
70 compatible = "rockchip,rk-fixed-clock";
71 clock-output-names = "dummy";
72 clock-frequency = <0>;
76 gmac_clkin: gmac_clkin {
77 compatible = "rockchip,rk-fixed-clock";
78 clock-output-names = "gmac_clkin";
79 clock-frequency = <0>;
83 phy_50m_out: phy_50m_out {
84 compatible = "rockchip,rk-fixed-clock";
85 clock-output-names = "phy_50m_out";
86 clock-frequency = <0>;
90 phy_rx_out: phy_rx_out {
91 compatible = "rockchip,rk-fixed-clock";
92 clock-output-names = "phy_rx_out";
93 clock-frequency = <0>;
97 phy_tx_out: phy_tx_out {
98 compatible = "rockchip,rk-fixed-clock";
99 clock-output-names = "phy_tx_out";
100 clock-frequency = <0>;
104 clkin_hsadc_tsp: clkin_hsadc_tsp {
105 compatible = "rockchip,rk-fixed-clock";
106 clock-output-names = "clkin_hsadc_tsp";
107 clock-frequency = <0>;
111 i2s_clkin: i2s_clkin {
112 compatible = "rockchip,rk-fixed-clock";
113 clock-output-names = "i2s_clkin";
114 clock-frequency = <0>;
120 compatible = "rockchip,rk-fixed-factor-cons";
122 hclk_rkvdec: hclk_rkvdec {
123 compatible = "rockchip,rk-fixed-factor-clock";
124 clocks = <&aclk_rkvdec>;
125 clock-output-names = "hclk_rkvdec";
132 compatible = "rockchip,rk-fixed-factor-clock";
133 clocks = <&aclk_vpu>;
134 clock-output-names = "hclk_vpu";
140 xin32k_out: xin32k_out {
141 compatible = "rockchip,rk-fixed-clock";
142 clocks = <&clk_hdmi_cec>;
143 clock-output-names = "xin32k_out";
152 compatible = "rockchip,rk-clock-regs";
153 #address-cells = <1>;
155 reg = <0x0000 0x1000>;
158 /* PLL control regs */
160 compatible = "rockchip,rk-pll-cons";
161 #address-cells = <1>;
165 clk_apll: pll-clk@0000 {
166 compatible = "rockchip,rk3188-pll-clk";
168 mode-reg = <0x0040 0>;
169 status-reg = <0x04 10>;
171 clock-output-names = "clk_apll";
172 rockchip,pll-type = <CLK_PLL_3036_APLL>;
176 clk_dpll: pll-clk@000c {
177 compatible = "rockchip,rk3188-pll-clk";
179 mode-reg = <0x0040 4>;
180 status-reg = <0x10 10>;
182 clock-output-names = "clk_dpll";
183 rockchip,pll-type = <CLK_PLL_3036PLUS_AUTO>;
188 clk_cpll: pll-clk@0018 {
189 compatible = "rockchip,rk3188-pll-clk";
191 mode-reg = <0x0040 8>;
192 status-reg = <0x1c 10>;
194 clock-output-names = "clk_cpll";
195 rockchip,pll-type = <CLK_PLL_312XPLUS>;
197 #clock-init-cells = <1>;
200 clk_gpll: pll-clk@0024 {
201 compatible = "rockchip,rk3188-pll-clk";
203 mode-reg = <0x0040 12>;
204 status-reg = <0x28 10>;
206 clock-output-names = "clk_gpll";
207 rockchip,pll-type = <CLK_PLL_312XPLUS>;
209 #clock-init-cells = <1>;
213 /* Select control regs */
215 compatible = "rockchip,rk-sel-cons";
216 #address-cells = <1>;
220 clk_sel_con0: sel-con@0044 {
221 compatible = "rockchip,rk3188-selcon";
223 #address-cells = <1>;
226 clk_core_div: clk_core_div {
227 compatible = "rockchip,rk3188-div-con";
228 rockchip,bits = <0 5>;
229 clocks = <&clk_core>;
230 clock-output-names = "clk_core";
231 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
233 rockchip,clkops-idx = <CLKOPS_RATE_CORE>;
234 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
235 CLK_SET_RATE_NO_REPARENT)>;
240 clk_core: clk_core_mux {
241 compatible = "rockchip,rk3188-mux-con";
242 rockchip,bits = <6 2>;
243 clocks = <&clk_apll>, <&clk_gpll>, <&clk_dpll>;
244 clock-output-names = "clk_core";
246 #clock-init-cells = <1>;
249 aclk_bus: aclk_bus_div {
250 compatible = "rockchip,rk3188-div-con";
251 rockchip,bits = <8 5>;
252 clocks = <&aclk_bus_mux>;
253 clock-output-names = "aclk_bus";
254 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
256 #clock-init-cells = <1>;
259 aclk_bus_mux: aclk_bus_mux {
260 compatible = "rockchip,rk3188-mux-con";
261 rockchip,bits = <13 2>;
262 clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>;
263 clock-output-names = "aclk_bus";
265 #clock-init-cells = <1>;
272 clk_sel_con1: sel-con@0048 {
273 compatible = "rockchip,rk3188-selcon";
275 #address-cells = <1>;
278 pclk_dbg: pclk_dbg_div {
279 compatible = "rockchip,rk3188-div-con";
280 rockchip,bits = <0 4>;
281 clocks = <&clk_core>;
282 clock-output-names = "pclk_dbg";
283 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
285 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
288 aclk_core: aclk_core_div {
289 compatible = "rockchip,rk3188-div-con";
290 rockchip,bits = <4 3>;
291 clocks = <&clk_core>;
292 clock-output-names = "aclk_core";
293 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
295 rockchip,clkops-idx = <CLKOPS_RATE_CORE_CHILD>;
300 hclk_bus: hclk_bus_div {
301 compatible = "rockchip,rk3188-div-con";
302 rockchip,bits = <8 2>;
303 clocks = <&aclk_bus>;
304 clock-output-names = "hclk_bus";
305 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
307 #clock-init-cells = <1>;
312 pclk_bus: pclk_bus_div {
313 compatible = "rockchip,rk3188-div-con";
314 rockchip,bits = <12 3>;
315 clocks = <&aclk_bus>;
316 clock-output-names = "pclk_bus";
317 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
319 #clock-init-cells = <1>;
326 clk_sel_con2: sel-con@004c {
327 compatible = "rockchip,rk3188-selcon";
329 #address-cells = <1>;
332 hclk_vio: hclk_vio_div {
333 compatible = "rockchip,rk3188-div-con";
334 rockchip,bits = <0 5>;
335 clocks = <&aclk_iep>;
336 clock-output-names = "hclk_vio";
337 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
339 #clock-init-cells = <1>;
344 clk_nandc_div: clk_nandc_div {
345 compatible = "rockchip,rk3188-div-con";
346 rockchip,bits = <8 5>;
347 clocks = <&clk_nandc>;
348 clock-output-names = "clk_nandc";
349 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
351 rockchip,clkops-idx =
352 <CLKOPS_RATE_MUX_DIV>;
357 clk_nandc: clk_nandc_mux {
358 compatible = "rockchip,rk3188-mux-con";
359 rockchip,bits = <14 1>;
360 clocks = <&clk_cpll>, <&clk_gpll>;
361 clock-output-names = "clk_nandc";
363 #clock-init-cells = <1>;
370 clk_sel_con3: sel-con@0050 {
371 compatible = "rockchip,rk3188-selcon";
373 #address-cells = <1>;
376 clk_i2s1_pll_div: clk_i2s1_pll_div {
377 compatible = "rockchip,rk3188-div-con";
378 rockchip,bits = <0 7>;
379 clocks = <&clk_i2s1_pll>;
380 clock-output-names = "clk_i2s1_pll";
381 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
383 rockchip,clkops-idx =
384 <CLKOPS_RATE_MUX_DIV>;
385 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
390 clk_i2s1: clk_i2s1_mux {
391 compatible = "rockchip,rk3188-mux-con";
392 rockchip,bits = <8 2>;
393 clocks = <&clk_i2s1_pll_div>, <&i2s1_frac>, <&i2s_clkin>, <&xin12m>;
394 clock-output-names = "clk_i2s1";
396 rockchip,clkops-idx =
397 <CLKOPS_RATE_RK3288_I2S>;
398 rockchip,flags = <CLK_SET_RATE_PARENT>;
401 /* 11:10: reserved */
403 clk_i2s1_out: clk_i2s1_out_mux {
404 compatible = "rockchip,rk3188-mux-con";
405 rockchip,bits = <12 1>;
406 clocks = <&clk_i2s1>, <&xin12m>;
407 clock-output-names = "i2s_clkout";
411 /* 14:13: reserved */
413 clk_i2s1_pll: i2s1_pll_mux {
414 compatible = "rockchip,rk3188-mux-con";
415 rockchip,bits = <15 1>;
416 clocks = <&clk_cpll>,<&clk_gpll>;
417 clock-output-names = "clk_i2s1_pll";
419 #clock-init-cells = <1>;
424 clk_sel_con4: sel-con@0054 {
425 compatible = "rockchip,rk3188-selcon";
427 #address-cells = <1>;
430 testclk_div: testclk_div {
431 compatible = "rockchip,rk3188-div-con";
432 rockchip,bits = <0 5>;
434 clock-output-names = "testclk";
435 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
437 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
442 clk_24m_div: clk_24m_div {
443 compatible = "rockchip,rk3188-div-con";
444 rockchip,bits = <8 5>;
446 clock-output-names = "clk_24m";
447 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
449 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
456 clk_sel_con5: sel-con@0058 {
457 compatible = "rockchip,rk3188-selcon";
459 #address-cells = <1>;
462 clk_mac_pll_div: clk_mac_pll_div {
463 compatible = "rockchip,rk3188-div-con";
464 rockchip,bits = <0 5>;
465 clocks = <&clk_mac_pll>;
466 clock-output-names = "clk_mac_pll";
467 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
469 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
472 clk_mac: clk_mac_mux {
473 compatible = "rockchip,rk3188-mux-con";
474 rockchip,bits = <5 1>;
475 clocks = <&clk_mac_pll>, <&rmii_clkin>;
476 clock-output-names = "clk_mac";
478 rockchip,flags = <CLK_SET_RATE_PARENT>;
479 #clock-init-cells = <1>;
484 clk_mac_pll: clk_mac_pll_mux {
485 compatible = "rockchip,rk3188-mux-con";
486 rockchip,bits = <7 1>;
487 clocks = <&clk_cpll>, <&clk_gpll>;
488 clock-output-names = "clk_mac_pll";
492 clk_gmac_div: clk_gmac_div {
493 compatible = "rockchip,rk3188-div-con";
494 rockchip,bits = <8 5>;
495 clocks = <&clk_gmac>;
496 clock-output-names = "clk_gmac";
497 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
499 rockchip,clkops-idx =
500 <CLKOPS_RATE_MUX_DIV>;
505 clk_gmac: clk_gmac_mux {
506 compatible = "rockchip,rk3188-mux-con";
507 rockchip,bits = <15 1>;
508 clocks = <&clk_cpll>, <&clk_gpll>;
509 clock-output-names = "clk_gmac";
511 #clock-init-cells = <1>;
516 clk_sel_con6: sel-con@005c {
517 compatible = "rockchip,rk3188-selcon";
519 #address-cells = <1>;
522 spdif_div: spdif_div {
523 compatible = "rockchip,rk3188-div-con";
524 rockchip,bits = <0 7>;
525 clocks = <&clk_spdif_pll>;
526 clock-output-names = "clk_spdif_pll";
527 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
529 rockchip,clkops-idx =
530 <CLKOPS_RATE_MUX_DIV>;
531 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
536 clk_spdif: spdif_mux {
537 compatible = "rockchip,rk3188-mux-con";
538 rockchip,bits = <8 2>;
539 clocks = <&spdif_div>, <&spdif_frac>, <&xin12m>;
540 clock-output-names = "clk_spdif";
542 rockchip,clkops-idx =
543 <CLKOPS_RATE_RK3288_I2S>;
544 rockchip,flags = <CLK_SET_RATE_PARENT>;
549 clk_spdif_pll: spdif_pll_mux {
550 compatible = "rockchip,rk3188-mux-con";
551 rockchip,bits = <15 1>;
552 clocks = <&clk_cpll>,<&clk_gpll>;
553 clock-output-names = "clk_spdif_pll";
555 #clock-init-cells = <1>;
560 clk_sel_con7: sel-con@0060 {
561 compatible = "rockchip,rk3188-selcon";
563 #address-cells = <1>;
566 i2s1_frac: i2s1_frac {
567 compatible = "rockchip,rk3188-frac-con";
568 clocks = <&clk_i2s1_pll_div>;
569 clock-output-names = "i2s1_frac";
570 /* numerator denominator */
571 rockchip,bits = <0 32>;
572 rockchip,clkops-idx =
579 clk_sel_con8: sel-con@0064 {
580 compatible = "rockchip,rk3188-selcon";
582 #address-cells = <1>;
585 i2s0_frac: i2s0_frac {
586 compatible = "rockchip,rk3188-frac-con";
587 clocks = <&clk_i2s0_pll_div>;
588 clock-output-names = "i2s0_frac";
589 /* numerator denominator */
590 rockchip,bits = <0 32>;
591 rockchip,clkops-idx =
598 clk_sel_con9: sel-con@0068 {
599 compatible = "rockchip,rk3188-selcon";
601 #address-cells = <1>;
604 clk_i2s0_pll_div: clk_i2s0_pll_div {
605 compatible = "rockchip,rk3188-div-con";
606 rockchip,bits = <0 7>;
607 clocks = <&clk_i2s0_pll>;
608 clock-output-names = "clk_i2s0_pll";
609 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
611 rockchip,clkops-idx =
612 <CLKOPS_RATE_MUX_DIV>;
613 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
618 clk_i2s0: clk_i2s0_mux {
619 compatible = "rockchip,rk3188-mux-con";
620 rockchip,bits = <8 2>;
621 clocks = <&clk_i2s0_pll_div>, <&i2s0_frac>, <&i2s_clkin>, <&xin12m>;
622 clock-output-names = "clk_i2s0";
624 rockchip,clkops-idx =
625 <CLKOPS_RATE_RK3288_I2S>;
626 rockchip,flags = <CLK_SET_RATE_PARENT>;
629 /* 14:10: reserved */
631 clk_i2s0_pll: i2s0_pll_mux {
632 compatible = "rockchip,rk3188-mux-con";
633 rockchip,bits = <15 1>;
634 clocks = <&clk_cpll>,<&clk_gpll>;
635 clock-output-names = "clk_i2s0_pll";
637 #clock-init-cells = <1>;
642 clk_sel_con10: sel-con@006c {
643 compatible = "rockchip,rk3188-selcon";
645 #address-cells = <1>;
648 aclk_peri_div: aclk_peri_div {
649 compatible = "rockchip,rk3188-div-con";
650 rockchip,bits = <0 5>;
651 clocks = <&aclk_peri>;
652 clock-output-names = "aclk_peri";
653 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
655 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
660 hclk_peri: hclk_peri_div {
661 compatible = "rockchip,rk3188-div-con";
662 rockchip,bits = <8 2>;
663 clocks = <&aclk_peri>;
664 clock-output-names = "hclk_peri";
665 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
666 rockchip,div-relations =
671 #clock-init-cells = <1>;
674 aclk_peri: aclk_peri_mux {
675 compatible = "rockchip,rk3188-mux-con";
676 rockchip,bits = <10 2>;
677 clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>;
678 clock-output-names = "aclk_peri";
680 #clock-init-cells = <1>;
683 pclk_peri: pclk_peri_div {
684 compatible = "rockchip,rk3188-div-con";
685 rockchip,bits = <12 2>;
686 clocks = <&aclk_peri>;
687 clock-output-names = "pclk_peri";
688 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
689 rockchip,div-relations =
695 #clock-init-cells = <1>;
702 clk_sel_con11: sel-con@0070 {
703 compatible = "rockchip,rk3188-selcon";
705 #address-cells = <1>;
708 clk_sdmmc0_div: clk_sdmmc0_div {
709 compatible = "rockchip,rk3188-div-con";
710 rockchip,bits = <0 8>;
711 clocks = <&clk_sdmmc0>;
712 clock-output-names = "clk_sdmmc0";
713 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
715 rockchip,clkops-idx =
716 <CLKOPS_RATE_MUX_EVENDIV>;
719 clk_sdmmc0: clk_sdmmc0_mux {
720 compatible = "rockchip,rk3188-mux-con";
721 rockchip,bits = <8 2>;
722 clocks = <&clk_cpll>,<&clk_gpll>,<&xin24m>,<&usb480m>;
723 clock-output-names = "clk_sdmmc0";
725 #clock-init-cells = <1>;
728 clk_sdio: clk_sdio_mux {
729 compatible = "rockchip,rk3188-mux-con";
730 rockchip,bits = <10 2>;
731 clocks = <&clk_cpll>,<&clk_gpll>,<&xin24m>,<&usb480m>;
732 clock-output-names = "clk_sdio";
734 #clock-init-cells = <1>;
737 clk_emmc: clk_emmc_mux {
738 compatible = "rockchip,rk3188-mux-con";
739 rockchip,bits = <12 2>;
740 clocks = <&clk_cpll>,<&clk_gpll>,<&xin24m>,<&usb480m>;
741 clock-output-names = "clk_emmc";
743 #clock-init-cells = <1>;
750 clk_sel_con12: sel-con@0074 {
751 compatible = "rockchip,rk3188-selcon";
753 #address-cells = <1>;
756 clk_sdio_div: clk_sdio_div {
757 compatible = "rockchip,rk3188-div-con";
758 rockchip,bits = <0 8>;
759 clocks = <&clk_sdio>;
760 clock-output-names = "clk_sdio";
761 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
763 rockchip,clkops-idx =
764 <CLKOPS_RATE_MUX_EVENDIV>;
767 clk_emmc_div: clk_emmc_div {
768 compatible = "rockchip,rk3188-div-con";
769 rockchip,bits = <8 8>;
770 clocks = <&clk_emmc>;
771 clock-output-names = "clk_emmc";
772 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
774 rockchip,clkops-idx =
775 <CLKOPS_RATE_MUX_EVENDIV>;
780 clk_sel_con13: sel-con@0078 {
781 compatible = "rockchip,rk3188-selcon";
783 #address-cells = <1>;
786 clk_uart0_pll_div: clk_uart0_pll_div {
787 compatible = "rockchip,rk3188-div-con";
788 rockchip,bits = <0 7>;
789 clocks = <&clk_uart0_pll>;
790 clock-output-names = "clk_uart0_pll";
791 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
797 clk_uart0: clk_uart0_mux {
798 compatible = "rockchip,rk3188-mux-con";
799 rockchip,bits = <8 2>;
800 clocks = <&clk_uart0_pll_div>, <&uart0_frac>, <&xin24m>;
801 clock-output-names = "clk_uart0";
803 rockchip,clkops-idx =
804 <CLKOPS_RATE_RK3288_I2S>;
805 rockchip,flags = <CLK_SET_RATE_PARENT>;
810 clk_uart0_pll: clk_uart0_pll_mux {
811 compatible = "rockchip,rk3188-mux-con";
812 rockchip,bits = <12 2>;
813 clocks = <&clk_cpll>, <&clk_gpll>, <&usb480m>;
814 clock-output-names = "clk_uart0_pll";
816 #clock-init-cells = <1>;
823 clk_sel_con14: sel-con@007c {
824 compatible = "rockchip,rk3188-selcon";
826 #address-cells = <1>;
829 clk_uart1_pll_div: clk_uart1_pll_div {
830 compatible = "rockchip,rk3188-div-con";
831 rockchip,bits = <0 7>;
832 clocks = <&clk_uart1_pll>;
833 clock-output-names = "clk_uart1_pll";
834 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
840 clk_uart1: clk_uart1_mux {
841 compatible = "rockchip,rk3188-mux-con";
842 rockchip,bits = <8 2>;
843 clocks = <&clk_uart1_pll_div>, <&uart1_frac>, <&xin24m>;
844 clock-output-names = "clk_uart1";
846 rockchip,clkops-idx =
847 <CLKOPS_RATE_RK3288_I2S>;
848 rockchip,flags = <CLK_SET_RATE_PARENT>;
853 clk_uart1_pll: clk_uart1_pll_mux {
854 compatible = "rockchip,rk3188-mux-con";
855 rockchip,bits = <12 2>;
856 clocks = <&clk_cpll>, <&clk_gpll>, <&usb480m>;
857 clock-output-names = "clk_uart1_pll";
859 #clock-init-cells = <1>;
865 clk_sel_con15: sel-con@0080 {
866 compatible = "rockchip,rk3188-selcon";
868 #address-cells = <1>;
871 clk_uart2_pll_div: clk_uart2_pll_div {
872 compatible = "rockchip,rk3188-div-con";
873 rockchip,bits = <0 7>;
874 clocks = <&clk_uart2_pll>;
875 clock-output-names = "clk_uart2_pll";
876 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
882 clk_uart2: clk_uart2_mux {
883 compatible = "rockchip,rk3188-mux-con";
884 rockchip,bits = <8 2>;
885 clocks = <&clk_uart2_pll>, <&uart2_frac>, <&xin24m>;
886 clock-output-names = "clk_uart2";
888 rockchip,clkops-idx =
889 <CLKOPS_RATE_RK3288_I2S>;
890 rockchip,flags = <CLK_SET_RATE_PARENT>;
895 clk_uart2_pll: clk_uart2_pll_mux {
896 compatible = "rockchip,rk3188-mux-con";
897 rockchip,bits = <12 2>;
898 clocks = <&clk_cpll>, <&clk_gpll>, <&usb480m>;
899 clock-output-names = "clk_uart2_pll";
901 #clock-init-cells = <1>;
908 clk_sel_con16: sel-con@0084 {
909 compatible = "rockchip,rk3188-selcon";
911 #address-cells = <1>;
914 i2s2_pll_div: i2s2_pll_div {
915 compatible = "rockchip,rk3188-div-con";
916 rockchip,bits = <0 7>;
917 clocks = <&clk_i2s2_pll>;
918 clock-output-names = "clk_i2s2_pll";
919 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
921 rockchip,clkops-idx =
922 <CLKOPS_RATE_MUX_DIV>;
923 rockchip,flags = <CLK_SET_RATE_NO_REPARENT>;
928 clk_i2s2: clk_i2s2_mux {
929 compatible = "rockchip,rk3188-mux-con";
930 rockchip,bits = <8 2>;
931 clocks = <&i2s2_pll_div>, <&i2s2_frac>, <&i2s_clkin>, <&xin12m>;
932 clock-output-names = "clk_i2s2";
934 rockchip,clkops-idx =
935 <CLKOPS_RATE_RK3288_I2S>;
936 rockchip,flags = <CLK_SET_RATE_PARENT>;
939 /* 14:10: reserved */
941 clk_i2s2_pll: i2s2_pll_mux {
942 compatible = "rockchip,rk3188-mux-con";
943 rockchip,bits = <15 1>;
944 clocks = <&clk_cpll>,<&clk_gpll>;
945 clock-output-names = "clk_i2s2_pll";
947 #clock-init-cells = <1>;
952 clk_sel_con17: sel-con@0088 {
953 compatible = "rockchip,rk3188-selcon";
955 #address-cells = <1>;
958 uart0_frac: uart0_frac {
959 compatible = "rockchip,rk3188-frac-con";
960 clocks = <&clk_uart0_pll_div>;
961 clock-output-names = "uart0_frac";
962 /* numerator denominator */
963 rockchip,bits = <0 32>;
964 rockchip,clkops-idx =
971 clk_sel_con18: sel-con@008c {
972 compatible = "rockchip,rk3188-selcon";
974 #address-cells = <1>;
977 uart1_frac: uart1_frac {
978 compatible = "rockchip,rk3188-frac-con";
979 clocks = <&clk_uart1_pll_div>;
980 clock-output-names = "uart1_frac";
981 /* numerator denominator */
982 rockchip,bits = <0 32>;
983 rockchip,clkops-idx =
990 clk_sel_con19: sel-con@0090 {
991 compatible = "rockchip,rk3188-selcon";
993 #address-cells = <1>;
996 uart2_frac: uart2_frac {
997 compatible = "rockchip,rk3188-frac-con";
998 clocks = <&clk_uart2_pll_div>;
999 clock-output-names = "uart2_frac";
1000 /* numerator denominator */
1001 rockchip,bits = <0 32>;
1002 rockchip,clkops-idx =
1009 clk_sel_con20: sel-con@0094 {
1010 compatible = "rockchip,rk3188-selcon";
1012 #address-cells = <1>;
1015 spdif_frac: spdif_frac {
1016 compatible = "rockchip,rk3188-frac-con";
1017 clocks = <&spdif_div>;
1018 clock-output-names = "spdif_frac";
1019 /* numerator denominator */
1020 rockchip,bits = <0 32>;
1021 rockchip,clkops-idx =
1028 clk_sel_con21: sel-con@0098 {
1029 compatible = "rockchip,rk3188-selcon";
1031 #address-cells = <1>;
1034 clk_hdmi_cec: clk_hdmi_cec_div {
1035 compatible = "rockchip,rk3188-div-con";
1036 rockchip,bits = <0 14>;
1038 clock-output-names = "clk_hdmi_cec";
1039 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1041 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1044 clk_hdmi_cec_div: clk_hdmi_cec_div {
1045 compatible = "rockchip,rk3188-div-con";
1046 rockchip,bits = <0 14>;
1047 clocks = <&clk_hdmi_cec>;
1048 clock-output-names = "clk_hdmi_cec";
1049 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1051 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1054 clk_hdmi_cec: clk_hdmi_cec_mux {
1055 compatible = "rockchip,rk3188-mux-con";
1056 rockchip,bits = <14 2>;
1057 clocks = <&dummy>, <&dummy>, <&xin24m>;
1058 clock-output-names = "clk_hdmi_cec";
1064 clk_sel_con22: sel-con@009c {
1065 compatible = "rockchip,rk3188-selcon";
1067 #address-cells = <1>;
1070 clk_rga: clk_rga_div {
1071 compatible = "rockchip,rk3188-div-con";
1072 rockchip,bits = <0 5>;
1073 clocks = <&aclk_rga>;
1074 clock-output-names = "clk_rga";
1075 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1077 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1082 clk_tsp_div: clk_tsp_div {
1083 compatible = "rockchip,rk3188-div-con";
1084 rockchip,bits = <8 5>;
1085 clocks = <&clk_tsp>;
1086 clock-output-names = "clk_tsp";
1087 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1089 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1092 /* 14:13 reserved */
1094 clk_tsp: clk_tsp_mux {
1095 compatible = "rockchip,rk3188-mux-con";
1096 rockchip,bits = <15 1>;
1097 clocks = <&clk_cpll>, <&clk_gpll>;
1098 clock-output-names = "clk_tsp";
1104 clk_sel_con23: sel-con@00a0 {
1105 compatible = "rockchip,rk3188-selcon";
1107 #address-cells = <1>;
1110 clk_wifi_div: clk_wifi_div {
1111 compatible = "rockchip,rk3188-div-con";
1112 rockchip,bits = <0 5>;
1113 clocks = <&clk_wifi>;
1114 clock-output-names = "clk_wifi";
1115 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1117 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1120 clk_wifi: clk_wifi_mux {
1121 compatible = "rockchip,rk3188-mux-con";
1122 rockchip,bits = <5 2>;
1123 clocks = <&clk_cpll>, <&clk_gpll>, <&usb480m>;
1124 clock-output-names = "clk_wifi";
1130 clk_hdcp_div: clk_hdcp_div {
1131 compatible = "rockchip,rk3188-div-con";
1132 rockchip,bits = <8 6>;
1133 clocks = <&clk_hdcp>;
1134 clock-output-names = "clk_hdcp";
1135 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1137 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1140 clk_hdcp: clk_hdcp_mux {
1141 compatible = "rockchip,rk3188-mux-con";
1142 rockchip,bits = <14 2>;
1143 clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>;
1144 clock-output-names = "clk_hdcp";
1150 clk_sel_con24: sel-con@00a4 {
1151 compatible = "rockchip,rk3188-selcon";
1153 #address-cells = <1>;
1156 clk_crypto_div: clk_crypto_div {
1157 compatible = "rockchip,rk3188-div-con";
1158 rockchip,bits = <0 5>;
1159 clocks = <&clk_crypto>;
1160 clock-output-names = "clk_crypto";
1161 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1163 #clock-init-cells = <1>;
1166 clk_crypto: clk_crypto_mux {
1167 compatible = "rockchip,rk3188-mux-con";
1168 rockchip,bits = <5 1>;
1169 clocks = <&clk_cpll>, <&clk_gpll>;
1170 clock-output-names = "clk_crypto";
1174 clk_tsadc: clk_tsadc_div {
1175 compatible = "rockchip,rk3188-div-con";
1176 rockchip,bits = <6 10>;
1178 clock-output-names = "clk_tsadc";
1179 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1181 #clock-init-cells = <1>;
1186 clk_sel_con25: sel-con@00a8 {
1187 compatible = "rockchip,rk3188-selcon";
1189 #address-cells = <1>;
1192 clk_spi0_div: clk_spi0_div {
1193 compatible = "rockchip,rk3188-div-con";
1194 rockchip,bits = <0 7>;
1195 clocks = <&clk_spi0>;
1196 clock-output-names = "clk_spi0";
1197 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1199 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1204 clk_spi0: clk_spi0_mux {
1205 compatible = "rockchip,rk3188-mux-con";
1206 rockchip,bits = <8 1>;
1207 clocks = <&clk_cpll>, <&clk_gpll>;
1208 clock-output-names = "clk_spi0";
1216 clk_sel_con26: sel-con@00ac {
1217 compatible = "rockchip,rk3188-selcon";
1219 #address-cells = <1>;
1222 clk_ddr_div: clk_ddr_div {
1223 compatible = "rockchip,rk3188-div-con";
1224 rockchip,bits = <0 2>;
1225 clocks = <&clk_ddr>;
1226 clock-output-names = "clk_ddr";
1227 rockchip,div-type = <CLK_DIVIDER_USER_DEFINE>;
1228 rockchip,div-relations =
1233 rockchip,flags = <(CLK_GET_RATE_NOCACHE |
1234 CLK_SET_RATE_NO_REPARENT)>;
1235 rockchip,clkops-idx = <CLKOPS_RATE_DDR_DIV2>;
1240 clk_ddr: clk_ddr_pll_mux {
1241 compatible = "rockchip,rk3188-mux-con";
1242 rockchip,bits = <8 2>;
1243 clocks = <&clk_dpll>, <&clk_gpll>, <&clk_apll>;
1244 clock-output-names = "clk_ddr";
1248 /* 15:10 reserved */
1252 clk_sel_con27: sel-con@00b0 {
1253 compatible = "rockchip,rk3188-selcon";
1255 #address-cells = <1>;
1258 dclk_vop0_pll: dclk_vop0_pll_mux {
1259 compatible = "rockchip,rk3188-mux-con";
1260 rockchip,bits = <0 1>;
1261 clocks = <&clk_gpll>, <&clk_cpll>;
1262 clock-output-names = "dclk_vop0_pll";
1264 #clock-init-cells = <1>;
1267 dclk_vop0: dclk_vop0_mux {
1268 compatible = "rockchip,rk3188-mux-con";
1269 rockchip,bits = <1 1>;
1270 clocks = <&hdmi_phy_clk>, <&dummy>;/*dclk_vop0_div*/
1271 clock-output-names = "dclk_vop0";
1273 #clock-init-cells = <1>;
1278 dclk_vop0_div: dclk_vop0_div {
1279 compatible = "rockchip,rk3188-div-con";
1280 rockchip,bits = <8 8>;
1281 clocks = <&dclk_vop0_pll>;
1282 clock-output-names = "dclk_vop0";
1283 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1285 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1290 clk_sel_con28: sel-con@00b4 {
1291 compatible = "rockchip,rk3188-selcon";
1293 #address-cells = <1>;
1296 aclk_rkvdec_div: aclk_rkvdec_div {
1297 compatible = "rockchip,rk3188-div-con";
1298 rockchip,bits = <0 5>;
1299 clocks = <&aclk_rkvdec>;
1300 clock-output-names = "aclk_rkvdec";
1301 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1303 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1308 aclk_rkvdec: aclk_rkvdec_mux {
1309 compatible = "rockchip,rk3188-mux-con";
1310 rockchip,bits = <6 2>;
1311 clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
1312 clock-output-names = "aclk_rkvdec";
1314 #clock-init-cells = <1>;
1317 clk_vdec_cabac_div: clk_vdec_cabac_div {
1318 compatible = "rockchip,rk3188-div-con";
1319 rockchip,bits = <8 5>;
1320 clocks = <&clk_vdec_cabac>;
1321 clock-output-names = "clk_vdec_cabac";
1322 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1324 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1329 clk_vdec_cabac: clk_vdec_cabac_mux {
1330 compatible = "rockchip,rk3188-mux-con";
1331 rockchip,bits = <14 2>;
1332 clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
1333 clock-output-names = "clk_vdec_cabac";
1335 #clock-init-cells = <1>;
1339 clk_sel_con29: sel-con@00b8 {
1340 compatible = "rockchip,rk3188-selcon";
1342 #address-cells = <1>;
1345 dclk_hdmiphy_div: dclk_hdmiphy_div {
1346 compatible = "rockchip,rk3188-div-con";
1347 rockchip,bits = <0 3>;
1348 clocks = <&dclk_vop0_pll>;
1349 clock-output-names = "dclk_hdmiphy";
1350 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1352 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1357 clk_macphy_div: clk_macphy_div {
1358 compatible = "rockchip,rk3188-div-con";
1359 rockchip,bits = <8 3>;
1360 clocks = <&clk_macphy>;
1361 clock-output-names = "clk_macphy";
1362 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1364 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1367 rmii_clkin: rmii_clkin {
1368 compatible = "rockchip,rk3188-mux-con";
1369 rockchip,bits = <10 1>;
1370 clocks = <&gmac_clkin>, <&phy_50m_out>;
1371 clock-output-names = "rmii_clkin";
1373 #clock-init-cells = <1>;
1376 clk_mac_tx: clk_mac_tx {
1377 compatible = "rockchip,rk3188-mux-con";
1378 rockchip,bits = <11 1>;
1379 clocks = <&clk_gates5 6>, <&phy_tx_out>;
1380 clock-output-names = "clk_mac_tx";
1382 #clock-init-cells = <1>;
1385 clk_macphy: clk_macphy_mux {
1386 compatible = "rockchip,rk3188-mux-con";
1387 rockchip,bits = <12 1>;
1388 clocks = <&clk_mac_pll_div>, <&gmac_clkin>;
1389 clock-output-names = "clk_macphy";
1391 #clock-init-cells = <1>;
1394 /* 15:13 reserved */
1398 clk_sel_con30: sel-con@00bc {
1399 compatible = "rockchip,rk3188-selcon";
1401 #address-cells = <1>;
1404 i2s2_frac: i2s2_frac {
1405 compatible = "rockchip,rk3188-frac-con";
1406 clocks = <&i2s2_pll_div>;
1407 clock-output-names = "i2s2_frac";
1408 /* numerator denominator */
1409 rockchip,bits = <0 32>;
1410 rockchip,clkops-idx =
1416 clk_sel_con31: sel-con@00c0 {
1417 compatible = "rockchip,rk3188-selcon";
1419 #address-cells = <1>;
1422 aclk_iep_div: aclk_iep_div {
1423 compatible = "rockchip,rk3188-div-con";
1424 rockchip,bits = <0 5>;
1425 clocks = <&aclk_iep>;
1426 clock-output-names = "aclk_iep";
1427 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1429 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1432 aclk_iep: aclk_iep_mux {
1433 compatible = "rockchip,rk3188-mux-con";
1434 rockchip,bits = <5 2>;
1435 clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
1436 clock-output-names = "aclk_iep";
1438 #clock-init-cells = <1>;
1443 aclk_hdcp_div: aclk_hdcp_div {
1444 compatible = "rockchip,rk3188-div-con";
1445 rockchip,bits = <8 5>;
1446 clocks = <&aclk_hdcp>;
1447 clock-output-names = "aclk_hdcp";
1448 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1450 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1453 aclk_hdcp: aclk_hdcp_mux {
1454 compatible = "rockchip,rk3188-mux-con";
1455 rockchip,bits = <13 2>;
1456 clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
1457 clock-output-names = "aclk_hdcp";
1464 clk_sel_con32: sel-con@00c4 {
1465 compatible = "rockchip,rk3188-selcon";
1467 #address-cells = <1>;
1470 aclk_vpu_div: aclk_vpu_div {
1471 compatible = "rockchip,rk3188-div-con";
1472 rockchip,bits = <0 5>;
1473 clocks = <&aclk_vpu>;
1474 clock-output-names = "aclk_vpu";
1475 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1477 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1480 aclk_vpu: aclk_vpu_mux {
1481 compatible = "rockchip,rk3188-mux-con";
1482 rockchip,bits = <5 2>;
1483 clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
1484 clock-output-names = "aclk_vpu";
1486 #clock-init-cells = <1>;
1493 clk_sel_con33: sel-con@00c8 {
1494 compatible = "rockchip,rk3188-selcon";
1496 #address-cells = <1>;
1499 aclk_vop_div: aclk_vop_div {
1500 compatible = "rockchip,rk3188-div-con";
1501 rockchip,bits = <0 5>;
1502 clocks = <&aclk_vop>;
1503 clock-output-names = "aclk_vop";
1504 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1506 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1509 aclk_vop: aclk_vop_mux {
1510 compatible = "rockchip,rk3188-mux-con";
1511 rockchip,bits = <5 2>;
1512 clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
1513 clock-output-names = "aclk_vop";
1515 #clock-init-cells = <1>;
1520 aclk_rga_div: aclk_rga_div {
1521 compatible = "rockchip,rk3188-div-con";
1522 rockchip,bits = <8 5>;
1523 clocks = <&aclk_rga>;
1524 clock-output-names = "aclk_rga";
1525 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1527 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1530 aclk_rga: aclk_rga_mux {
1531 compatible = "rockchip,rk3188-mux-con";
1532 rockchip,bits = <13 2>;
1533 clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
1534 clock-output-names = "aclk_rga";
1536 #clock-init-cells = <1>;
1543 clk_sel_con34: sel-con@00cc {
1544 compatible = "rockchip,rk3188-selcon";
1546 #address-cells = <1>;
1549 clk_gpu_div: clk_gpu_div {
1550 compatible = "rockchip,rk3188-div-con";
1551 rockchip,bits = <0 5>;
1552 clocks = <&clk_gpu>;
1553 clock-output-names = "clk_gpu";
1554 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1556 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1559 clk_gpu: clk_gpu_mux {
1560 compatible = "rockchip,rk3188-mux-con";
1561 rockchip,bits = <5 2>;
1562 clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
1563 clock-output-names = "clk_gpu";
1565 #clock-init-cells = <1>;
1570 clk_vdec_core_div: clk_vdec_core_div {
1571 compatible = "rockchip,rk3188-div-con";
1572 rockchip,bits = <8 5>;
1573 clocks = <&clk_vdec_core>;
1574 clock-output-names = "clk_vdec_core";
1575 rockchip,div-type = <CLK_DIVIDER_PLUS_ONE>;
1577 rockchip,clkops-idx = <CLKOPS_RATE_MUX_DIV>;
1580 clk_vdec_core: clk_vdec_core_mux {
1581 compatible = "rockchip,rk3188-mux-con";
1582 rockchip,bits = <13 2>;
1583 clocks = <&clk_cpll>, <&clk_gpll>, <&hdmi_phy_clk>, <&usb480m>;
1584 clock-output-names = "clk_vdec_core";
1586 #clock-init-cells = <1>;
1593 clk_sel_con35: sel-con@0134 {
1594 compatible = "rockchip,rk3188-selcon";
1596 #address-cells = <1>;
1601 testclk: testclk_mux {
1602 compatible = "rockchip,rk3188-mux-con";
1603 rockchip,bits = <8 4>;
1604 clocks = <&clk_wifi>, <&dummy>, <&clk_core>, <&clk_gates7 0>, <&aclk_iep>, <&clk_gpu>, <&aclk_peri>, <&aclk_core>;
1605 clock-output-names = "testclk";
1607 #clock-init-cells = <1>;
1612 hdmi_phy_clk: hdmi_phy_clk_mux {
1613 compatible = "rockchip,rk3188-mux-con";
1614 rockchip,bits = <13 1>;
1615 clocks = <&hdmiphy_out>, <&xin24m>;
1616 clock-output-names = "hdmi_phy_clk";
1618 #clock-init-cells = <1>;
1621 usb480m_phy: usb480m_phy_mux {
1622 compatible = "rockchip,rk3188-mux-con";
1623 rockchip,bits = <14 1>;
1624 clocks = <&usbphy0_480m>, <&usbphy1_480m>;
1625 clock-output-names = "usb480m_phy";
1627 #clock-init-cells = <1>;
1630 usb480m: usb480m_mux {
1631 compatible = "rockchip,rk3188-mux-con";
1632 rockchip,bits = <15 1>;
1633 clocks = <&usb480m_phy>, <&xin24m>;
1634 clock-output-names = "usb480m";
1636 rockchip,clkops-idx =
1637 <CLKOPS_RATE_RK3288_USB480M>;
1638 #clock-init-cells = <1>;
1642 /* Gate control regs */
1644 compatible = "rockchip,rk-gate-cons";
1645 #address-cells = <1>;
1648 clk_gates0: gate-clk@00d0 {
1649 compatible = "rockchip,rk3188-gate-clk";
1653 <&dummy>, <&clk_i2s0_pll>,
1655 <&i2s0_frac>, <&clk_i2s0>,
1656 <&dummy>, <&clk_i2s2_pll>,
1658 <&i2s2_frac>, <&clk_i2s2>,
1659 <&clk_i2s1_pll>, <&i2s1_frac>,
1661 <&dummy>, <&clk_i2s1_out>,
1662 <&clk_i2s1>, <&testclk>;
1664 clock-output-names =
1665 "reserved", "reserved",
1666 "reserved", "clk_i2s0_pll",
1668 "i2s0_frac", "i2s0_8ch",
1669 "reserved", "clk_i2s2_pll",
1671 "i2s2_frac", "i2s2_2ch",
1672 "clk_i2s1_pll", "i2s1_frac",
1674 "reserved", "i2s_clkout",
1675 "i2s1_8ch", "testclk";
1680 clk_gates1: gate-clk@00d4 {
1681 compatible = "rockchip,rk3188-gate-clk";
1684 <&clk_nandc>, <&aclk_vop>,
1685 <&aclk_rga>, <&jtag_clkin>,
1687 <&aclk_hdcp>, <&xin24m>,
1688 <&xin24m>, <&clk_mac_pll>,
1690 <&clk_uart0_pll>, <&uart0_frac>,
1691 <&clk_uart1_pll>, <&uart1_frac>,
1693 <&clk_uart2_pll>, <&uart2_frac>,
1696 clock-output-names =
1697 "clk_nandc", "aclk_vop",
1698 "aclk_rga", "clk_jtag",
1700 "aclk_hdcp", "clk_otgphy0",
1701 "clk_otgphy1", "clk_mac_pll",
1703 "clk_uart0_pll", "uart0_frac",
1704 "clk_uart1_pll", "uart1_frac",
1706 "clk_uart2_pll", "uart2_frac",
1707 "reserved", "reserved";
1712 clk_gates2: gate-clk@00d8 {
1713 compatible = "rockchip,rk3188-gate-clk";
1717 <&clk_gmac>, <&dummy>,
1720 <&clk_tsp>, <&clk_crypto>,
1722 <&clk_tsadc>, <&clk_spi0>,
1723 <&clk_spdif_pll>, <&clk_sdmmc0>,
1725 <&spdif_frac>, <&clk_sdio>,
1726 <&clk_emmc>, <&clk_wifi>;
1728 clock-output-names =
1729 "reserved", "clk_ddrmon",
1730 "clk_gmac", "reserved",
1732 "reserved", "reserved",
1733 "clk_tsp", "clk_crypto",
1735 "clk_tsadc", "clk_spi0",
1736 "clk_spdif_pll", "clk_sdmmc0",
1738 "spdif_frac", "clk_sdio",
1739 "clk_emmc", "clk_wifi";
1744 clk_gates3: gate-clk@00dc {
1745 compatible = "rockchip,rk3188-gate-clk";
1748 <&aclk_iep>, <&dummy>,
1749 <&aclk_rkvdec>, <&clk_vdec_cabac>,
1751 <&clk_vdec_core>, <&clk_hdcp>,
1752 <&aclk_rga>, <&xin24m>,
1754 <&clk_hdmi_cec>, <&dummy>,
1755 <&dummy>, <&aclk_vpu>,
1760 clock-output-names =
1761 "aclk_iep", "dclk_vop0",
1762 "aclk_rkvdec", "clk_vdec_cabac",
1764 "clk_vdec_core", "clk_hdcp",
1765 "clk_rga", "clk_hdmi_hdcp",
1767 "clk_hdmi_cec", "reserved",
1768 "reserved", "aclk_vpu",
1770 "reserved", "reserved",
1771 "reserved", "reserved";
1776 clk_gates4: gate-clk@00e0 {
1777 compatible = "rockchip,rk3188-gate-clk";
1780 <&clk_core>, <&clk_core>,
1781 <&aclk_core>, <&dummy>,
1783 <&aclk_vpu>, <&aclk_rkvdec>,
1792 clock-output-names =
1793 "aclk_core", "pclk_dbg",
1794 "aclk_gic400", "reserved",
1796 "hclk_vpu", "hclk_rkvdec",
1797 "reserved", "reserved",
1799 "reserved", "reserved",
1800 "reserved", "reserved",
1802 "reserved", "reserved",
1803 "reserved", "reserved";
1808 clk_gates5: gate-clk@00e4 {
1809 compatible = "rockchip,rk3188-gate-clk";
1812 <&aclk_peri>, <&aclk_peri>,
1813 <&aclk_peri>, <&clk_mac>,
1815 <&clk_mac>, <&clk_mac>,
1816 <&clk_mac>, <&clk_macphy>,
1824 clock-output-names =
1825 "aclk_peri", "hclk_peri",
1826 "pclk_peri", "clk_mac_ref",
1828 "clk_mac_refout", "clk_mac_rx",
1829 "clk_mac_tx", "clk_macphy",
1831 "reserved", "reserved",
1832 "reserved", "reserved",
1834 "reserved", "reserved",
1835 "reserved", "reserved";
1840 clk_gates6: gate-clk@00e8 {
1841 compatible = "rockchip,rk3188-gate-clk";
1844 <&aclk_bus>, <&aclk_bus>,
1845 <&aclk_bus>, <&pclk_bus>,
1847 <&pclk_bus>, <&xin24m>,
1848 <&xin24m>, <&xin24m>,
1850 <&xin24m>, <&xin24m>,
1851 <&xin24m>, <&dummy>,
1853 <&dummy>, <&pclk_bus>,
1856 clock-output-names =
1857 "aclk_bus", "hclk_bus",
1858 "pclk_bus", "pclk_bus_pre",
1860 "pclk_phy", "clk_timer0",
1861 "clk_timer1", "clk_timer2",
1863 "clk_timer3", "clk_timer4",
1864 "clk_timer5", "reserved",
1866 "reserved", "pclk_ddr",
1867 "reserved", "reserved";
1872 clk_gates7: gate-clk@00ec {
1873 compatible = "rockchip,rk3188-gate-clk";
1876 <&clk_ddr_div>, <&clk_ddr_div>,
1886 <&clk_gpu>, <&clk_gpu>;
1888 clock-output-names =
1889 "clk_ddrphy", "clk4x_ddrphy",
1890 "reserved", "reserved",
1892 "reserved", "reserved",
1893 "reserved", "reserved",
1895 "reserved", "reserved",
1896 "reserved", "reserved",
1898 "reserved", "reserved",
1899 "g_aclk_gpu", "g_aclk_gpu_noc";
1904 clk_gates8: gate-clk@00f0 {
1905 compatible = "rockchip,rk3188-gate-clk";
1908 <&aclk_bus>, <&aclk_bus>,
1909 <&aclk_bus>, <&hclk_bus>,
1911 <&clk_gates6 13>, <&clk_gates7 0>,
1912 <&clk_gates6 13>, <&hclk_bus>,
1914 <&hclk_bus>, <&hclk_bus>,
1915 <&hclk_bus>, <&hclk_bus>,
1917 <&hclk_bus>, <&pclk_bus>,
1918 <&pclk_bus>, <&pclk_bus>;
1920 clock-output-names =
1921 "g_aclk_intmem", "g_intmem_mbist",
1922 "g_aclk_dmac_bus", "g_hclk_rom",
1924 "g_p_ddrupctl", "g_clk_ddrupctl",
1925 "g_p_ddrmon", "g_h_i2s0_8ch",
1927 "g_h_i2s1_8ch", "g_h_i2s2_2ch",
1928 "g_h_spdif_8ch", "g_h_crypto_mst",
1930 "g_h_crypto_slv", "g_p_efuse_1024",
1931 "g_p_efuse_256", "g_pclk_i2c0";
1936 clk_gates9: gate-clk@00f4 {
1937 compatible = "rockchip,rk3188-gate-clk";
1940 <&pclk_bus>, <&pclk_bus>,
1941 <&pclk_bus>, <&dummy>,
1943 <&pclk_bus>, <&pclk_bus>,
1944 <&pclk_bus>, <&pclk_bus>,
1946 <&pclk_bus>, <&pclk_bus>,
1947 <&pclk_bus>, <&pclk_bus>,
1949 <&pclk_bus>, <&pclk_bus>,
1950 <&pclk_bus>, <&pclk_bus>;
1952 clock-output-names =
1953 "g_pclk_i2c1", "g_pclk_i2c2",
1954 "g_pclk_i2c3", "reserved",
1956 "g_pclk_timer0", "g_pclk_stimer",
1957 "g_pclk_spi0", "g_pclk_rk_pwm",
1959 "g_pclk_gpio0", "g_pclk_gpio1",
1960 "g_pclk_gpio2", "g_pclk_gpio3",
1962 "g_pclk_uart0", "g_pclk_uart1",
1963 "g_pclk_uart2", "g_pclk_tsadc";
1968 clk_gates10: gate-clk@00f8 {
1969 compatible = "rockchip,rk3188-gate-clk";
1972 <&pclk_bus>, <&aclk_bus>,
1973 <&clk_gates6 13>, <&clk_gates6 4>,
1975 <&pclk_bus>, <&clk_gates6 4>,
1976 <&pclk_bus>, <&clk_gates6 4>,
1978 <&clk_gates6 4>, <&clk_gates6 4>,
1979 <&pclk_bus>, <&hclk_bus>,
1981 <&clkin_hsadc_tsp>, <&dummy>,
1984 clock-output-names =
1985 "g_pclk_grf", "g_aclk_bus",
1986 "g_p_mschniu", "g_p_ddrphy",
1988 "g_pclk_cru", "g_p_acodecphy",
1989 "g_pclk_sgrf", "g_p_hdmiphy",
1991 "g_p_vdacphy", "g_p_phy_noc",
1992 "g_pclk_sim", "g_hclk_tsp",
1994 "clk_hsadc_tsp", "reserved",
1995 "reserved", "reserved";
2000 clk_gates11: gate-clk@00fc {
2001 compatible = "rockchip,rk3188-gate-clk";
2004 <&hclk_peri>, <&hclk_peri>,
2005 <&hclk_peri>, <&hclk_peri>,
2007 <&aclk_peri>, <&pclk_peri>,
2008 <&hclk_peri>, <&hclk_peri>,
2010 <&hclk_peri>, <&hclk_peri>,
2011 <&hclk_peri>, <&dummy>,
2013 <&hclk_peri>, <&hclk_peri>,
2014 <&hclk_peri>, <&dummy>;
2016 clock-output-names =
2017 "g_hclk_sdmmc", "g_hclk_sdio",
2018 "g_clk_emmc", "g_clk_nandc",
2020 "g_aclk_gmac", "g_pclk_gmac",
2021 "g_hclk_host0", "g_h_host0_arb",
2023 "g_hclk_host1", "g_h_host1_arb",
2024 "g_hclk_host2", "reserved",
2026 "g_hclk_otg", "g_hclk_otg_pmu",
2027 "g_h_host2_arb", "reserved";
2032 clk_gates12: gate-clk@0100 {
2033 compatible = "rockchip,rk3188-gate-clk";
2036 <&aclk_peri>, <&hclk_peri>,
2037 <&pclk_peri>, <&dummy>,
2048 clock-output-names =
2049 "g_a_peri_noc", "g_h_peri_noc",
2050 "g_p_peri_noc", "reserved",
2052 "reserved", "reserved",
2053 "reserved", "reserved",
2055 "reserved", "reserved",
2056 "reserved", "reserved",
2058 "reserved", "reserved",
2059 "reserved", "reserved";
2064 clk_gates13: gate-clk@0104 {
2065 compatible = "rockchip,rk3188-gate-clk";
2068 <&aclk_rga>, <&hclk_vio>,
2069 <&aclk_iep>, <&hclk_vio>,
2071 <&dummy>, <&aclk_vop>,
2072 <&hclk_vio>, <&hclk_vio>,
2074 <&hclk_vio>, <&aclk_iep>,
2075 <&aclk_hdcp>, <&aclk_rga>,
2077 <&aclk_vop>, <&hclk_vio>,
2080 clock-output-names =
2081 "g_aclk_rga", "g_hclk_rga",
2082 "g_aclk_iep", "g_hclk_iep",
2084 "reserved", "g_aclk_vop",
2085 "g_hclk_vop", "g_h_vio_ahbarbi",
2087 "g_h_vio_noc", "g_a_iep_noc",
2088 "g_a_hdcp_noc", "g_a_rga_noc",
2090 "g_a_vop_noc", "g_h_vop_noc",
2091 "reserved", "reserved";
2096 clk_gates14: gate-clk@0108 {
2097 compatible = "rockchip,rk3188-gate-clk";
2104 <&hclk_vio>, <&hclk_vio>,
2107 <&aclk_hdcp>, <&hclk_vio>,
2109 <&hclk_vio>, <&dummy>,
2112 clock-output-names =
2113 "reserved", "reserved",
2114 "reserved", "reserved",
2116 "reserved", "reserved",
2117 "g_p_hdmi_ctrl", "g_h_vio_h2p",
2119 "reserved", "reserved",
2120 "g_aclk_hdcp", "g_pclk_hdcp",
2122 "g_h_hdcp_mmu", "reserved",
2123 "reserved", "reserved";
2128 clk_gates15: gate-clk@010c {
2129 compatible = "rockchip,rk3188-gate-clk";
2132 <&aclk_vpu>, <&hclk_vpu>,
2133 <&aclk_rkvdec>, <&hclk_rkvdec>,
2135 <&aclk_vpu>, <&hclk_vpu>,
2136 <&aclk_rkvdec>, <&hclk_rkvdec>,
2144 clock-output-names =
2145 "g_aclk_vpu", "g_hclk_vpu",
2146 "g_a_rkvdec", "g_h_rkvdec",
2148 "g_a_vpu_noc", "g_h_vpu_noc",
2149 "g_a_rkvdec_noc", "g_h_rkvdec_noc",
2151 "reserved", "reserved",
2152 "reserved", "reserved",
2154 "reserved", "reserved",
2155 "reserved", "reserved";