arch/arm/boot/dts/rk3228.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/rkfb/rk_fb.h>
   3
   4 #include "skeleton.dtsi"
   5 #include "rk3228-clocks.dtsi"
   6
   7 #include <dt-bindings/pinctrl/rockchip.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9
  10 / {
  11         compatible = "rockchip,rk3228";
  12         interrupt-parent = <&gic>;
  13
  14         aliases {
  15                 serial2 = &uart_dbg;
  16         };
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 cpu@0 {
  23                         device_type = "cpu";
  24                         compatible = "arm,cortex-a7";
  25                         reg = <0xf00>;
  26                 };
  27                 cpu@1 {
  28                         device_type = "cpu";
  29                         compatible = "arm,cortex-a7";
  30                         reg = <0xf01>;
  31                 };
  32                 cpu@2 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a7";
  35                         reg = <0xf02>;
  36                 };
  37                 cpu@3 {
  38                         device_type = "cpu";
  39                         compatible = "arm,cortex-a7";
  40                         reg = <0xf03>;
  41                 };
  42         };
  43
  44         gic: interrupt-controller@32010000 {
  45                 compatible = "arm,cortex-a15-gic";
  46                 interrupt-controller;
  47                 #interrupt-cells = <3>;
  48                 #address-cells = <0>;
  49                 reg = <0x32011000 0x1000>,
  50                       <0x32012000 0x1000>;
  51         };
  52
  53         sgrf: syscon@10140000 {
  54                 compatible = "rockchip,rk3228-sgrf", "rockchip,sgrf", "syscon";
  55                 reg = <0x10140000 0x1000>;
  56         };
  57
  58         grf: syscon@11000000 {
  59                 compatible = "rockchip,rk3228-grf", "rockchip,grf", "syscon";
  60                 reg = <0x11000000 0x1000>;
  61         };
  62
  63         cru: syscon@110e0000 {
  64                 compatible = "rockchip,rk3228-cru", "rockchip,cru", "syscon";
  65                 reg = <0x110e0000 0x1000>;
  66         };
  67
  68         ddrpctl: syscon@11200000 {
  69                 compatible = "rockchip,rk3228-ddrpctl", "syscon";
  70                 reg = <0x11200000 0x400>;
  71         };
  72
  73         msch: syscon@31020000 {
  74                 compatible = "rockchip,rk32288-msch", "rockchip,msch", "syscon";
  75                 reg = <0x31020000 0x3000>;
  76         };
  77
  78         arm-pmu {
  79                 compatible = "arm,cortex-a7-pmu";
  80                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
  82                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
  83                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
  84         };
  85
  86         reset: reset@110e0110{
  87                 compatible = "rockchip,reset";
  88                 reg = <0x110e0110 0x20>;
  89                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
  90                 #reset-cells = <1>;
  91         };
  92
  93         timer {
  94                 compatible = "arm,armv7-timer";
  95                 interrupts = <GIC_PPI 13
  96                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  97                              <GIC_PPI 14
  98                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  99                 clock-frequency = <24000000>;
 100         };
 101
 102         uart_dbg: serial@11030000 {
 103                 compatible = "rockchip,serial";
 104                 reg = <0x11030000 0x100>;
 105                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 106                 clock-frequency = <24000000>;
 107                 clocks = <&xin24m>, <&xin24m>;
 108                 clock-names = "sclk_uart", "pclk_uart";
 109                 reg-shift = <2>;
 110                 reg-io-width = <4>;
 111                 status = "disabled";
 112         };
 113
 114         fiq-debugger {
 115                 compatible = "rockchip,fiq-debugger";
 116                 rockchip,serial-id = <2>;
 117                 rockchip,signal-irq = <159>;
 118                 rockchip,wake-irq = <0>;
 119                 rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
 120                 rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
 121                 status = "disabled";
 122         };
 123
 124         rockchip_clocks_init: clocks-init{
 125                 compatible = "rockchip,clocks-init";
 126                 rockchip,clocks-init-parent =
 127                         <&clk_i2s0_pll &clk_cpll>, <&clk_i2s1_pll &clk_cpll>,
 128                         <&clk_i2s2_pll &clk_cpll>, <&clk_spdif_pll &clk_cpll>,
 129                         <&clk_gpu &clk_cpll>, <&dclk_vop0 &hdmi_phy_clk>,
 130                         <&aclk_bus &clk_cpll>, <&aclk_peri &clk_cpll>,
 131                         <&clk_sdmmc0 &clk_cpll>, <&clk_emmc &clk_cpll>,
 132                         <&clk_sdio &clk_cpll>, <&aclk_vpu &clk_cpll>,
 133                         <&hdmi_phy_clk &hdmiphy_out>, <&usb480m &usb480m_phy>;
 134                 rockchip,clocks-init-rate =
 135                         <&clk_gpll 600000000>, <&clk_core 700000000>,
 136                         <&clk_cpll 500000000>, <&aclk_bus 250000000>,
 137                         <&hclk_bus 125000000>, <&pclk_bus 62500000>,
 138                         <&aclk_peri 250000000>, <&hclk_peri 125000000>,
 139                         <&pclk_peri 62500000>, <&clk_mac 125000000>,
 140                         <&aclk_iep 250000000>, <&hclk_vio 125000000>,
 141                         <&aclk_rga 250000000>, <&clk_gpu 250000000>,
 142                         <&aclk_vpu 25000000>, <&clk_vdec_core 250000000>,
 143                         <&clk_vdec_cabac 250000000>;
 144 /*
 145                 rockchip,clocks-uboot-has-init =
 146                         <&aclk_vio0>;
 147 */
 148         };
 149
 150         rockchip_clocks_enable: clocks-enable {
 151                 compatible = "rockchip,clocks-enable";
 152                 clocks =
 153                         /*PLL*/
 154                         <&clk_apll>,
 155                         <&clk_dpll>,
 156                         <&clk_gpll>,
 157                         <&clk_cpll>,
 158
 159                         /*PD_CORE*/
 160                         <&clk_core>,
 161                         <&pclk_dbg>,
 162                         <&aclk_core>,
 163                         <&clk_gates4 2>,
 164
 165                         /*PD_BUS*/
 166                         <&aclk_bus>,
 167                         <&hclk_bus>,
 168                         <&pclk_bus>,
 169                         <&clk_gates8 0>,/*aclk_intmem*/
 170                         <&clk_gates8 1>,/*clk_intmem_mbist*/
 171                         <&clk_gates8 2>,/*aclk_dmac_bus*/
 172                         <&clk_gates10 1>,/*g_aclk_bus*/
 173                         <&clk_gates13 9>,/*aclk_gic400*/
 174                         <&clk_gates8 3>,/*hclk_rom*/
 175                         <&clk_gates8 4>,/*pclk_ddrupctl*/
 176                         <&clk_gates8 6>,/*pclk_ddrmon*/
 177                         <&clk_gates9 4>,/*pclk_timer0*/
 178                         <&clk_gates9 5>,/*pclk_stimer*/
 179                         <&clk_gates10 0>,/*pclk_grf*/
 180                         <&clk_gates10 4>,/*pclk_cru*/
 181                         <&clk_gates10 6>,/*pclk_sgrf*/
 182                         <&clk_gates10 3>,/*pclk_ddrphy*/
 183                         <&clk_gates10 9>,/*pclk_phy_noc*/
 184
 185                         /*PD_PERI*/
 186                         <&aclk_peri>,
 187                         <&hclk_peri>,
 188                         <&pclk_peri>,
 189                         <&clk_gates12 0>,/*aclk_peri_noc*/
 190                         <&clk_gates12 1>,/*hclk_peri_noc*/
 191                         <&clk_gates12 2>,/*pclk_peri_noc*/
 192
 193                         <&clk_gates6 5>, /* g_clk_timer0 */
 194                         <&clk_gates6 6>, /* g_clk_timer1 */
 195
 196                         <&clk_gates7 14>, /* g_aclk_gpu */
 197                         <&clk_gates7 15>, /* g_aclk_gpu_noc */
 198
 199                         <&clk_gates1 3>;/*clk_jtag*/
 200         };
 201
 202         amba {
 203                 #address-cells = <1>;
 204                 #size-cells = <1>;
 205                 compatible = "arm,amba-bus";
 206                 interrupt-parent = <&gic>;
 207                 ranges;
 208
 209                 pdma: pdma@110f0000 {
 210                         compatible = "arm,pl330", "arm,primecell";
 211                         reg = <0x110f0000 0x4000>;
 212                         clocks = <&clk_gates8 2>;
 213                         clock-names = "apb_pclk";
 214                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 215                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 216                         #dma-cells = <1>;
 217                 };
 218         };
 219
 220         i2s0: i2s0@100c0000 {
 221                 compatible = "rockchip-i2s";
 222                 reg = <0x100c0000 0x1000>;
 223                 i2s-id = <0>;
 224                 clocks = <&clk_i2s0>, <&clk_gates8 7>;
 225                 clock-names = "i2s_clk", "i2s_hclk";
 226                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 227                 dmas = <&pdma 11>, <&pdma 12>;
 228                 #dma-cells = <2>;
 229                 dma-names = "tx", "rx";
 230         };
 231
 232         i2s1: i2s1@100b0000 {
 233                 compatible = "rockchip-i2s";
 234                 reg = <0x100b0000 0x1000>;
 235                 i2s-id = <1>;
 236                 clocks = <&clk_i2s1>, <&clk_i2s1_out>, <&clk_gates8 8>;
 237                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 238                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 239                 dmas = <&pdma 14>, <&pdma 15>;
 240                 #dma-cells = <2>;
 241                 dma-names = "tx", "rx";
 242                 status = "disabled";
 243         };
 244
 245         i2s2: i2s2@100e0000 {
 246                 compatible = "rockchip-i2s";
 247                 reg = <0x100e0000 0x1000>;
 248                 i2s-id = <2>;
 249                 clocks = <&clk_i2s2>, <&clk_gates8 9>;
 250                 clock-names = "i2s_clk", "i2s_hclk";
 251                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 252                 dmas = <&pdma 0>, <&pdma 1>;
 253                 #dma-cells = <2>;
 254                 dma-names = "tx", "rx";
 255                 status = "disabled";
 256         };
 257
 258         spdif: spdif@100d0000 {
 259                 compatible = "rockchip-spdif";
 260                 reg = <0x100d0000 0x1000>;
 261                 clocks = <&clk_spdif>, <&clk_gates8 10>;
 262                 clock-names = "spdif_mclk", "spdif_hclk";
 263                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 264                 dmas = <&pdma 10>;
 265                 #dma-cells = <1>;
 266                 dma-names = "tx";
 267                 status = "disabled";
 268         };
 269
 270         gpu {
 271                 compatible = "arm,mali400";
 272                 reg = <0x20001000 0x200>,
 273                       <0x20000000 0x100>,
 274                       <0x20003000 0x100>,
 275                       <0x20008000 0x1100>,
 276                       <0x20004000 0x100>,
 277                       <0x2000A000 0x1100>,
 278                       <0x20005000 0x100>;
 279
 280                 reg-names = "Mali_L2",
 281                             "Mali_GP",
 282                             "Mali_GP_MMU",
 283                             "Mali_PP0",
 284                             "Mali_PP0_MMU",
 285                             "Mali_PP1",
 286                             "Mali_PP1_MMU";
 287
 288                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 289                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 290                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 291                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 292                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 293                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 294
 295                 interrupt-names = "Mali_GP_IRQ",
 296                                   "Mali_GP_MMU_IRQ",
 297                                   "Mali_PP0_IRQ",
 298                                   "Mali_PP0_MMU_IRQ",
 299                                   "Mali_PP1_IRQ",
 300                                   "Mali_PP1_MMU_IRQ";
 301         };
 302
 303         fb: fb {
 304                 compatible = "rockchip,rk-fb";
 305                 rockchip,disp-mode = <NO_DUAL>;
 306         };
 307
 308         rk_screen: rk_screen {
 309                 compatible = "rockchip,screen";
 310         };
 311
 312         vop: vop@20050000 {
 313                 compatible = "rockchip,rk3228-lcdc";
 314
 315                 rockchip,cabc_mode = <0>;
 316                 rockchip,pwr18 = <0>;
 317                 rockchip,iommu-enabled = <1>;
 318                 reg = <0x20050000 0x300>;
 319                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 320                 clocks = <&aclk_vop>, <&dclk_vop0>, <&hclk_vio>;
 321                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 322         };
 323
 324         vop_mmu {
 325                 dbgname = "vop";
 326                 compatible = "rockchip,vop_mmu";
 327                 reg = <0x20053f00 0x100>;
 328                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 329                 interrupt-names = "vop_mmu";
 330         };
 331
 332         hevc_mmu {
 333                 dbgname = "hevc";
 334                 compatible = "rockchip,hevc_mmu";
 335                 reg = <0x20034440 0x40>,
 336                       <0x20034480 0x40>;
 337                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 338                 interrupt-names = "hevc_mmu";
 339         };
 340
 341         vpu_mmu {
 342                 dbgname = "vpu";
 343                 compatible = "rockchip,vpu_mmu";
 344                 reg = <0x20026800 0x100>;
 345                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 346                 interrupt-names = "vpu_mmu";
 347         };
 348
 349         iep_mmu {
 350                 dbgname = "iep";
 351                 compatible = "rockchip,iep_mmu";
 352                 reg = <0x20078800 0x100>;
 353                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 354                 interrupt-names = "iep_mmu";
 355         };
 356
 357         hdmi: hdmi@200a0000 {
 358                 compatible = "rockchip,rk3228-hdmi";
 359                 reg = <0x200a0000 0x20000>,
 360                       <0x12030000 0x10000>;
 361                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 362                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 363                 clocks = <&clk_gates14 6>, <&clk_gates3 7>, <&clk_hdmi_cec>;
 364                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 365                 rockchip,hdmi_audio_source = <0>;
 366                 rockchip,hdcp_enable = <0>;
 367                 rockchip,cec_enable = <0>;
 368                 status = "disabled";
 369         };
 370
 371         hdmi_hdcp2: hdmi_hdcp2@20090000 {
 372                 compatible = "rockchip,rk3228-hdmi-hdcp2";
 373                 reg = <0x20090000 0x10000>;
 374                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 375                 clocks = <&aclk_hdcp>,
 376                          <&clk_gates14 12>,
 377                          <&clk_gates14 11>,
 378                          <&clk_hdcp>;
 379                 clock-names = "aclk_hdcp2",
 380                               "hclk_hdcp2_mmu",
 381                               "pclk_hdcp2",
 382                               "hdcp2_clk_hdmi";
 383                 status = "disabled";
 384         };
 385
 386         tve: tve {
 387                 compatible = "rockchip,rk3228-tve";
 388                 reg = <0x20053e00 0x100>,
 389                       <0x12020000 0x10000>;
 390                 clocks = <&clk_gates10 8>;
 391                 clock-names = "pclk_vdac";
 392                 status = "disabled";
 393         };
 394
 395         emmc: rksdmmc@30020000 {
 396                 compatible = "rockchip,rk_mmc", "rockchip,rk3228-sdmmc";
 397                 reg = <0x30020000 0x10000>;
 398                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 399                 #address-cells = <1>;
 400                 #size-cells = <0>;
 401                 clocks = <&clk_emmc>, <&clk_gates7 0>;
 402                 clock-names = "clk_mmc", "hclk_mmc";
 403                 num-slots = <1>;
 404                 fifo-depth = <0x100>;
 405                 bus-width = <8>;
 406                 cru_regsbase = <0x124>;
 407                 cru_reset_offset = <3>;
 408         };
 409
 410         sdmmc: rksdmmc@30000000 {
 411                 compatible = "rockchip,rk_mmc", "rockchip,rk3228-sdmmc";
 412                 reg = <0x30000000 0x10000>;
 413                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 414                 #address-cells = <1>;
 415                 #size-cells = <0>;
 416                 clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
 417                 clock-names = "clk_mmc", "hclk_mmc";
 418                 num-slots = <1>;
 419                 fifo-depth = <0x100>;
 420                 bus-width = <4>;
 421                 cru_regsbase = <0x124>;
 422                 cru_reset_offset = <1>;
 423         };
 424
 425         sdio: rksdmmc@30010000 {
 426                 compatible = "rockchip,rk_mmc", "rockchip,rk3228-sdmmc";
 427                 reg = <0x30010000 0x10000>;
 428                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 429                 #address-cells = <1>;
 430                 #size-cells = <0>;
 431                 clocks = <&clk_sdio>, <&clk_gates5 11>;
 432                 clock-names = "clk_mmc", "hclk_mmc";
 433                 num-slots = <1>;
 434                 fifo-depth = <0x100>;
 435                 bus-width = <4>;
 436                 cru_regsbase = <0x124>;
 437                 cru_reset_offset = <2>;
 438         };
 439
 440         pinctrl: pinctrl {
 441                 compatible = "rockchip,rk3228-pinctrl";
 442                 rockchip,grf = <&grf>;
 443                 #address-cells = <1>;
 444                 #size-cells = <1>;
 445                 ranges;
 446
 447                 gpio0: gpio0@11110000 {
 448                         compatible = "rockchip,gpio-bank";
 449                         reg =   <0x11110000 0x100>;
 450                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 451                         clocks = <&clk_gates9 9>;
 452
 453                         gpio-controller;
 454                         #gpio-cells = <2>;
 455
 456                         interrupt-controller;
 457                         #interrupt-cells = <2>;
 458                 };
 459
 460                 gpio1: gpio1@11120000 {
 461                         compatible = "rockchip,gpio-bank";
 462                         reg = <0x11120000 0x100>;
 463                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 464                         clocks = <&clk_gates9 9>;
 465
 466                         gpio-controller;
 467                         #gpio-cells = <2>;
 468
 469                         interrupt-controller;
 470                         #interrupt-cells = <2>;
 471                 };
 472
 473                 gpio2: gpio2@11130000 {
 474                         compatible = "rockchip,gpio-bank";
 475                         reg = <0x11130000 0x100>;
 476                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 477                         clocks = <&clk_gates9 10>;
 478
 479                         gpio-controller;
 480                         #gpio-cells = <2>;
 481
 482                         interrupt-controller;
 483                         #interrupt-cells = <2>;
 484                 };
 485
 486                 gpio3: gpio3@11140000 {
 487                         compatible = "rockchip,gpio-bank";
 488                         reg = <0x11140000 0x100>;
 489                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 490                         clocks = <&clk_gates9 11>;
 491
 492                         gpio-controller;
 493                         #gpio-cells = <2>;
 494
 495                         interrupt-controller;
 496                         #interrupt-cells = <2>;
 497                 };
 498
 499                 pcfg_pull_up: pcfg-pull-up {
 500                         bias-pull-up;
 501                 };
 502
 503                 pcfg_pull_down: pcfg-pull-down {
 504                         bias-pull-down;
 505                 };
 506
 507                 pcfg_pull_none: pcfg-pull-none {
 508                         bias-disable;
 509                 };
 510
 511                 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
 512                         drive-strength = <8>;
 513                 };
 514
 515                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
 516                         drive-strength = <12>;
 517                 };
 518
 519                 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
 520                         bias-pull-up;
 521                         drive-strength = <8>;
 522                 };
 523
 524                 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
 525                         drive-strength = <4>;
 526                 };
 527
 528                 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
 529                         bias-pull-up;
 530                         drive-strength = <4>;
 531                 };
 532
 533                 pcfg_pull_down_drv_12ma: pcfg-pull-down-drv-12ma {
 534                         bias-pull-down;
 535                         drive-strength = <12>;
 536                 };
 537
 538                 pcfg_output_high: pcfg-output-high {
 539                         output-high;
 540                 };
 541
 542                 pcfg_output_low: pcfg-output-low {
 543                         output-low;
 544                 };
 545
 546                 pcfg_input_high: pcfg-input-high {
 547                         bias-pull-up;
 548                         input-enable;
 549                 };
 550
 551                 i2c0 {
 552                         i2c0_xfer: i2c0-xfer {
 553                                 rockchip,pins = <0 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,
 554                                                 <0 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>;
 555                         };
 556                         i2c0_gpio: i2c0-gpio {
 557                                 rockchip,pins = <0 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_none>,
 558                                                 <0 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_none>;
 559                         };
 560                         i2c0_sleep: i2c0-sleep {
 561                                 rockchip,pins = <0 GPIO_A0 RK_FUNC_GPIO &pcfg_input_high>,
 562                                                 <0 GPIO_A1 RK_FUNC_GPIO &pcfg_input_high>;
 563                         };
 564                 };
 565
 566                 i2c1 {
 567                         i2c1_xfer: i2c1-xfer {
 568                                 rockchip,pins = <0 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,
 569                                                 <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
 570                         };
 571                         i2c1_gpio: i2c1-gpio {
 572                                 rockchip,pins = <0 GPIO_A2  RK_FUNC_GPIO &pcfg_pull_none>,
 573                                                 <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
 574                         };
 575                         i2c1_sleep: i2c1-sleep {
 576                                 rockchip,pins = <0 GPIO_A2 RK_FUNC_GPIO &pcfg_input_high>,
 577                                                 <0 GPIO_A3 RK_FUNC_GPIO &pcfg_input_high>;
 578
 579                         };
 580                 };
 581
 582                 i2c2 {
 583                         i2c2_xfer: i2c2-xfer {
 584                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
 585                                                 <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
 586                         };
 587                         i2c2_gpio: i2c2-gpio {
 588                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
 589                                                 <2 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;
 590                         };
 591                         i2c2_sleep: i2c2-sleep {
 592                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_input_high>,
 593                                                 <2 GPIO_C4 RK_FUNC_GPIO &pcfg_input_high>;
 594                         };
 595                 };
 596
 597                 i2c3 {
 598                         i2c3_xfer: i2c3-xfer {
 599                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
 600                                                 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
 601                         };
 602                         i2c3_gpio: i2c3-gpio {
 603                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
 604                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
 605                         };
 606                         i2c3_sleep: i2c3-sleep {
 607                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_input_high>,
 608                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_input_high>;
 609                         };
 610                 };
 611
 612                 uart0 {
 613                         uart0_xfer: uart0-xfer {
 614                                 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_up>,
 615                                                 <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
 616                         };
 617
 618                         uart0_cts: uart0-cts {
 619                                 rockchip,pins = <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;
 620                         };
 621
 622                         uart0_rts: uart0-rts {
 623                                 rockchip,pins = <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
 624                         };
 625
 626                         uart0_rts_gpio: uart0-rts-gpio {
 627                                 rockchip,pins = <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
 628                         };
 629                 };
 630
 631                 uart1 {
 632                         uart1_xfer: uart1-xfer {
 633                                 rockchip,pins = <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_up>,
 634                                                 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>;
 635                         };
 636
 637                         uart1_cts: uart1-cts {
 638                                 rockchip,pins = <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>;
 639                         };
 640
 641                         uart1_rts: uart1-rts {
 642                                 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;
 643                         };
 644                 };
 645
 646                 uart11 {
 647                         uart11_xfer: uart11-xfer {
 648                                 rockchip,pins = <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_up>,
 649                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
 650                         };
 651
 652                         uart11_cts: uart11-cts {
 653                                 rockchip,pins = <3 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
 654                         };
 655
 656                         uart11_rts: uart11-rts {
 657                                 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>;
 658                         };
 659                 };
 660
 661                 uart2 {
 662                         uart2_xfer: uart2-xfer {
 663                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up>,
 664                                                 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>;
 665                         };
 666
 667                         uart2_cts: uart2-cts {
 668                                 rockchip,pins = <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
 669                         };
 670
 671                         uart2_rts: uart2-rts {
 672                                 rockchip,pins = <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>;
 673                         };
 674                 };
 675
 676                 uart21 {
 677                         uart21_xfer: uart21-xfer {
 678                                 rockchip,pins = <1 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>,
 679                                                 <1 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
 680                         };
 681                 };
 682
 683                 spi0 {
 684                         spi0_clk: spi0-clk {
 685                                 rockchip,pins = <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_up>;
 686                         };
 687                         spi0_cs0: spi0-cs0 {
 688                                 rockchip,pins = <0 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
 689                         };
 690                         spi0_tx: spi0-tx {
 691                                 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
 692                         };
 693                         spi0_rx: spi0-rx {
 694                                 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
 695                         };
 696                         spi0_cs1: spi0-cs1 {
 697                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_up>;
 698                         };
 699                 };
 700
 701                 spi1 {
 702                         spi1_clk: spi1-clk {
 703                                 rockchip,pins = <0 GPIO_C7 RK_FUNC_2 &pcfg_pull_up>;
 704                         };
 705                         spi1_cs0: spi1-cs0 {
 706                                 rockchip,pins = <2 GPIO_A2 RK_FUNC_2 &pcfg_pull_up>;
 707                         };
 708                         spi1_rx: spi1-rx {
 709                                 rockchip,pins = <2 GPIO_A0 RK_FUNC_2 &pcfg_pull_up>;
 710                         };
 711                         spi1_tx: spi1-tx {
 712                                 rockchip,pins = <2 GPIO_A1 RK_FUNC_2 &pcfg_pull_up>;
 713                         };
 714                         spi1_cs1: spi1-cs1 {
 715                                 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_up>;
 716                         };
 717                 };
 718
 719                 i2s {
 720                         i2s_mclk: i2s-mclk {
 721                                 rockchip,pins = <0 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>;
 722                         };
 723
 724                         i2s_sclk:i2s-sclk {
 725                                 rockchip,pins = <0 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>;
 726                         };
 727
 728                         i2s_lrckrx:i2s-lrckrx {
 729                                 rockchip,pins = <0 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;
 730                         };
 731
 732                         i2s_lrcktx:i2s-lrcktx {
 733                                 rockchip,pins = <0 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
 734                         };
 735
 736                         i2s_sdi:i2s-sdi {
 737                                 rockchip,pins = <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
 738                         };
 739
 740                         i2s_sdo0:i2s-sdo0 {
 741                                 rockchip,pins = <0 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
 742                         };
 743
 744                         i2s_sdo1:i2s-sdo1 {
 745                                 rockchip,pins = <1 GPIO_A2 RK_FUNC_2 &pcfg_pull_none>;
 746                         };
 747
 748                         i2s_sdo2:i2s-sdo2 {
 749                                 rockchip,pins = <1 GPIO_A4 RK_FUNC_2 &pcfg_pull_none>;
 750                         };
 751
 752                         i2s_sdo3:i2s-sdo3 {
 753                                 rockchip,pins = <1 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
 754                         };
 755
 756                         i2s_gpio: i2s-gpio {
 757                                 rockchip,pins = <0 GPIO_B0  RK_FUNC_GPIO &pcfg_pull_none>,
 758                                                 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>,
 759                                                 <0 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_none>,
 760                                                 <0 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
 761                                                 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
 762                                                 <0 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
 763                                                 <1 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_none>,
 764                                                 <1 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_none>,
 765                                                 <1 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_none>;
 766                         };
 767                 };
 768
 769                 spdif0 {
 770                         spdif0_tx: spdif0-tx {
 771                                 rockchip,pins = <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
 772                         };
 773                 };
 774
 775                 spdif1 {
 776                         spdif1_tx: spdif1-tx {
 777                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>;
 778                         };
 779                 };
 780
 781                 sdmmc {
 782                         sdmmc_clk: sdmmc-clk {
 783                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
 784                         };
 785
 786                         sdmmc_cmd: sdmmc-cmd {
 787                                 rockchip,pins = <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
 788                         };
 789
 790                         sdmmc_dectn: sdmmc-dectn {
 791                                 rockchip,pins = <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
 792                         };
 793
 794                         sdmmc_wrprt: sdmmc-wrprt {
 795                                 rockchip,pins = <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
 796                         };
 797
 798                         sdmmc_pwren: sdmmc-pwren {
 799                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
 800                         };
 801
 802                         sdmmc_bus1: sdmmc-bus1 {
 803                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
 804                         };
 805
 806                         sdmmc_bus4: sdmmc-bus4 {
 807                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
 808                                                 <1 GPIO_C3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
 809                                                 <1 GPIO_C4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
 810                                                 <1 GPIO_C5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
 811                         };
 812
 813                         sdmmc_gpio: sdmmc-gpio {
 814                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
 815                                                 <1 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
 816                                                 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
 817                                                 <1 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
 818                                                 <1 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
 819                                                 <1 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
 820                                                 <1 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
 821                                                 <1 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
 822                                                 <1 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;
 823                         };
 824                 };
 825
 826                 sdio0 {
 827                         sdio0_bus1: sdio0-bus1 {
 828                                 rockchip,pins = <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
 829                         };
 830
 831                         sdio0_bus4: sdio0-bus4 {
 832                                 rockchip,pins = <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
 833                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
 834                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
 835                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
 836                         };
 837
 838                         sdio0_cmd: sdio0-cmd {
 839                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_2 &pcfg_pull_up_drv_4ma>;
 840                         };
 841
 842                         sdio0_clk: sdio0-clk {
 843                                 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
 844                         };
 845
 846                         sdio0_pwren: sdio0-pwren {
 847                                 rockchip,pins = <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_up>;
 848                         };
 849
 850                         sdio0_gpio: sdio0-gpio {
 851                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
 852                                                 <1 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
 853                                                 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
 854                                                 <1 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
 855                                                 <1 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
 856                                                 <1 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
 857                                                 <1 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;
 858                         };
 859                 };
 860
 861
 862                 sdio1 {
 863                         sdio1_bus1: sdio1-bus1 {
 864                                 rockchip,pins = <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
 865                         };
 866
 867                         sdio1_bus4: sdio1-bus4 {
 868                                 rockchip,pins = <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
 869                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
 870                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
 871                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
 872                         };
 873
 874                         sdio1_cmd: sdio1-cmd {
 875                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_2 &pcfg_pull_up_drv_4ma>;
 876                         };
 877
 878                         sdio1_clk: sdio1-clk {
 879                                 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
 880                         };
 881
 882                         sdio1_pwren: sdio1-pwren {
 883                                 rockchip,pins = <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_up>;
 884                         };
 885
 886                         sdio1_gpio: sdio1-gpio {
 887                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
 888                                                 <1 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
 889                                                 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
 890                                                 <1 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
 891                                                 <1 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
 892                                                 <1 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
 893                                                 <1 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;
 894                         };
 895                 };
 896
 897                 emmc {
 898                         emmc_clk: emmc-clk {
 899                                 rockchip,pins = <2 GPIO_A7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
 900                         };
 901
 902                         emmc_cmd: emmc-cmd {
 903                                 rockchip,pins = <1 GPIO_C6 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
 904                         };
 905
 906                         emmc_pwren: emmc-pwren {
 907                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
 908                         };
 909
 910                         emmc_rstnout: emmc_rstnout {
 911                                 rockchip,pins = <1 GPIO_C7 RK_FUNC_2 &pcfg_pull_none>;
 912                         };
 913
 914                         emmc_bus1: emmc-bus1 {
 915                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
 916                         };
 917
 918                         emmc_bus4: emmc-bus4 {
 919                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
 920                                                 <1 GPIO_C3 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
 921                                                 <1 GPIO_C4 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
 922                                                 <1 GPIO_C5 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
 923                         };
 924                 };
 925
 926                 pwm0 {
 927                         pwm0_pin: pwm0-pin {
 928                                 rockchip,pins = <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
 929                         };
 930                 };
 931
 932                 pwm1 {
 933                         pwm1_pin: pwm1-pin {
 934                                 rockchip,pins = <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
 935                         };
 936                 };
 937
 938                 pwm2 {
 939                         pwm2_pin: pwm2-pin {
 940                                 rockchip,pins = <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>;
 941                         };
 942                 };
 943
 944                 pwmir {
 945                         pwmir_pin: pwmir-pin {
 946                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
 947                         };
 948                 };
 949
 950                 pwm10 {
 951                         pwm10_pin: pwm10-pin {
 952                                 rockchip,pins = <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>;
 953                         };
 954                 };
 955
 956                 pwm11 {
 957                         pwm11_pin: pwm11-pin {
 958                                 rockchip,pins = <0 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
 959                         };
 960                 };
 961
 962                 pwm12 {
 963                         pwm12_pin: pwm12-pin {
 964                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_2 &pcfg_pull_none>;
 965                         };
 966                 };
 967
 968                 pwm1ir {
 969                         pwm1ir_pin: pwm1ir-pin {
 970                                 rockchip,pins = <1 GPIO_B3 RK_FUNC_2 &pcfg_pull_none>;
 971                         };
 972                 };
 973
 974                 gmac {
 975                         rgmii_pins: rgmii-pins {
 976                                 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,
 977                                                 <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,
 978                                                 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,
 979                                                 <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 980                                                 <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 981                                                 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 982                                                 <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 983                                                 <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 984                                                 <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 985                                                 <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,
 986                                                 <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
 987                                                 <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
 988                                                 <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,
 989                                                 <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>,
 990                                                 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>;
 991                         };
 992
 993                         rmii_pins: rmii-pins {
 994                                 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,
 995                                                 <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,
 996                                                 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,
 997                                                 <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 998                                                 <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 999                                                 <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1000                                                 <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,
1001                                                 <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1002                                                 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,
1003                                                 <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1004                         };
1005                 };
1006
1007                 tsadc_pin {
1008                         tsadc_int: tsadc-int {
1009                                 rockchip,pins = <0 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>;
1010                         };
1011                         tsadc_gpio: tsadc-gpio {
1012                                 rockchip,pins = <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>;
1013                         };
1014                 };
1015
1016                 hdmi_pin {
1017                         hdmi_cec: hdmi-cec {
1018                                 rockchip,pins = <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1019                         };
1020
1021                         hdmi_hpd: hdmi-hpd {
1022                                 rockchip,pins = <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1023                         };
1024                 };
1025
1026                 hdmi_i2c {
1027                         hdmii2c_xfer: hdmii2c-xfer {
1028                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_2 &pcfg_pull_none>,
1029                                                 <0 GPIO_A7 RK_FUNC_2 &pcfg_pull_none>;
1030                         };
1031                 };
1032         };
1033 };