1 #include <dt-bindings/interrupt-controller/arm-gic.h>
3 #include "skeleton.dtsi"
4 #include "rk3228-clocks.dtsi"
7 compatible = "rockchip,rk3228";
8 interrupt-parent = <&gic>;
20 compatible = "arm,cortex-a7";
25 compatible = "arm,cortex-a7";
30 compatible = "arm,cortex-a7";
35 compatible = "arm,cortex-a7";
40 gic: interrupt-controller@32010000 {
41 compatible = "arm,cortex-a15-gic";
43 #interrupt-cells = <3>;
45 reg = <0x32011000 0x1000>,
50 compatible = "arm,cortex-a7-pmu";
51 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
52 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
53 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
54 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
58 compatible = "arm,armv7-timer";
59 interrupts = <GIC_PPI 13
60 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
62 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
63 clock-frequency = <24000000>;
66 uart_dbg: serial@11030000 {
67 compatible = "rockchip,serial";
68 reg = <0x11030000 0x100>;
69 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
70 clock-frequency = <24000000>;
71 clocks = <&xin24m>, <&xin24m>;
72 clock-names = "sclk_uart", "pclk_uart";
79 compatible = "rockchip,fiq-debugger";
80 rockchip,serial-id = <2>;
81 rockchip,signal-irq = <159>;
82 rockchip,wake-irq = <0>;
83 rockchip,irq-mode-enable = <1>; /* If enable uart uses irq instead of fiq */
84 rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
88 rockchip_clocks_init: clocks-init{
89 compatible = "rockchip,clocks-init";
90 rockchip,clocks-init-parent =
91 <&clk_i2s0_pll &clk_cpll>, <&clk_i2s1_pll &clk_cpll>,
92 <&clk_i2s2_pll &clk_cpll>, <&clk_spdif_pll &clk_cpll>,
93 <&aclk_gpu &clk_cpll>, <&dclk_vop0 &hdmi_phy_clk>,
94 <&aclk_bus &clk_cpll>, <&aclk_peri &clk_cpll>,
95 <&clk_sdmmc0 &clk_cpll>, <&clk_emmc &clk_cpll>,
96 <&clk_sdio &clk_cpll>, <&aclk_vpu &clk_cpll>,
97 <&hdmi_phy_clk &hdmiphy_out>, <&usb480m &usb480m_phy>;
98 rockchip,clocks-init-rate =
99 <&clk_gpll 600000000>, <&clk_core 700000000>,
100 <&clk_cpll 500000000>, <&aclk_bus 250000000>,
101 <&hclk_bus 125000000>, <&pclk_bus 62500000>,
102 <&aclk_peri 250000000>, <&hclk_peri 125000000>,
103 <&pclk_peri 62500000>, <&clk_mac 125000000>,
104 <&aclk_iep 250000000>, <&hclk_vio 125000000>,
105 <&aclk_rga 250000000>, <&aclk_gpu 250000000>,
106 <&aclk_vpu 25000000>, <&clk_vdec_core 250000000>,
107 <&clk_vdec_cabac 250000000>;
109 rockchip,clocks-uboot-has-init =
114 rockchip_clocks_enable: clocks-enable {
115 compatible = "rockchip,clocks-enable";
133 <&clk_gates8 0>,/*aclk_intmem*/
134 <&clk_gates8 1>,/*clk_intmem_mbist*/
135 <&clk_gates8 2>,/*aclk_dmac_bus*/
136 <&clk_gates10 1>,/*g_aclk_bus*/
137 <&clk_gates13 9>,/*aclk_gic400*/
138 <&clk_gates8 3>,/*hclk_rom*/
139 <&clk_gates8 4>,/*pclk_ddrupctl*/
140 <&clk_gates8 6>,/*pclk_ddrmon*/
141 <&clk_gates9 4>,/*pclk_timer0*/
142 <&clk_gates9 5>,/*pclk_stimer*/
143 <&clk_gates10 0>,/*pclk_grf*/
144 <&clk_gates10 4>,/*pclk_cru*/
145 <&clk_gates10 6>,/*pclk_sgrf*/
146 <&clk_gates10 3>,/*pclk_ddrphy*/
147 <&clk_gates10 9>,/*pclk_phy_noc*/
153 <&clk_gates12 0>,/*aclk_peri_noc*/
154 <&clk_gates12 1>,/*hclk_peri_noc*/
155 <&clk_gates12 2>,/*pclk_peri_noc*/
157 <&clk_gates6 5>, /* g_clk_timer0 */
158 <&clk_gates6 6>, /* g_clk_timer1 */
160 <&clk_gates7 14>, /* g_aclk_gpu */
161 <&clk_gates7 15>, /* g_aclk_gpu_noc */
163 <&clk_gates1 3>;/*clk_jtag*/
167 #address-cells = <1>;
169 compatible = "arm,amba-bus";
170 interrupt-parent = <&gic>;
173 pdma: pdma@110f0000 {
174 compatible = "arm,pl330", "arm,primecell";
175 reg = <0x110f0000 0x4000>;
176 clocks = <&clk_gates8 2>;
177 clock-names = "apb_pclk";
178 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
179 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
184 i2s0: i2s0@100c0000 {
185 compatible = "rockchip-i2s";
186 reg = <0x100c0000 0x1000>;
188 clocks = <&clk_i2s0>, <&clk_gates8 7>;
189 clock-names = "i2s_clk", "i2s_hclk";
190 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
191 dmas = <&pdma 11>, <&pdma 12>;
193 dma-names = "tx", "rx";
196 i2s1: i2s1@100b0000 {
197 compatible = "rockchip-i2s";
198 reg = <0x100b0000 0x1000>;
200 clocks = <&clk_i2s1>, <&clk_i2s1_out>, <&clk_gates8 8>;
201 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
202 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
203 dmas = <&pdma 14>, <&pdma 15>;
205 dma-names = "tx", "rx";
209 i2s2: i2s2@100e0000 {
210 compatible = "rockchip-i2s";
211 reg = <0x100e0000 0x1000>;
213 clocks = <&clk_i2s2>, <&clk_gates8 9>;
214 clock-names = "i2s_clk", "i2s_hclk";
215 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
216 dmas = <&pdma 0>, <&pdma 1>;
218 dma-names = "tx", "rx";
222 spdif: spdif@100d0000 {
223 compatible = "rockchip-spdif";
224 reg = <0x100d0000 0x1000>;
225 clocks = <&clk_spdif>, <&clk_gates8 10>;
226 clock-names = "spdif_mclk", "spdif_hclk";
227 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;