arch/arm/boot/dts/rk3228.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3228-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include "skeleton.dtsi"
  48
  49 / {
  50         compatible = "rockchip,rk3228";
  51
  52         interrupt-parent = <&gic>;
  53
  54         aliases {
  55                 serial0 = &uart0;
  56                 serial1 = &uart1;
  57                 serial2 = &uart2;
  58         };
  59
  60         cpus {
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;
  63
  64                 cpu0: cpu@f00 {
  65                         device_type = "cpu";
  66                         compatible = "arm,cortex-a7";
  67                         reg = <0xf00>;
  68                         resets = <&cru SRST_CORE0>;
  69                         operating-points = <
  70                                 /* KHz    uV */
  71                                  816000 1000000
  72                         >;
  73                         #cooling-cells = <2>; /* min followed by max */
  74                         clock-latency = <40000>;
  75                         clocks = <&cru ARMCLK>;
  76                 };
  77
  78                 cpu1: cpu@f01 {
  79                         device_type = "cpu";
  80                         compatible = "arm,cortex-a7";
  81                         reg = <0xf01>;
  82                         resets = <&cru SRST_CORE1>;
  83                 };
  84
  85                 cpu2: cpu@f02 {
  86                         device_type = "cpu";
  87                         compatible = "arm,cortex-a7";
  88                         reg = <0xf02>;
  89                         resets = <&cru SRST_CORE2>;
  90                 };
  91
  92                 cpu3: cpu@f03 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a7";
  95                         reg = <0xf03>;
  96                         resets = <&cru SRST_CORE3>;
  97                 };
  98         };
  99
 100         amba {
 101                 compatible = "arm,amba-bus";
 102                 #address-cells = <1>;
 103                 #size-cells = <1>;
 104                 ranges;
 105
 106                 pdma: pdma@110f0000 {
 107                         compatible = "arm,pl330", "arm,primecell";
 108                         reg = <0x110f0000 0x4000>;
 109                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 110                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 111                         #dma-cells = <1>;
 112                         clocks = <&cru ACLK_DMAC>;
 113                         clock-names = "apb_pclk";
 114                 };
 115         };
 116
 117         arm-pmu {
 118                 compatible = "arm,cortex-a7-pmu";
 119                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 120                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
 121                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 122                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 123                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 124         };
 125
 126         timer {
 127                 compatible = "arm,armv7-timer";
 128                 arm,cpu-registers-not-fw-configured;
 129                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 130                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 131                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 132                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 133                 clock-frequency = <24000000>;
 134         };
 135
 136         xin24m: oscillator {
 137                 compatible = "fixed-clock";
 138                 clock-frequency = <24000000>;
 139                 clock-output-names = "xin24m";
 140                 #clock-cells = <0>;
 141         };
 142
 143         grf: syscon@11000000 {
 144                 compatible = "syscon";
 145                 reg = <0x11000000 0x1000>;
 146         };
 147
 148         uart0: serial@11010000 {
 149                 compatible = "snps,dw-apb-uart";
 150                 reg = <0x11010000 0x100>;
 151                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 152                 clock-frequency = <24000000>;
 153                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 154                 clock-names = "baudclk", "apb_pclk";
 155                 pinctrl-names = "default";
 156                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 157                 reg-shift = <2>;
 158                 reg-io-width = <4>;
 159                 status = "disabled";
 160         };
 161
 162         uart1: serial@11020000 {
 163                 compatible = "snps,dw-apb-uart";
 164                 reg = <0x11020000 0x100>;
 165                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 166                 clock-frequency = <24000000>;
 167                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 168                 clock-names = "baudclk", "apb_pclk";
 169                 pinctrl-names = "default";
 170                 pinctrl-0 = <&uart1_xfer>;
 171                 reg-shift = <2>;
 172                 reg-io-width = <4>;
 173                 status = "disabled";
 174         };
 175
 176         uart2: serial@11030000 {
 177                 compatible = "snps,dw-apb-uart";
 178                 reg = <0x11030000 0x100>;
 179                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 180                 clock-frequency = <24000000>;
 181                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 182                 clock-names = "baudclk", "apb_pclk";
 183                 pinctrl-names = "default";
 184                 pinctrl-0 = <&uart2_xfer>;
 185                 reg-shift = <2>;
 186                 reg-io-width = <4>;
 187                 status = "disabled";
 188         };
 189
 190         pwm0: pwm@110b0000 {
 191                 compatible = "rockchip,rk3288-pwm";
 192                 reg = <0x110b0000 0x10>;
 193                 #pwm-cells = <3>;
 194                 clocks = <&cru PCLK_PWM>;
 195                 clock-names = "pwm";
 196                 pinctrl-names = "default";
 197                 pinctrl-0 = <&pwm0_pin>;
 198                 status = "disabled";
 199         };
 200
 201         pwm1: pwm@110b0010 {
 202                 compatible = "rockchip,rk3288-pwm";
 203                 reg = <0x110b0010 0x10>;
 204                 #pwm-cells = <3>;
 205                 clocks = <&cru PCLK_PWM>;
 206                 clock-names = "pwm";
 207                 pinctrl-names = "default";
 208                 pinctrl-0 = <&pwm1_pin>;
 209                 status = "disabled";
 210         };
 211
 212         pwm2: pwm@110b0020 {
 213                 compatible = "rockchip,rk3288-pwm";
 214                 reg = <0x110b0020 0x10>;
 215                 #pwm-cells = <3>;
 216                 clocks = <&cru PCLK_PWM>;
 217                 clock-names = "pwm";
 218                 pinctrl-names = "default";
 219                 pinctrl-0 = <&pwm2_pin>;
 220                 status = "disabled";
 221         };
 222
 223         pwm3: pwm@110b0030 {
 224                 compatible = "rockchip,rk3288-pwm";
 225                 reg = <0x110b0030 0x10>;
 226                 #pwm-cells = <2>;
 227                 clocks = <&cru PCLK_PWM>;
 228                 clock-names = "pwm";
 229                 pinctrl-names = "default";
 230                 pinctrl-0 = <&pwm3_pin>;
 231                 status = "disabled";
 232         };
 233
 234         timer: timer@110c0000 {
 235                 compatible = "rockchip,rk3288-timer";
 236                 reg = <0x110c0000 0x20>;
 237                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 238                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 239                 clock-names = "timer", "pclk";
 240         };
 241
 242         cru: clock-controller@110e0000 {
 243                 compatible = "rockchip,rk3228-cru";
 244                 reg = <0x110e0000 0x1000>;
 245                 rockchip,grf = <&grf>;
 246                 #clock-cells = <1>;
 247                 #reset-cells = <1>;
 248                 assigned-clocks = <&cru PLL_GPLL>;
 249                 assigned-clock-rates = <594000000>;
 250         };
 251
 252         thermal-zones {
 253                 cpu_thermal: cpu-thermal {
 254                         polling-delay-passive = <100>; /* milliseconds */
 255                         polling-delay = <5000>; /* milliseconds */
 256
 257                         thermal-sensors = <&tsadc 0>;
 258
 259                         trips {
 260                                 cpu_alert0: cpu_alert0 {
 261                                         temperature = <70000>; /* millicelsius */
 262                                         hysteresis = <2000>; /* millicelsius */
 263                                         type = "passive";
 264                                 };
 265                                 cpu_alert1: cpu_alert1 {
 266                                         temperature = <75000>; /* millicelsius */
 267                                         hysteresis = <2000>; /* millicelsius */
 268                                         type = "passive";
 269                                 };
 270                                 cpu_crit: cpu_crit {
 271                                         temperature = <90000>; /* millicelsius */
 272                                         hysteresis = <2000>; /* millicelsius */
 273                                         type = "critical";
 274                                 };
 275                         };
 276
 277                         cooling-maps {
 278                                 map0 {
 279                                         trip = <&cpu_alert0>;
 280                                         cooling-device =
 281                                                 <&cpu0 THERMAL_NO_LIMIT 6>;
 282                                 };
 283                                 map1 {
 284                                         trip = <&cpu_alert1>;
 285                                         cooling-device =
 286                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 287                                 };
 288                         };
 289                 };
 290         };
 291
 292         tsadc: tsadc@11150000 {
 293                 compatible = "rockchip,rk3228-tsadc";
 294                 reg = <0x11150000 0x100>;
 295                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 296                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 297                 clock-names = "tsadc", "apb_pclk";
 298                 resets = <&cru SRST_TSADC>;
 299                 reset-names = "tsadc-apb";
 300                 pinctrl-names = "init", "default", "sleep";
 301                 pinctrl-0 = <&otp_gpio>;
 302                 pinctrl-1 = <&otp_out>;
 303                 pinctrl-2 = <&otp_gpio>;
 304                 #thermal-sensor-cells = <0>;
 305                 rockchip,hw-tshut-temp = <95000>;
 306                 status = "disabled";
 307         };
 308
 309         emmc: dwmmc@30020000 {
 310                 compatible = "rockchip,rk3288-dw-mshc";
 311                 reg = <0x30020000 0x4000>;
 312                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 313                 clock-frequency = <37500000>;
 314                 clock-freq-min-max = <400000 37500000>;
 315                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 316                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 317                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 318                 bus-width = <8>;
 319                 default-sample-phase = <158>;
 320                 num-slots = <1>;
 321                 fifo-depth = <0x100>;
 322                 pinctrl-names = "default";
 323                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 324                 status = "disabled";
 325         };
 326
 327         gic: interrupt-controller@32010000 {
 328                 compatible = "arm,gic-400";
 329                 interrupt-controller;
 330                 #interrupt-cells = <3>;
 331                 #address-cells = <0>;
 332
 333                 reg = <0x32011000 0x1000>,
 334                       <0x32012000 0x1000>,
 335                       <0x32014000 0x2000>,
 336                       <0x32016000 0x2000>;
 337                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 338         };
 339
 340         pinctrl: pinctrl {
 341                 compatible = "rockchip,rk3228-pinctrl";
 342                 rockchip,grf = <&grf>;
 343                 #address-cells = <1>;
 344                 #size-cells = <1>;
 345                 ranges;
 346
 347                 gpio0: gpio0@11110000 {
 348                         compatible = "rockchip,gpio-bank";
 349                         reg = <0x11110000 0x100>;
 350                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 351                         clocks = <&cru PCLK_GPIO0>;
 352
 353                         gpio-controller;
 354                         #gpio-cells = <2>;
 355
 356                         interrupt-controller;
 357                         #interrupt-cells = <2>;
 358                 };
 359
 360                 gpio1: gpio1@11120000 {
 361                         compatible = "rockchip,gpio-bank";
 362                         reg = <0x11120000 0x100>;
 363                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 364                         clocks = <&cru PCLK_GPIO1>;
 365
 366                         gpio-controller;
 367                         #gpio-cells = <2>;
 368
 369                         interrupt-controller;
 370                         #interrupt-cells = <2>;
 371                 };
 372
 373                 gpio2: gpio2@11130000 {
 374                         compatible = "rockchip,gpio-bank";
 375                         reg = <0x11130000 0x100>;
 376                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 377                         clocks = <&cru PCLK_GPIO2>;
 378
 379                         gpio-controller;
 380                         #gpio-cells = <2>;
 381
 382                         interrupt-controller;
 383                         #interrupt-cells = <2>;
 384                 };
 385
 386                 gpio3: gpio3@11140000 {
 387                         compatible = "rockchip,gpio-bank";
 388                         reg = <0x11140000 0x100>;
 389                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 390                         clocks = <&cru PCLK_GPIO3>;
 391
 392                         gpio-controller;
 393                         #gpio-cells = <2>;
 394
 395                         interrupt-controller;
 396                         #interrupt-cells = <2>;
 397                 };
 398
 399                 pcfg_pull_up: pcfg-pull-up {
 400                         bias-pull-up;
 401                 };
 402
 403                 pcfg_pull_down: pcfg-pull-down {
 404                         bias-pull-down;
 405                 };
 406
 407                 pcfg_pull_none: pcfg-pull-none {
 408                         bias-disable;
 409                 };
 410
 411                 emmc {
 412                         emmc_clk: emmc-clk {
 413                                 rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
 414                         };
 415
 416                         emmc_cmd: emmc-cmd {
 417                                 rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>;
 418                         };
 419
 420                         emmc_bus8: emmc-bus8 {
 421                                 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
 422                                                 <1 25 RK_FUNC_2 &pcfg_pull_none>,
 423                                                 <1 26 RK_FUNC_2 &pcfg_pull_none>,
 424                                                 <1 27 RK_FUNC_2 &pcfg_pull_none>,
 425                                                 <1 28 RK_FUNC_2 &pcfg_pull_none>,
 426                                                 <1 29 RK_FUNC_2 &pcfg_pull_none>,
 427                                                 <1 30 RK_FUNC_2 &pcfg_pull_none>,
 428                                                 <1 31 RK_FUNC_2 &pcfg_pull_none>;
 429                         };
 430                 };
 431
 432                 pwm0 {
 433                         pwm0_pin: pwm0-pin {
 434                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>;
 435                         };
 436                 };
 437
 438                 pwm1 {
 439                         pwm1_pin: pwm1-pin {
 440                                 rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>;
 441                         };
 442                 };
 443
 444                 pwm2 {
 445                         pwm2_pin: pwm2-pin {
 446                                 rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>;
 447                         };
 448                 };
 449
 450                 pwm3 {
 451                         pwm3_pin: pwm3-pin {
 452                                 rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>;
 453                         };
 454                 };
 455
 456                 tsadc {
 457                         otp_gpio: otp-gpio {
 458                                 rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
 459                         };
 460
 461                         otp_out: otp-out {
 462                                 rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>;
 463                         };
 464                 };
 465
 466                 uart0 {
 467                         uart0_xfer: uart0-xfer {
 468                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>,
 469                                                 <2 27 RK_FUNC_1 &pcfg_pull_none>;
 470                         };
 471
 472                         uart0_cts: uart0-cts {
 473                                 rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>;
 474                         };
 475
 476                         uart0_rts: uart0-rts {
 477                                 rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>;
 478                         };
 479                 };
 480
 481                 uart1 {
 482                         uart1_xfer: uart1-xfer {
 483                                 rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>,
 484                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>;
 485                         };
 486
 487                         uart1_cts: uart1-cts {
 488                                 rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>;
 489                         };
 490
 491                         uart1_rts: uart1-rts {
 492                                 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;
 493                         };
 494                 };
 495
 496                 uart2 {
 497                         uart2_xfer: uart2-xfer {
 498                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
 499                                                 <1 19 RK_FUNC_2 &pcfg_pull_none>;
 500                         };
 501
 502                         uart2_cts: uart2-cts {
 503                                 rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>;
 504                         };
 505
 506                         uart2_rts: uart2-rts {
 507                                 rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>;
 508                         };
 509                 };
 510         };
 511 };