arch/arm/boot/dts/rk3228.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/rkfb/rk_fb.h>
   3
   4 #include "skeleton.dtsi"
   5 #include "rk3228-clocks.dtsi"
   6
   7 / {
   8         compatible = "rockchip,rk3228";
   9         interrupt-parent = <&gic>;
  10
  11         aliases {
  12                 serial2 = &uart_dbg;
  13         };
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a7";
  22                         reg = <0xf00>;
  23                 };
  24                 cpu@1 {
  25                         device_type = "cpu";
  26                         compatible = "arm,cortex-a7";
  27                         reg = <0xf01>;
  28                 };
  29                 cpu@2 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a7";
  32                         reg = <0xf02>;
  33                 };
  34                 cpu@3 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a7";
  37                         reg = <0xf03>;
  38                 };
  39         };
  40
  41         gic: interrupt-controller@32010000 {
  42                 compatible = "arm,cortex-a15-gic";
  43                 interrupt-controller;
  44                 #interrupt-cells = <3>;
  45                 #address-cells = <0>;
  46                 reg = <0x32011000 0x1000>,
  47                       <0x32012000 0x1000>;
  48         };
  49
  50         sgrf: syscon@10140000 {
  51                 compatible = "rockchip,rk3228-sgrf", "rockchip,sgrf", "syscon";
  52                 reg = <0x10140000 0x1000>;
  53         };
  54
  55         grf: syscon@11000000 {
  56                 compatible = "rockchip,rk3228-grf", "rockchip,grf", "syscon";
  57                 reg = <0x11000000 0x1000>;
  58         };
  59
  60         cru: syscon@110e0000 {
  61                 compatible = "rockchip,rk3228-cru", "rockchip,cru", "syscon";
  62                 reg = <0x110e0000 0x1000>;
  63         };
  64
  65         ddrpctl: syscon@11200000 {
  66                 compatible = "rockchip,rk3228-ddrpctl", "syscon";
  67                 reg = <0x11200000 0x400>;
  68         };
  69
  70         msch: syscon@31020000 {
  71                 compatible = "rockchip,rk32288-msch", "rockchip,msch", "syscon";
  72                 reg = <0x31020000 0x3000>;
  73         };
  74
  75         arm-pmu {
  76                 compatible = "arm,cortex-a7-pmu";
  77                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  78                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
  79                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
  80                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
  81         };
  82
  83         reset: reset@110e0110{
  84                 compatible = "rockchip,reset";
  85                 reg = <0x110e0110 0x20>;
  86                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
  87                 #reset-cells = <1>;
  88         };
  89
  90         timer {
  91                 compatible = "arm,armv7-timer";
  92                 interrupts = <GIC_PPI 13
  93                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  94                              <GIC_PPI 14
  95                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  96                 clock-frequency = <24000000>;
  97         };
  98
  99         uart_dbg: serial@11030000 {
 100                 compatible = "rockchip,serial";
 101                 reg = <0x11030000 0x100>;
 102                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 103                 clock-frequency = <24000000>;
 104                 clocks = <&xin24m>, <&xin24m>;
 105                 clock-names = "sclk_uart", "pclk_uart";
 106                 reg-shift = <2>;
 107                 reg-io-width = <4>;
 108                 status = "disabled";
 109         };
 110
 111         fiq-debugger {
 112                 compatible = "rockchip,fiq-debugger";
 113                 rockchip,serial-id = <2>;
 114                 rockchip,signal-irq = <159>;
 115                 rockchip,wake-irq = <0>;
 116                 rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
 117                 rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
 118                 status = "disabled";
 119         };
 120
 121         rockchip_clocks_init: clocks-init{
 122                 compatible = "rockchip,clocks-init";
 123                 rockchip,clocks-init-parent =
 124                         <&clk_i2s0_pll &clk_cpll>, <&clk_i2s1_pll &clk_cpll>,
 125                         <&clk_i2s2_pll &clk_cpll>, <&clk_spdif_pll &clk_cpll>,
 126                         <&clk_gpu &clk_cpll>, <&dclk_vop0 &hdmi_phy_clk>,
 127                         <&aclk_bus &clk_cpll>, <&aclk_peri &clk_cpll>,
 128                         <&clk_sdmmc0 &clk_cpll>, <&clk_emmc &clk_cpll>,
 129                         <&clk_sdio &clk_cpll>, <&aclk_vpu &clk_cpll>,
 130                         <&hdmi_phy_clk &hdmiphy_out>, <&usb480m &usb480m_phy>;
 131                 rockchip,clocks-init-rate =
 132                         <&clk_gpll 600000000>, <&clk_core 700000000>,
 133                         <&clk_cpll 500000000>, <&aclk_bus 250000000>,
 134                         <&hclk_bus 125000000>, <&pclk_bus 62500000>,
 135                         <&aclk_peri 250000000>, <&hclk_peri 125000000>,
 136                         <&pclk_peri 62500000>, <&clk_mac 125000000>,
 137                         <&aclk_iep 250000000>, <&hclk_vio 125000000>,
 138                         <&aclk_rga 250000000>, <&clk_gpu 250000000>,
 139                         <&aclk_vpu 25000000>, <&clk_vdec_core 250000000>,
 140                         <&clk_vdec_cabac 250000000>;
 141 /*
 142                 rockchip,clocks-uboot-has-init =
 143                         <&aclk_vio0>;
 144 */
 145         };
 146
 147         rockchip_clocks_enable: clocks-enable {
 148                 compatible = "rockchip,clocks-enable";
 149                 clocks =
 150                         /*PLL*/
 151                         <&clk_apll>,
 152                         <&clk_dpll>,
 153                         <&clk_gpll>,
 154                         <&clk_cpll>,
 155
 156                         /*PD_CORE*/
 157                         <&clk_core>,
 158                         <&pclk_dbg>,
 159                         <&aclk_core>,
 160                         <&clk_gates4 2>,
 161
 162                         /*PD_BUS*/
 163                         <&aclk_bus>,
 164                         <&hclk_bus>,
 165                         <&pclk_bus>,
 166                         <&clk_gates8 0>,/*aclk_intmem*/
 167                         <&clk_gates8 1>,/*clk_intmem_mbist*/
 168                         <&clk_gates8 2>,/*aclk_dmac_bus*/
 169                         <&clk_gates10 1>,/*g_aclk_bus*/
 170                         <&clk_gates13 9>,/*aclk_gic400*/
 171                         <&clk_gates8 3>,/*hclk_rom*/
 172                         <&clk_gates8 4>,/*pclk_ddrupctl*/
 173                         <&clk_gates8 6>,/*pclk_ddrmon*/
 174                         <&clk_gates9 4>,/*pclk_timer0*/
 175                         <&clk_gates9 5>,/*pclk_stimer*/
 176                         <&clk_gates10 0>,/*pclk_grf*/
 177                         <&clk_gates10 4>,/*pclk_cru*/
 178                         <&clk_gates10 6>,/*pclk_sgrf*/
 179                         <&clk_gates10 3>,/*pclk_ddrphy*/
 180                         <&clk_gates10 9>,/*pclk_phy_noc*/
 181
 182                         /*PD_PERI*/
 183                         <&aclk_peri>,
 184                         <&hclk_peri>,
 185                         <&pclk_peri>,
 186                         <&clk_gates12 0>,/*aclk_peri_noc*/
 187                         <&clk_gates12 1>,/*hclk_peri_noc*/
 188                         <&clk_gates12 2>,/*pclk_peri_noc*/
 189
 190                         <&clk_gates6 5>, /* g_clk_timer0 */
 191                         <&clk_gates6 6>, /* g_clk_timer1 */
 192
 193                         <&clk_gates7 14>, /* g_aclk_gpu */
 194                         <&clk_gates7 15>, /* g_aclk_gpu_noc */
 195
 196                         <&clk_gates1 3>;/*clk_jtag*/
 197         };
 198
 199         amba {
 200                 #address-cells = <1>;
 201                 #size-cells = <1>;
 202                 compatible = "arm,amba-bus";
 203                 interrupt-parent = <&gic>;
 204                 ranges;
 205
 206                 pdma: pdma@110f0000 {
 207                         compatible = "arm,pl330", "arm,primecell";
 208                         reg = <0x110f0000 0x4000>;
 209                         clocks = <&clk_gates8 2>;
 210                         clock-names = "apb_pclk";
 211                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 212                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 213                         #dma-cells = <1>;
 214                 };
 215         };
 216
 217         i2s0: i2s0@100c0000 {
 218                 compatible = "rockchip-i2s";
 219                 reg = <0x100c0000 0x1000>;
 220                 i2s-id = <0>;
 221                 clocks = <&clk_i2s0>, <&clk_gates8 7>;
 222                 clock-names = "i2s_clk", "i2s_hclk";
 223                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 224                 dmas = <&pdma 11>, <&pdma 12>;
 225                 #dma-cells = <2>;
 226                 dma-names = "tx", "rx";
 227         };
 228
 229         i2s1: i2s1@100b0000 {
 230                 compatible = "rockchip-i2s";
 231                 reg = <0x100b0000 0x1000>;
 232                 i2s-id = <1>;
 233                 clocks = <&clk_i2s1>, <&clk_i2s1_out>, <&clk_gates8 8>;
 234                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 235                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 236                 dmas = <&pdma 14>, <&pdma 15>;
 237                 #dma-cells = <2>;
 238                 dma-names = "tx", "rx";
 239                 status = "disabled";
 240         };
 241
 242         i2s2: i2s2@100e0000 {
 243                 compatible = "rockchip-i2s";
 244                 reg = <0x100e0000 0x1000>;
 245                 i2s-id = <2>;
 246                 clocks = <&clk_i2s2>, <&clk_gates8 9>;
 247                 clock-names = "i2s_clk", "i2s_hclk";
 248                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 249                 dmas = <&pdma 0>, <&pdma 1>;
 250                 #dma-cells = <2>;
 251                 dma-names = "tx", "rx";
 252                 status = "disabled";
 253         };
 254
 255         spdif: spdif@100d0000 {
 256                 compatible = "rockchip-spdif";
 257                 reg = <0x100d0000 0x1000>;
 258                 clocks = <&clk_spdif>, <&clk_gates8 10>;
 259                 clock-names = "spdif_mclk", "spdif_hclk";
 260                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 261                 dmas = <&pdma 10>;
 262                 #dma-cells = <1>;
 263                 dma-names = "tx";
 264                 status = "disabled";
 265         };
 266
 267         gpu {
 268                 compatible = "arm,mali400";
 269                 reg = <0x20001000 0x200>,
 270                       <0x20000000 0x100>,
 271                       <0x20003000 0x100>,
 272                       <0x20008000 0x1100>,
 273                       <0x20004000 0x100>,
 274                       <0x2000A000 0x1100>,
 275                       <0x20005000 0x100>;
 276
 277                 reg-names = "Mali_L2",
 278                             "Mali_GP",
 279                             "Mali_GP_MMU",
 280                             "Mali_PP0",
 281                             "Mali_PP0_MMU",
 282                             "Mali_PP1",
 283                             "Mali_PP1_MMU";
 284
 285                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 286                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 287                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 288                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 289                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 290                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 291
 292                 interrupt-names = "Mali_GP_IRQ",
 293                                   "Mali_GP_MMU_IRQ",
 294                                   "Mali_PP0_IRQ",
 295                                   "Mali_PP0_MMU_IRQ",
 296                                   "Mali_PP1_IRQ",
 297                                   "Mali_PP1_MMU_IRQ";
 298         };
 299
 300         fb: fb {
 301                 compatible = "rockchip,rk-fb";
 302                 rockchip,disp-mode = <NO_DUAL>;
 303         };
 304
 305         rk_screen: rk_screen {
 306                 compatible = "rockchip,screen";
 307         };
 308
 309         vop: vop@20050000 {
 310                 compatible = "rockchip,rk3228-lcdc";
 311
 312                 rockchip,cabc_mode = <0>;
 313                 rockchip,pwr18 = <0>;
 314                 rockchip,iommu-enabled = <1>;
 315                 reg = <0x20050000 0x300>;
 316                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 317                 clocks = <&aclk_vop>, <&dclk_vop0>, <&hclk_vio>;
 318                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 319         };
 320
 321         vop_mmu {
 322                 dbgname = "vop";
 323                 compatible = "rockchip,vop_mmu";
 324                 reg = <0x20053f00 0x100>;
 325                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 326                 interrupt-names = "vop_mmu";
 327         };
 328
 329         hevc_mmu {
 330                 dbgname = "hevc";
 331                 compatible = "rockchip,hevc_mmu";
 332                 reg = <0x20034440 0x40>,
 333                       <0x20034480 0x40>;
 334                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 335                 interrupt-names = "hevc_mmu";
 336         };
 337
 338         vpu_mmu {
 339                 dbgname = "vpu";
 340                 compatible = "rockchip,vpu_mmu";
 341                 reg = <0x20026800 0x100>;
 342                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 343                 interrupt-names = "vpu_mmu";
 344         };
 345
 346         iep_mmu {
 347                 dbgname = "iep";
 348                 compatible = "rockchip,iep_mmu";
 349                 reg = <0x20078800 0x100>;
 350                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 351                 interrupt-names = "iep_mmu";
 352         };
 353
 354         hdmi: hdmi@200a0000 {
 355                 compatible = "rockchip,rk3228-hdmi";
 356                 reg = <0x200a0000 0x20000>,
 357                       <0x12030000 0x10000>;
 358                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 359                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 360                 clocks = <&clk_gates14 6>, <&clk_gates3 7>, <&clk_hdmi_cec>;
 361                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 362                 rockchip,hdmi_audio_source = <0>;
 363                 rockchip,hdcp_enable = <0>;
 364                 rockchip,cec_enable = <0>;
 365                 status = "disabled";
 366         };
 367
 368         hdmi_hdcp2: hdmi_hdcp2@20090000 {
 369                 compatible = "rockchip,rk3228-hdmi-hdcp2";
 370                 reg = <0x20090000 0x10000>;
 371                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 372                 clocks = <&aclk_hdcp>,
 373                          <&clk_gates14 12>,
 374                          <&clk_gates14 11>,
 375                          <&clk_hdcp>;
 376                 clock-names = "aclk_hdcp2",
 377                               "hclk_hdcp2_mmu",
 378                               "pclk_hdcp2",
 379                               "hdcp2_clk_hdmi";
 380                 status = "disabled";
 381         };
 382
 383         tve: tve {
 384                 compatible = "rockchip,rk3228-tve";
 385                 reg = <0x20053e00 0x100>,
 386                       <0x12020000 0x10000>;
 387                 clocks = <&clk_gates10 8>;
 388                 clock-names = "pclk_vdac";
 389                 status = "disabled";
 390         };
 391
 392         emmc: rksdmmc@30020000 {
 393                 compatible = "rockchip,rk_mmc", "rockchip,rk3228-sdmmc";
 394                 reg = <0x30020000 0x10000>;
 395                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 396                 #address-cells = <1>;
 397                 #size-cells = <0>;
 398                 clocks = <&clk_emmc>, <&clk_gates7 0>;
 399                 clock-names = "clk_mmc", "hclk_mmc";
 400                 num-slots = <1>;
 401                 fifo-depth = <0x100>;
 402                 bus-width = <8>;
 403                 cru_regsbase = <0x124>;
 404                 cru_reset_offset = <3>;
 405         };
 406
 407         sdmmc: rksdmmc@30000000 {
 408                 compatible = "rockchip,rk_mmc", "rockchip,rk3228-sdmmc";
 409                 reg = <0x30000000 0x10000>;
 410                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 411                 #address-cells = <1>;
 412                 #size-cells = <0>;
 413                 clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
 414                 clock-names = "clk_mmc", "hclk_mmc";
 415                 num-slots = <1>;
 416                 fifo-depth = <0x100>;
 417                 bus-width = <4>;
 418                 cru_regsbase = <0x124>;
 419                 cru_reset_offset = <1>;
 420         };
 421
 422         sdio: rksdmmc@30010000 {
 423                 compatible = "rockchip,rk_mmc", "rockchip,rk3228-sdmmc";
 424                 reg = <0x30010000 0x10000>;
 425                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 426                 #address-cells = <1>;
 427                 #size-cells = <0>;
 428                 clocks = <&clk_sdio>, <&clk_gates5 11>;
 429                 clock-names = "clk_mmc", "hclk_mmc";
 430                 num-slots = <1>;
 431                 fifo-depth = <0x100>;
 432                 bus-width = <4>;
 433                 cru_regsbase = <0x124>;
 434                 cru_reset_offset = <2>;
 435         };
 436  };