arch/arm/boot/dts/rk3228.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/rkfb/rk_fb.h>
   3
   4 #include "skeleton.dtsi"
   5 #include "rk3228-clocks.dtsi"
   6
   7 / {
   8         compatible = "rockchip,rk3228";
   9         interrupt-parent = <&gic>;
  10
  11         aliases {
  12                 serial2 = &uart_dbg;
  13         };
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "arm,cortex-a7";
  22                         reg = <0xf00>;
  23                 };
  24                 cpu@1 {
  25                         device_type = "cpu";
  26                         compatible = "arm,cortex-a7";
  27                         reg = <0xf01>;
  28                 };
  29                 cpu@2 {
  30                         device_type = "cpu";
  31                         compatible = "arm,cortex-a7";
  32                         reg = <0xf02>;
  33                 };
  34                 cpu@3 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a7";
  37                         reg = <0xf03>;
  38                 };
  39         };
  40
  41         gic: interrupt-controller@32010000 {
  42                 compatible = "arm,cortex-a15-gic";
  43                 interrupt-controller;
  44                 #interrupt-cells = <3>;
  45                 #address-cells = <0>;
  46                 reg = <0x32011000 0x1000>,
  47                       <0x32012000 0x1000>;
  48         };
  49
  50         arm-pmu {
  51                 compatible = "arm,cortex-a7-pmu";
  52                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  53                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
  54                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
  55                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
  56         };
  57
  58         timer {
  59                 compatible = "arm,armv7-timer";
  60                 interrupts = <GIC_PPI 13
  61                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  62                              <GIC_PPI 14
  63                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  64                 clock-frequency = <24000000>;
  65         };
  66
  67         uart_dbg: serial@11030000 {
  68                 compatible = "rockchip,serial";
  69                 reg = <0x11030000 0x100>;
  70                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
  71                 clock-frequency = <24000000>;
  72                 clocks = <&xin24m>, <&xin24m>;
  73                 clock-names = "sclk_uart", "pclk_uart";
  74                 reg-shift = <2>;
  75                 reg-io-width = <4>;
  76                 status = "disabled";
  77         };
  78
  79         fiq-debugger {
  80                 compatible = "rockchip,fiq-debugger";
  81                 rockchip,serial-id = <2>;
  82                 rockchip,signal-irq = <159>;
  83                 rockchip,wake-irq = <0>;
  84                 rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
  85                 rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
  86                 status = "disabled";
  87         };
  88
  89         rockchip_clocks_init: clocks-init{
  90                 compatible = "rockchip,clocks-init";
  91                 rockchip,clocks-init-parent =
  92                         <&clk_i2s0_pll &clk_cpll>, <&clk_i2s1_pll &clk_cpll>,
  93                         <&clk_i2s2_pll &clk_cpll>, <&clk_spdif_pll &clk_cpll>,
  94                         <&clk_gpu &clk_cpll>, <&dclk_vop0 &hdmi_phy_clk>,
  95                         <&aclk_bus &clk_cpll>, <&aclk_peri &clk_cpll>,
  96                         <&clk_sdmmc0 &clk_cpll>, <&clk_emmc &clk_cpll>,
  97                         <&clk_sdio &clk_cpll>, <&aclk_vpu &clk_cpll>,
  98                         <&hdmi_phy_clk &hdmiphy_out>, <&usb480m &usb480m_phy>;
  99                 rockchip,clocks-init-rate =
 100                         <&clk_gpll 600000000>, <&clk_core 700000000>,
 101                         <&clk_cpll 500000000>, <&aclk_bus 250000000>,
 102                         <&hclk_bus 125000000>, <&pclk_bus 62500000>,
 103                         <&aclk_peri 250000000>, <&hclk_peri 125000000>,
 104                         <&pclk_peri 62500000>, <&clk_mac 125000000>,
 105                         <&aclk_iep 250000000>, <&hclk_vio 125000000>,
 106                         <&aclk_rga 250000000>, <&clk_gpu 250000000>,
 107                         <&aclk_vpu 25000000>, <&clk_vdec_core 250000000>,
 108                         <&clk_vdec_cabac 250000000>;
 109 /*
 110                 rockchip,clocks-uboot-has-init =
 111                         <&aclk_vio0>;
 112 */
 113         };
 114
 115         rockchip_clocks_enable: clocks-enable {
 116                 compatible = "rockchip,clocks-enable";
 117                 clocks =
 118                         /*PLL*/
 119                         <&clk_apll>,
 120                         <&clk_dpll>,
 121                         <&clk_gpll>,
 122                         <&clk_cpll>,
 123
 124                         /*PD_CORE*/
 125                         <&clk_core>,
 126                         <&pclk_dbg>,
 127                         <&aclk_core>,
 128                         <&clk_gates4 2>,
 129
 130                         /*PD_BUS*/
 131                         <&aclk_bus>,
 132                         <&hclk_bus>,
 133                         <&pclk_bus>,
 134                         <&clk_gates8 0>,/*aclk_intmem*/
 135                         <&clk_gates8 1>,/*clk_intmem_mbist*/
 136                         <&clk_gates8 2>,/*aclk_dmac_bus*/
 137                         <&clk_gates10 1>,/*g_aclk_bus*/
 138                         <&clk_gates13 9>,/*aclk_gic400*/
 139                         <&clk_gates8 3>,/*hclk_rom*/
 140                         <&clk_gates8 4>,/*pclk_ddrupctl*/
 141                         <&clk_gates8 6>,/*pclk_ddrmon*/
 142                         <&clk_gates9 4>,/*pclk_timer0*/
 143                         <&clk_gates9 5>,/*pclk_stimer*/
 144                         <&clk_gates10 0>,/*pclk_grf*/
 145                         <&clk_gates10 4>,/*pclk_cru*/
 146                         <&clk_gates10 6>,/*pclk_sgrf*/
 147                         <&clk_gates10 3>,/*pclk_ddrphy*/
 148                         <&clk_gates10 9>,/*pclk_phy_noc*/
 149
 150                         /*PD_PERI*/
 151                         <&aclk_peri>,
 152                         <&hclk_peri>,
 153                         <&pclk_peri>,
 154                         <&clk_gates12 0>,/*aclk_peri_noc*/
 155                         <&clk_gates12 1>,/*hclk_peri_noc*/
 156                         <&clk_gates12 2>,/*pclk_peri_noc*/
 157
 158                         <&clk_gates6 5>, /* g_clk_timer0 */
 159                         <&clk_gates6 6>, /* g_clk_timer1 */
 160
 161                         <&clk_gates7 14>, /* g_aclk_gpu */
 162                         <&clk_gates7 15>, /* g_aclk_gpu_noc */
 163
 164                         <&clk_gates1 3>;/*clk_jtag*/
 165         };
 166
 167         amba {
 168                 #address-cells = <1>;
 169                 #size-cells = <1>;
 170                 compatible = "arm,amba-bus";
 171                 interrupt-parent = <&gic>;
 172                 ranges;
 173
 174                 pdma: pdma@110f0000 {
 175                         compatible = "arm,pl330", "arm,primecell";
 176                         reg = <0x110f0000 0x4000>;
 177                         clocks = <&clk_gates8 2>;
 178                         clock-names = "apb_pclk";
 179                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 180                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 181                         #dma-cells = <1>;
 182                 };
 183         };
 184
 185         i2s0: i2s0@100c0000 {
 186                 compatible = "rockchip-i2s";
 187                 reg = <0x100c0000 0x1000>;
 188                 i2s-id = <0>;
 189                 clocks = <&clk_i2s0>, <&clk_gates8 7>;
 190                 clock-names = "i2s_clk", "i2s_hclk";
 191                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 192                 dmas = <&pdma 11>, <&pdma 12>;
 193                 #dma-cells = <2>;
 194                 dma-names = "tx", "rx";
 195         };
 196
 197         i2s1: i2s1@100b0000 {
 198                 compatible = "rockchip-i2s";
 199                 reg = <0x100b0000 0x1000>;
 200                 i2s-id = <1>;
 201                 clocks = <&clk_i2s1>, <&clk_i2s1_out>, <&clk_gates8 8>;
 202                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 203                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 204                 dmas = <&pdma 14>, <&pdma 15>;
 205                 #dma-cells = <2>;
 206                 dma-names = "tx", "rx";
 207                 status = "disabled";
 208         };
 209
 210         i2s2: i2s2@100e0000 {
 211                 compatible = "rockchip-i2s";
 212                 reg = <0x100e0000 0x1000>;
 213                 i2s-id = <2>;
 214                 clocks = <&clk_i2s2>, <&clk_gates8 9>;
 215                 clock-names = "i2s_clk", "i2s_hclk";
 216                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 217                 dmas = <&pdma 0>, <&pdma 1>;
 218                 #dma-cells = <2>;
 219                 dma-names = "tx", "rx";
 220                 status = "disabled";
 221         };
 222
 223         spdif: spdif@100d0000 {
 224                 compatible = "rockchip-spdif";
 225                 reg = <0x100d0000 0x1000>;
 226                 clocks = <&clk_spdif>, <&clk_gates8 10>;
 227                 clock-names = "spdif_mclk", "spdif_hclk";
 228                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 229                 dmas = <&pdma 10>;
 230                 #dma-cells = <1>;
 231                 dma-names = "tx";
 232                 status = "disabled";
 233         };
 234
 235         gpu {
 236                 compatible = "arm,mali400";
 237                 reg = <0x20001000 0x200>,
 238                       <0x20000000 0x100>,
 239                       <0x20003000 0x100>,
 240                       <0x20008000 0x1100>,
 241                       <0x20004000 0x100>,
 242                       <0x2000A000 0x1100>,
 243                       <0x20005000 0x100>;
 244
 245                 reg-names = "Mali_L2",
 246                             "Mali_GP",
 247                             "Mali_GP_MMU",
 248                             "Mali_PP0",
 249                             "Mali_PP0_MMU",
 250                             "Mali_PP1",
 251                             "Mali_PP1_MMU";
 252
 253                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 254                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 255                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 256                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 257                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 258                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 259
 260                 interrupt-names = "Mali_GP_IRQ",
 261                                   "Mali_GP_MMU_IRQ",
 262                                   "Mali_PP0_IRQ",
 263                                   "Mali_PP0_MMU_IRQ",
 264                                   "Mali_PP1_IRQ",
 265                                   "Mali_PP1_MMU_IRQ";
 266         };
 267
 268         fb: fb {
 269                 compatible = "rockchip,rk-fb";
 270                 rockchip,disp-mode = <NO_DUAL>;
 271         };
 272
 273         rk_screen: rk_screen {
 274                 compatible = "rockchip,screen";
 275         };
 276
 277         vop: vop@20050000 {
 278                 compatible = "rockchip,rk3228-lcdc";
 279
 280                 rockchip,cabc_mode = <0>;
 281                 rockchip,pwr18 = <0>;
 282                 rockchip,iommu-enabled = <1>;
 283                 reg = <0x20050000 0x300>;
 284                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 285                 clocks = <&aclk_vop>, <&dclk_vop0>, <&hclk_vio>;
 286                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 287         };
 288
 289         vop_mmu {
 290                 dbgname = "vop";
 291                 compatible = "rockchip,vop_mmu";
 292                 reg = <0x20053f00 0x100>;
 293                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 294                 interrupt-names = "vop_mmu";
 295         };
 296
 297         hevc_mmu {
 298                 dbgname = "hevc";
 299                 compatible = "rockchip,hevc_mmu";
 300                 reg = <0x20034440 0x40>,
 301                       <0x20034480 0x40>;
 302                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 303                 interrupt-names = "hevc_mmu";
 304         };
 305
 306         vpu_mmu {
 307                 dbgname = "vpu";
 308                 compatible = "rockchip,vpu_mmu";
 309                 reg = <0x20026800 0x100>;
 310                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 311                 interrupt-names = "vpu_mmu";
 312         };
 313
 314         iep_mmu {
 315                 dbgname = "iep";
 316                 compatible = "rockchip,iep_mmu";
 317                 reg = <0x20078800 0x100>;
 318                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 319                 interrupt-names = "iep_mmu";
 320         };
 321
 322         hdmi: hdmi@200a0000 {
 323                 compatible = "rockchip,rk3228-hdmi";
 324                 reg = <0x200a0000 0x20000>,
 325                       <0x12030000 0x10000>;
 326                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 327                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 328                 clocks = <&clk_gates14 6>, <&clk_gates3 7>, <&clk_hdmi_cec>;
 329                 clock-names = "pclk_hdmi", "hdcp_clk_hdmi", "cec_clk_hdmi";
 330                 rockchip,hdmi_audio_source = <0>;
 331                 rockchip,hdcp_enable = <0>;
 332                 rockchip,cec_enable = <0>;
 333                 status = "disabled";
 334         };
 335
 336         hdmi_hdcp2: hdmi_hdcp2@20090000 {
 337                 compatible = "rockchip,rk3228-hdmi-hdcp2";
 338                 reg = <0x20090000 0x10000>;
 339                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 340                 clocks = <&aclk_hdcp>,
 341                          <&clk_gates14 12>,
 342                          <&clk_gates14 11>,
 343                          <&clk_hdcp>;
 344                 clock-names = "aclk_hdcp2",
 345                               "hclk_hdcp2_mmu",
 346                               "pclk_hdcp2",
 347                               "hdcp2_clk_hdmi";
 348                 status = "disabled";
 349         };
 350
 351         tve: tve {
 352                 compatible = "rockchip,rk3228-tve";
 353                 reg = <0x20053e00 0x100>,
 354                       <0x12020000 0x10000>;
 355                 clocks = <&clk_gates10 8>;
 356                 clock-names = "pclk_vdac";
 357                 status = "disabled";
 358         };
 359
 360         emmc: rksdmmc@30020000 {
 361                 compatible = "rockchip,rk_mmc", "rockchip,rk3228-sdmmc";
 362                 reg = <0x30020000 0x10000>;
 363                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 364                 #address-cells = <1>;
 365                 #size-cells = <0>;
 366                 clocks = <&clk_emmc>, <&clk_gates7 0>;
 367                 clock-names = "clk_mmc", "hclk_mmc";
 368                 num-slots = <1>;
 369                 fifo-depth = <0x100>;
 370                 bus-width = <8>;
 371                 cru_regsbase = <0x124>;
 372                 cru_reset_offset = <3>;
 373         };
 374
 375         sdmmc: rksdmmc@30000000 {
 376                 compatible = "rockchip,rk_mmc", "rockchip,rk3228-sdmmc";
 377                 reg = <0x30000000 0x10000>;
 378                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 379                 #address-cells = <1>;
 380                 #size-cells = <0>;
 381                 clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
 382                 clock-names = "clk_mmc", "hclk_mmc";
 383                 num-slots = <1>;
 384                 fifo-depth = <0x100>;
 385                 bus-width = <4>;
 386                 cru_regsbase = <0x124>;
 387                 cru_reset_offset = <1>;
 388         };
 389
 390         sdio: rksdmmc@30010000 {
 391                 compatible = "rockchip,rk_mmc", "rockchip,rk3228-sdmmc";
 392                 reg = <0x30010000 0x10000>;
 393                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 394                 #address-cells = <1>;
 395                 #size-cells = <0>;
 396                 clocks = <&clk_sdio>, <&clk_gates5 11>;
 397                 clock-names = "clk_mmc", "hclk_mmc";
 398                 num-slots = <1>;
 399                 fifo-depth = <0x100>;
 400                 bus-width = <4>;
 401                 cru_regsbase = <0x124>;
 402                 cru_reset_offset = <2>;
 403         };
 404  };