arch/arm/boot/dts/rk3228.dtsi

   1 #include <dt-bindings/interrupt-controller/arm-gic.h>
   2 #include <dt-bindings/rkfb/rk_fb.h>
   3
   4 #include "skeleton.dtsi"
   5 #include "rk3228-clocks.dtsi"
   6
   7 #include <dt-bindings/pinctrl/rockchip.h>
   8 #include <dt-bindings/gpio/gpio.h>
   9
  10 / {
  11         compatible = "rockchip,rk3228";
  12         interrupt-parent = <&gic>;
  13
  14         aliases {
  15                 serial0 = &uart0;
  16                 serial1 = &uart1;
  17                 serial2 = &uart2;
  18                 i2c0 = &i2c0;
  19                 i2c1 = &i2c1;
  20                 i2c2 = &i2c2;
  21                 i2c3 = &i2c3;
  22         };
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27
  28                 cpu@0 {
  29                         device_type = "cpu";
  30                         compatible = "arm,cortex-a7";
  31                         reg = <0xf00>;
  32                 };
  33                 cpu@1 {
  34                         device_type = "cpu";
  35                         compatible = "arm,cortex-a7";
  36                         reg = <0xf01>;
  37                 };
  38                 cpu@2 {
  39                         device_type = "cpu";
  40                         compatible = "arm,cortex-a7";
  41                         reg = <0xf02>;
  42                 };
  43                 cpu@3 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a7";
  46                         reg = <0xf03>;
  47                 };
  48         };
  49
  50         psci {
  51                 compatible      = "arm,psci";
  52                 method          = "smc";
  53                 cpu_suspend     = <0x84000001>;
  54                 cpu_off         = <0x84000002>;
  55                 cpu_on          = <0x84000003>;
  56         };
  57
  58         gic: interrupt-controller@32010000 {
  59                 compatible = "arm,cortex-a15-gic";
  60                 interrupt-controller;
  61                 #interrupt-cells = <3>;
  62                 #address-cells = <0>;
  63                 reg = <0x32011000 0x1000>,
  64                       <0x32012000 0x1000>;
  65         };
  66
  67         sgrf: syscon@10140000 {
  68                 compatible = "rockchip,rk3228-sgrf", "rockchip,sgrf", "syscon";
  69                 reg = <0x10140000 0x1000>;
  70         };
  71
  72         grf: syscon@11000000 {
  73                 compatible = "rockchip,rk3228-grf", "rockchip,grf", "syscon";
  74                 reg = <0x11000000 0x1000>;
  75         };
  76
  77         cru: syscon@110e0000 {
  78                 compatible = "rockchip,rk3228-cru", "rockchip,cru", "syscon";
  79                 reg = <0x110e0000 0x1000>;
  80         };
  81
  82         ddrpctl: syscon@11200000 {
  83                 compatible = "rockchip,rk3228-ddrpctl", "syscon";
  84                 reg = <0x11200000 0x400>;
  85         };
  86
  87         msch: syscon@31020000 {
  88                 compatible = "rockchip,rk32288-msch", "rockchip,msch", "syscon";
  89                 reg = <0x31020000 0x3000>;
  90         };
  91
  92         arm-pmu {
  93                 compatible = "arm,cortex-a7-pmu";
  94                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
  95                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
  96                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
  97                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
  98         };
  99
 100         reset: reset@110e0110{
 101                 compatible = "rockchip,reset";
 102                 reg = <0x110e0110 0x20>;
 103                 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
 104                 #reset-cells = <1>;
 105         };
 106
 107         timer {
 108                 compatible = "arm,armv7-timer";
 109                 interrupts = <GIC_PPI 13
 110                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 111                              <GIC_PPI 14
 112                               (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 113                 clock-frequency = <24000000>;
 114         };
 115
 116         fiq-debugger {
 117                 compatible = "rockchip,fiq-debugger";
 118                 rockchip,serial-id = <2>;
 119                 rockchip,signal-irq = <159>;
 120                 rockchip,wake-irq = <0>;
 121                 rockchip,irq-mode-enable = <1>;  /* If enable uart uses irq instead of fiq */
 122                 rockchip,baudrate = <1500000>;  /* Only 115200 and 1500000 */
 123                 status = "disabled";
 124         };
 125
 126         rockchip_ion: rockchip-ion {
 127                 compatible = "rockchip,ion";
 128                 #address-cells = <1>;
 129                 #size-cells = <0>;
 130
 131                 ion_cma: cma-heap {
 132                          compatible = "rockchip,ion-heap";
 133                          status = "disabled";
 134                          rockchip,ion_heap = <4>;
 135                          reg = <0x10000000 0x08000000>; /* 128 MB */
 136                 };
 137                 system_heap: system-heap {
 138                         compatible = "rockchip,ion-heap";
 139                         rockchip,ion_heap = <0>;
 140                 };
 141         };
 142
 143         rockchip_clocks_init: clocks-init{
 144                 compatible = "rockchip,clocks-init";
 145                 rockchip,clocks-init-parent =
 146                         <&clk_i2s0_pll &clk_cpll>, <&clk_i2s1_pll &clk_cpll>,
 147                         <&clk_i2s2_pll &clk_cpll>, <&clk_spdif_pll &clk_cpll>,
 148                         <&clk_gpu &clk_cpll>, <&dclk_vop0 &hdmi_phy_clk>,
 149                         <&aclk_bus &clk_cpll>, <&aclk_peri &clk_cpll>,
 150                         <&clk_sdmmc0 &clk_cpll>, <&clk_emmc &clk_cpll>,
 151                         <&clk_sdio &clk_cpll>, <&aclk_vpu &clk_cpll>,
 152                         <&hdmi_phy_clk &hdmiphy_out>, <&usb480m &usb480m_phy>;
 153                 rockchip,clocks-init-rate =
 154                         <&clk_gpll 600000000>, <&clk_core 700000000>,
 155                         <&clk_cpll 500000000>, <&aclk_bus 250000000>,
 156                         <&hclk_bus 125000000>, <&pclk_bus 62500000>,
 157                         <&aclk_peri 250000000>, <&hclk_peri 125000000>,
 158                         <&pclk_peri 62500000>, <&clk_mac 125000000>,
 159                         <&aclk_iep 250000000>, <&hclk_vio 125000000>,
 160                         <&aclk_rga 250000000>, <&clk_gpu 250000000>,
 161                         <&aclk_vpu 25000000>, <&clk_vdec_core 250000000>,
 162                         <&clk_vdec_cabac 250000000>;
 163 /*
 164                 rockchip,clocks-uboot-has-init =
 165                         <&aclk_vio0>;
 166 */
 167         };
 168
 169         rockchip_clocks_enable: clocks-enable {
 170                 compatible = "rockchip,clocks-enable";
 171                 clocks =
 172                         /*PLL*/
 173                         <&clk_apll>,
 174                         <&clk_dpll>,
 175                         <&clk_gpll>,
 176                         <&clk_cpll>,
 177
 178                         /*PD_CORE*/
 179                         <&clk_core>,
 180                         <&pclk_dbg>,
 181                         <&aclk_core>,
 182                         <&clk_gates4 2>,
 183
 184                         /*PD_BUS*/
 185                         <&aclk_bus>,
 186                         <&hclk_bus>,
 187                         <&pclk_bus>,
 188                         <&clk_gates8 0>,/*aclk_intmem*/
 189                         <&clk_gates8 1>,/*clk_intmem_mbist*/
 190                         <&clk_gates8 2>,/*aclk_dmac_bus*/
 191                         <&clk_gates10 1>,/*g_aclk_bus*/
 192                         <&clk_gates13 9>,/*aclk_gic400*/
 193                         <&clk_gates8 3>,/*hclk_rom*/
 194                         <&clk_gates8 4>,/*pclk_ddrupctl*/
 195                         <&clk_gates8 6>,/*pclk_ddrmon*/
 196                         <&clk_gates9 4>,/*pclk_timer0*/
 197                         <&clk_gates9 5>,/*pclk_stimer*/
 198                         <&clk_gates10 0>,/*pclk_grf*/
 199                         <&clk_gates10 4>,/*pclk_cru*/
 200                         <&clk_gates10 6>,/*pclk_sgrf*/
 201                         <&clk_gates10 3>,/*pclk_ddrphy*/
 202                         <&clk_gates10 9>,/*pclk_phy_noc*/
 203
 204                         /*PD_PERI*/
 205                         <&aclk_peri>,
 206                         <&hclk_peri>,
 207                         <&pclk_peri>,
 208                         <&clk_gates12 0>,/*aclk_peri_noc*/
 209                         <&clk_gates12 1>,/*hclk_peri_noc*/
 210                         <&clk_gates12 2>,/*pclk_peri_noc*/
 211
 212                         <&clk_gates6 5>, /* g_clk_timer0 */
 213                         <&clk_gates6 6>, /* g_clk_timer1 */
 214
 215                         <&clk_gates7 14>, /* g_aclk_gpu */
 216                         <&clk_gates7 15>, /* g_aclk_gpu_noc */
 217
 218                         <&clk_gates1 3>;/*clk_jtag*/
 219         };
 220
 221         uart0: serial@11010000 {
 222                 compatible = "rockchip,serial";
 223                 reg = <0x11010000 0x100>;
 224                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 225                 clock-frequency = <24000000>;
 226                 clocks = <&clk_uart0>, <&clk_gates9 12>;
 227                 clock-names = "sclk_uart", "pclk_uart";
 228                 reg-shift = <2>;
 229                 reg-io-width = <4>;
 230                 dmas = <&pdma 2>, <&pdma 3>;
 231                 #dma-cells = <2>;
 232                 pinctrl-names = "default";
 233                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 234                 status = "disabled";
 235         };
 236
 237         uart1: serial@11020000 {
 238                 compatible = "rockchip,serial";
 239                 reg = <0x11020000 0x100>;
 240                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 241                 clock-frequency = <24000000>;
 242                 clocks = <&clk_uart1>, <&clk_gates9 13>;
 243                 clock-names = "sclk_uart", "pclk_uart";
 244                 reg-shift = <2>;
 245                 reg-io-width = <4>;
 246                 dmas = <&pdma 4>, <&pdma 5>;
 247                 #dma-cells = <2>;
 248                 pinctrl-names = "default";
 249                 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
 250                 status = "disabled";
 251         };
 252
 253         uart2: serial@11030000 {
 254                 compatible = "rockchip,serial";
 255                 reg = <0x11030000 0x100>;
 256                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 257                 clock-frequency = <24000000>;
 258                 clocks = <&clk_uart2>, <&clk_gates9 14>;
 259                 lock-names = "sclk_uart", "pclk_uart";
 260                 reg-shift = <2>;
 261                 reg-io-width = <4>;
 262                 dmas = <&pdma 6>, <&pdma 7>;
 263                 #dma-cells = <2>;
 264                 pinctrl-names = "default";
 265                 pinctrl-0 = <&uart2_xfer>;
 266                 status = "disabled";
 267         };
 268
 269         i2c0: i2c@11050000 {
 270                 compatible = "rockchip,rk30-i2c";
 271                 reg = <0x11050000 0x1000>;
 272                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 273                 #address-cells = <1>;
 274                 #size-cells = <0>;
 275                 pinctrl-names = "default", "gpio", "sleep";
 276                 pinctrl-0 = <&i2c0_xfer>;
 277                 pinctrl-1 = <&i2c0_gpio>;
 278                 pinctrl-2 = <&i2c0_sleep>;
 279                 gpios = <&gpio0 GPIO_A1 GPIO_ACTIVE_LOW>,
 280                         <&gpio0 GPIO_A0 GPIO_ACTIVE_LOW>;
 281                 clocks = <&clk_gates8 15>;
 282                 rockchip,check-idle = <1>;
 283                 status = "disabled";
 284         };
 285
 286         i2c1: i2c@11060000 {
 287                 compatible = "rockchip,rk30-i2c";
 288                 reg = <0x11060000 0x1000>;
 289                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 290                 #address-cells = <1>;
 291                 #size-cells = <0>;
 292                 pinctrl-names = "default", "gpio", "sleep";
 293                 pinctrl-0 = <&i2c1_xfer>;
 294                 pinctrl-1 = <&i2c1_gpio>;
 295                 pinctrl-2 = <&i2c1_sleep>;
 296                 gpios = <&gpio0 GPIO_A3 GPIO_ACTIVE_LOW>,
 297                         <&gpio0 GPIO_A2 GPIO_ACTIVE_LOW>;
 298                 clocks = <&clk_gates9 0>;
 299                 rockchip,check-idle = <1>;
 300                 status = "disabled";
 301         };
 302
 303         i2c2: i2c@11070000 {
 304                 compatible = "rockchip,rk30-i2c";
 305                 reg = <0x11070000 0x1000>;
 306                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 307                 #address-cells = <1>;
 308                 #size-cells = <0>;
 309                 pinctrl-names = "default", "gpio", "sleep";
 310                 pinctrl-0 = <&i2c2_xfer>;
 311                 pinctrl-1 = <&i2c2_gpio>;
 312                 pinctrl-2 = <&i2c2_sleep>;
 313                 gpios = <&gpio2 GPIO_C4 GPIO_ACTIVE_LOW>,
 314                         <&gpio2 GPIO_C5 GPIO_ACTIVE_LOW>;
 315                 clocks = <&clk_gates9 1>;
 316                 rockchip,check-idle = <1>;
 317                 status = "disabled";
 318         };
 319
 320         i2c3: i2c@11080000 {
 321                 compatible = "rockchip,rk30-i2c";
 322                 reg = <0x11080000 0x1000>;
 323                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 324                 #address-cells = <1>;
 325                 #size-cells = <0>;
 326                 pinctrl-names = "default", "gpio", "sleep";
 327                 pinctrl-0 = <&i2c3_xfer>;
 328                 pinctrl-1 = <&i2c3_gpio>;
 329                 pinctrl-2 = <&i2c3_sleep>;
 330                 gpios = <&gpio0 GPIO_A7 GPIO_ACTIVE_LOW>,
 331                         <&gpio0 GPIO_A6 GPIO_ACTIVE_LOW>;
 332                 clocks = <&clk_gates9 2>;
 333                 rockchip,check-idle = <1>;
 334                 status = "disabled";
 335         };
 336
 337         amba {
 338                 #address-cells = <1>;
 339                 #size-cells = <1>;
 340                 compatible = "arm,amba-bus";
 341                 interrupt-parent = <&gic>;
 342                 ranges;
 343
 344                 pdma: pdma@110f0000 {
 345                         compatible = "arm,pl330", "arm,primecell";
 346                         reg = <0x110f0000 0x4000>;
 347                         clocks = <&clk_gates8 2>;
 348                         clock-names = "apb_pclk";
 349                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 350                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 351                         #dma-cells = <1>;
 352                 };
 353         };
 354
 355         i2s0: i2s0@100c0000 {
 356                 compatible = "rockchip-i2s";
 357                 reg = <0x100c0000 0x1000>;
 358                 i2s-id = <0>;
 359                 clocks = <&clk_i2s0>, <&clk_gates8 7>;
 360                 clock-names = "i2s_clk", "i2s_hclk";
 361                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 362                 dmas = <&pdma 11>, <&pdma 12>;
 363                 #dma-cells = <2>;
 364                 dma-names = "tx", "rx";
 365         };
 366
 367         i2s1: i2s1@100b0000 {
 368                 compatible = "rockchip-i2s";
 369                 reg = <0x100b0000 0x1000>;
 370                 i2s-id = <1>;
 371                 clocks = <&clk_i2s1>, <&clk_i2s1_out>, <&clk_gates8 8>;
 372                 clock-names = "i2s_clk", "i2s_mclk", "i2s_hclk";
 373                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 374                 dmas = <&pdma 14>, <&pdma 15>;
 375                 #dma-cells = <2>;
 376                 dma-names = "tx", "rx";
 377                 status = "disabled";
 378         };
 379
 380         i2s2: i2s2@100e0000 {
 381                 compatible = "rockchip-i2s";
 382                 reg = <0x100e0000 0x1000>;
 383                 i2s-id = <2>;
 384                 clocks = <&clk_i2s2>, <&clk_gates8 9>;
 385                 clock-names = "i2s_clk", "i2s_hclk";
 386                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 387                 dmas = <&pdma 0>, <&pdma 1>;
 388                 #dma-cells = <2>;
 389                 dma-names = "tx", "rx";
 390                 status = "disabled";
 391         };
 392
 393         spdif: spdif@100d0000 {
 394                 compatible = "rockchip-spdif";
 395                 reg = <0x100d0000 0x1000>;
 396                 clocks = <&clk_spdif>, <&clk_gates8 10>;
 397                 clock-names = "spdif_mclk", "spdif_hclk";
 398                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 399                 dmas = <&pdma 10>;
 400                 #dma-cells = <1>;
 401                 dma-names = "tx";
 402                 status = "disabled";
 403         };
 404
 405         tsadc: tsadc@11150000 {
 406                 compatible = "rockchip,rk3228-tsadc";
 407                 reg = <0x11150000 0x100>;
 408                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 409                 clock-frequency = <32768>;
 410                 clocks = <&clk_tsadc>, <&clk_gates9 15>;
 411                 resets = <&reset RK3228_RST_TSADC>;
 412                 reset-names = "tsadc-apb";
 413                 #thermal-sensor-cells = <1>;
 414                 hw-shut-temp = <120000>;
 415                 pinctrl-names = "default";
 416                 pinctrl-0 = <&tsadc_gpio>;
 417                 tsadc-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
 418                 tsadc-tshut-polarity = <0>;/* tshut polarity 0:LOW 1:HIGH */
 419                 status = "okay";
 420         };
 421
 422         gpu {
 423                 compatible = "arm,mali400";
 424                 reg = <0x20001000 0x200>,
 425                       <0x20000000 0x100>,
 426                       <0x20003000 0x100>,
 427                       <0x20008000 0x1100>,
 428                       <0x20004000 0x100>,
 429                       <0x2000A000 0x1100>,
 430                       <0x20005000 0x100>;
 431
 432                 reg-names = "Mali_L2",
 433                             "Mali_GP",
 434                             "Mali_GP_MMU",
 435                             "Mali_PP0",
 436                             "Mali_PP0_MMU",
 437                             "Mali_PP1",
 438                             "Mali_PP1_MMU";
 439
 440                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 441                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 442                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 443                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 444                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 445                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 446
 447                 interrupt-names = "Mali_GP_IRQ",
 448                                   "Mali_GP_MMU_IRQ",
 449                                   "Mali_PP0_IRQ",
 450                                   "Mali_PP0_MMU_IRQ",
 451                                   "Mali_PP1_IRQ",
 452                                   "Mali_PP1_MMU_IRQ";
 453         };
 454
 455         fb: fb {
 456                 compatible = "rockchip,rk-fb";
 457                 rockchip,disp-mode = <NO_DUAL>;
 458         };
 459
 460         rk_screen: rk_screen {
 461                 compatible = "rockchip,screen";
 462         };
 463
 464         pwm0: pwm@110b0000 {
 465                 compatible = "rockchip,rk-pwm";
 466                 reg = <0x110b0000 0x10>;
 467                 /* used by driver on remotectl'pwm */
 468                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 469                 #pwm-cells = <2>;
 470                 pinctrl-names = "default";
 471                 pinctrl-0 = <&pwm0_pin>;
 472                 clocks = <&clk_gates9 7>;
 473                 clock-names = "pclk_pwm";
 474                 status = "disabled";
 475         };
 476
 477         pwm1: pwm@110b0010 {
 478                 compatible = "rockchip,rk-pwm";
 479                 reg = <0x110b0010 0x10>;
 480                 /* used by driver on remotectl'pwm */
 481                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 482                 #pwm-cells = <2>;
 483                 pinctrl-names = "default";
 484                 pinctrl-0 = <&pwm1_pin>;
 485                 clocks = <&clk_gates9 7>;
 486                 clock-names = "pclk_pwm";
 487                 status = "disabled";
 488         };
 489
 490         pwm2: pwm@110b0020 {
 491                 compatible = "rockchip,rk-pwm";
 492                 reg = <0x110b0020 0x10>;
 493                 /* used by driver on remotectl'pwm */
 494                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 495                 #pwm-cells = <2>;
 496                 pinctrl-names = "default";
 497                 pinctrl-0 = <&pwm2_pin>;
 498                 clocks = <&clk_gates9 7>;
 499                 clock-names = "pclk_pwm";
 500                 status = "disabled";
 501         };
 502
 503         pwm3: pwm@110b0030 {
 504                 compatible = "rockchip,rk-pwm";
 505                 reg = <0x110b0030 0x10>;
 506                 /* used by driver on remotectl'pwm */
 507                 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 508                 #pwm-cells = <2>;
 509                 pinctrl-names = "default";
 510                 pinctrl-0 = <&pwmir_pin>;
 511                 clocks = <&clk_gates9 7>;
 512                 clock-names = "pclk_pwm";
 513                 status = "disabled";
 514         };
 515
 516         vop: vop@20050000 {
 517                 compatible = "rockchip,rk3228-lcdc";
 518
 519                 rockchip,cabc_mode = <0>;
 520                 rockchip,pwr18 = <0>;
 521                 rockchip,iommu-enabled = <1>;
 522                 reg = <0x20050000 0x300>;
 523                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 524                 clocks = <&aclk_vop>, <&dclk_vop0>, <&hclk_vio>;
 525                 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc";
 526         };
 527
 528         vop_mmu {
 529                 dbgname = "vop";
 530                 compatible = "rockchip,vop_mmu";
 531                 reg = <0x20053f00 0x100>;
 532                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 533                 interrupt-names = "vop_mmu";
 534         };
 535
 536         hevc_mmu {
 537                 dbgname = "hevc";
 538                 compatible = "rockchip,hevc_mmu";
 539                 reg = <0x20034440 0x40>,
 540                       <0x20034480 0x40>;
 541                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 542                 interrupt-names = "hevc_mmu";
 543         };
 544
 545         vpu_mmu {
 546                 dbgname = "vpu";
 547                 compatible = "rockchip,vpu_mmu";
 548                 reg = <0x20026800 0x100>;
 549                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 550                 interrupt-names = "vpu_mmu";
 551         };
 552
 553         iep_mmu {
 554                 dbgname = "iep";
 555                 compatible = "rockchip,iep_mmu";
 556                 reg = <0x20078800 0x100>;
 557                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 558                 interrupt-names = "iep_mmu";
 559         };
 560
 561         hdmi: hdmi@200a0000 {
 562                 compatible = "rockchip,rk3228-hdmi";
 563                 reg = <0x200a0000 0x20000>,
 564                       <0x12030000 0x10000>;
 565                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 566                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 567                 clocks = <&clk_gates3 7>,
 568                          <&clk_gates14 6>,
 569                          <&clk_gates10 7>,
 570                          <&clk_hdmi_cec>;
 571                 clock-names = "hdcp_clk_hdmi",
 572                               "pclk_hdmi",
 573                               "pclk_hdmi_phy",
 574                               "cec_clk_hdmi";
 575                 pinctrl-names = "default", "gpio";
 576                 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer>;
 577                 pinctrl-1 = <&i2c3_gpio>;
 578                 rockchip,hotplug = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>;
 579                 rockchip,hdmi_audio_source = <0>;
 580                 rockchip,hdcp_enable = <0>;
 581                 rockchip,cec_enable = <0>;
 582                 status = "disabled";
 583         };
 584
 585         hdmi_hdcp2: hdmi_hdcp2@20090000 {
 586                 compatible = "rockchip,rk3228-hdmi-hdcp2";
 587                 reg = <0x20090000 0x10000>;
 588                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 589                 clocks = <&aclk_hdcp>,
 590                          <&clk_gates14 12>,
 591                          <&clk_gates14 11>,
 592                          <&clk_hdcp>;
 593                 clock-names = "aclk_hdcp2",
 594                               "hclk_hdcp2_mmu",
 595                               "pclk_hdcp2",
 596                               "hdcp2_clk_hdmi";
 597                 status = "disabled";
 598         };
 599
 600         tve: tve {
 601                 compatible = "rockchip,rk3228-tve";
 602                 reg = <0x20053e00 0x100>,
 603                       <0x12020000 0x10000>;
 604                 clocks = <&clk_gates10 8>;
 605                 clock-names = "pclk_vdac";
 606                 status = "disabled";
 607         };
 608
 609         emmc: rksdmmc@30020000 {
 610                 compatible = "rockchip,rk_mmc", "rockchip,rk3228-sdmmc";
 611                 reg = <0x30020000 0x10000>;
 612                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 613                 #address-cells = <1>;
 614                 #size-cells = <0>;
 615                 clocks = <&clk_emmc>, <&clk_gates7 0>;
 616                 clock-names = "clk_mmc", "hclk_mmc";
 617                 num-slots = <1>;
 618                 fifo-depth = <0x100>;
 619                 bus-width = <8>;
 620                 cru_regsbase = <0x124>;
 621                 cru_reset_offset = <3>;
 622         };
 623
 624         sdmmc: rksdmmc@30000000 {
 625                 compatible = "rockchip,rk_mmc", "rockchip,rk3228-sdmmc";
 626                 reg = <0x30000000 0x10000>;
 627                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 628                 #address-cells = <1>;
 629                 #size-cells = <0>;
 630                 clocks = <&clk_sdmmc0>, <&clk_gates5 10>;
 631                 clock-names = "clk_mmc", "hclk_mmc";
 632                 num-slots = <1>;
 633                 fifo-depth = <0x100>;
 634                 bus-width = <4>;
 635                 cru_regsbase = <0x124>;
 636                 cru_reset_offset = <1>;
 637         };
 638
 639         sdio: rksdmmc@30010000 {
 640                 compatible = "rockchip,rk_mmc", "rockchip,rk3228-sdmmc";
 641                 reg = <0x30010000 0x10000>;
 642                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 643                 #address-cells = <1>;
 644                 #size-cells = <0>;
 645                 clocks = <&clk_sdio>, <&clk_gates5 11>;
 646                 clock-names = "clk_mmc", "hclk_mmc";
 647                 num-slots = <1>;
 648                 fifo-depth = <0x100>;
 649                 bus-width = <4>;
 650                 cru_regsbase = <0x124>;
 651                 cru_reset_offset = <2>;
 652         };
 653
 654         pinctrl: pinctrl {
 655                 compatible = "rockchip,rk3228-pinctrl";
 656                 rockchip,grf = <&grf>;
 657                 #address-cells = <1>;
 658                 #size-cells = <1>;
 659                 ranges;
 660
 661                 gpio0: gpio0@11110000 {
 662                         compatible = "rockchip,gpio-bank";
 663                         reg =   <0x11110000 0x100>;
 664                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 665                         clocks = <&clk_gates9 9>;
 666
 667                         gpio-controller;
 668                         #gpio-cells = <2>;
 669
 670                         interrupt-controller;
 671                         #interrupt-cells = <2>;
 672                 };
 673
 674                 gpio1: gpio1@11120000 {
 675                         compatible = "rockchip,gpio-bank";
 676                         reg = <0x11120000 0x100>;
 677                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 678                         clocks = <&clk_gates9 9>;
 679
 680                         gpio-controller;
 681                         #gpio-cells = <2>;
 682
 683                         interrupt-controller;
 684                         #interrupt-cells = <2>;
 685                 };
 686
 687                 gpio2: gpio2@11130000 {
 688                         compatible = "rockchip,gpio-bank";
 689                         reg = <0x11130000 0x100>;
 690                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 691                         clocks = <&clk_gates9 10>;
 692
 693                         gpio-controller;
 694                         #gpio-cells = <2>;
 695
 696                         interrupt-controller;
 697                         #interrupt-cells = <2>;
 698                 };
 699
 700                 gpio3: gpio3@11140000 {
 701                         compatible = "rockchip,gpio-bank";
 702                         reg = <0x11140000 0x100>;
 703                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 704                         clocks = <&clk_gates9 11>;
 705
 706                         gpio-controller;
 707                         #gpio-cells = <2>;
 708
 709                         interrupt-controller;
 710                         #interrupt-cells = <2>;
 711                 };
 712
 713                 pcfg_pull_up: pcfg-pull-up {
 714                         bias-pull-up;
 715                 };
 716
 717                 pcfg_pull_down: pcfg-pull-down {
 718                         bias-pull-down;
 719                 };
 720
 721                 pcfg_pull_none: pcfg-pull-none {
 722                         bias-disable;
 723                 };
 724
 725                 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
 726                         drive-strength = <8>;
 727                 };
 728
 729                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
 730                         drive-strength = <12>;
 731                 };
 732
 733                 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
 734                         bias-pull-up;
 735                         drive-strength = <8>;
 736                 };
 737
 738                 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
 739                         drive-strength = <4>;
 740                 };
 741
 742                 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
 743                         bias-pull-up;
 744                         drive-strength = <4>;
 745                 };
 746
 747                 pcfg_pull_down_drv_12ma: pcfg-pull-down-drv-12ma {
 748                         bias-pull-down;
 749                         drive-strength = <12>;
 750                 };
 751
 752                 pcfg_output_high: pcfg-output-high {
 753                         output-high;
 754                 };
 755
 756                 pcfg_output_low: pcfg-output-low {
 757                         output-low;
 758                 };
 759
 760                 pcfg_input_high: pcfg-input-high {
 761                         bias-pull-up;
 762                         input-enable;
 763                 };
 764
 765                 i2c0 {
 766                         i2c0_xfer: i2c0-xfer {
 767                                 rockchip,pins = <0 GPIO_A0 RK_FUNC_1 &pcfg_pull_none>,
 768                                                 <0 GPIO_A1 RK_FUNC_1 &pcfg_pull_none>;
 769                         };
 770                         i2c0_gpio: i2c0-gpio {
 771                                 rockchip,pins = <0 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_none>,
 772                                                 <0 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_none>;
 773                         };
 774                         i2c0_sleep: i2c0-sleep {
 775                                 rockchip,pins = <0 GPIO_A0 RK_FUNC_GPIO &pcfg_input_high>,
 776                                                 <0 GPIO_A1 RK_FUNC_GPIO &pcfg_input_high>;
 777                         };
 778                 };
 779
 780                 i2c1 {
 781                         i2c1_xfer: i2c1-xfer {
 782                                 rockchip,pins = <0 GPIO_A2 RK_FUNC_1 &pcfg_pull_none>,
 783                                                 <0 GPIO_A3 RK_FUNC_1 &pcfg_pull_none>;
 784                         };
 785                         i2c1_gpio: i2c1-gpio {
 786                                 rockchip,pins = <0 GPIO_A2  RK_FUNC_GPIO &pcfg_pull_none>,
 787                                                 <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_none>;
 788                         };
 789                         i2c1_sleep: i2c1-sleep {
 790                                 rockchip,pins = <0 GPIO_A2 RK_FUNC_GPIO &pcfg_input_high>,
 791                                                 <0 GPIO_A3 RK_FUNC_GPIO &pcfg_input_high>;
 792
 793                         };
 794                 };
 795
 796                 i2c2 {
 797                         i2c2_xfer: i2c2-xfer {
 798                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
 799                                                 <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
 800                         };
 801                         i2c2_gpio: i2c2-gpio {
 802                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_none>,
 803                                                 <2 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_none>;
 804                         };
 805                         i2c2_sleep: i2c2-sleep {
 806                                 rockchip,pins = <2 GPIO_C5 RK_FUNC_GPIO &pcfg_input_high>,
 807                                                 <2 GPIO_C4 RK_FUNC_GPIO &pcfg_input_high>;
 808                         };
 809                 };
 810
 811                 i2c3 {
 812                         i2c3_xfer: i2c3-xfer {
 813                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>,
 814                                                 <0 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
 815                         };
 816                         i2c3_gpio: i2c3-gpio {
 817                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_pull_none>,
 818                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_none>;
 819                         };
 820                         i2c3_sleep: i2c3-sleep {
 821                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_GPIO &pcfg_input_high>,
 822                                                 <0 GPIO_A7 RK_FUNC_GPIO &pcfg_input_high>;
 823                         };
 824                 };
 825
 826                 uart0 {
 827                         uart0_xfer: uart0-xfer {
 828                                 rockchip,pins = <2 GPIO_D2 RK_FUNC_1 &pcfg_pull_up>,
 829                                                 <2 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
 830                         };
 831
 832                         uart0_cts: uart0-cts {
 833                                 rockchip,pins = <2 GPIO_D5 RK_FUNC_1 &pcfg_pull_none>;
 834                         };
 835
 836                         uart0_rts: uart0-rts {
 837                                 rockchip,pins = <0 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>;
 838                         };
 839
 840                         uart0_rts_gpio: uart0-rts-gpio {
 841                                 rockchip,pins = <0 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_none>;
 842                         };
 843                 };
 844
 845                 uart1 {
 846                         uart1_xfer: uart1-xfer {
 847                                 rockchip,pins = <1 GPIO_B2 RK_FUNC_1 &pcfg_pull_up>,
 848                                                 <1 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>;
 849                         };
 850
 851                         uart1_cts: uart1-cts {
 852                                 rockchip,pins = <1 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>;
 853                         };
 854
 855                         uart1_rts: uart1-rts {
 856                                 rockchip,pins = <1 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;
 857                         };
 858                 };
 859
 860                 uart11 {
 861                         uart11_xfer: uart11-xfer {
 862                                 rockchip,pins = <3 GPIO_B6 RK_FUNC_1 &pcfg_pull_up>,
 863                                                 <3 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
 864                         };
 865
 866                         uart11_cts: uart11-cts {
 867                                 rockchip,pins = <3 GPIO_A7 RK_FUNC_1 &pcfg_pull_none>;
 868                         };
 869
 870                         uart11_rts: uart11-rts {
 871                                 rockchip,pins = <3 GPIO_A6 RK_FUNC_1 &pcfg_pull_none>;
 872                         };
 873                 };
 874
 875                 uart2 {
 876                         uart2_xfer: uart2-xfer {
 877                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_2 &pcfg_pull_up>,
 878                                                 <1 GPIO_C3 RK_FUNC_2 &pcfg_pull_none>;
 879                         };
 880
 881                         uart2_cts: uart2-cts {
 882                                 rockchip,pins = <0 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>;
 883                         };
 884
 885                         uart2_rts: uart2-rts {
 886                                 rockchip,pins = <0 GPIO_D0 RK_FUNC_1 &pcfg_pull_none>;
 887                         };
 888                 };
 889
 890                 uart21 {
 891                         uart21_xfer: uart21-xfer {
 892                                 rockchip,pins = <1 GPIO_B2 RK_FUNC_2 &pcfg_pull_up>,
 893                                                 <1 GPIO_B1 RK_FUNC_2 &pcfg_pull_none>;
 894                         };
 895                 };
 896
 897                 spi0 {
 898                         spi0_clk: spi0-clk {
 899                                 rockchip,pins = <0 GPIO_B1 RK_FUNC_2 &pcfg_pull_up>;
 900                         };
 901                         spi0_cs0: spi0-cs0 {
 902                                 rockchip,pins = <0 GPIO_B6 RK_FUNC_2 &pcfg_pull_up>;
 903                         };
 904                         spi0_tx: spi0-tx {
 905                                 rockchip,pins = <0 GPIO_B3 RK_FUNC_2 &pcfg_pull_up>;
 906                         };
 907                         spi0_rx: spi0-rx {
 908                                 rockchip,pins = <0 GPIO_B5 RK_FUNC_2 &pcfg_pull_up>;
 909                         };
 910                         spi0_cs1: spi0-cs1 {
 911                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_1 &pcfg_pull_up>;
 912                         };
 913                 };
 914
 915                 spi1 {
 916                         spi1_clk: spi1-clk {
 917                                 rockchip,pins = <0 GPIO_C7 RK_FUNC_2 &pcfg_pull_up>;
 918                         };
 919                         spi1_cs0: spi1-cs0 {
 920                                 rockchip,pins = <2 GPIO_A2 RK_FUNC_2 &pcfg_pull_up>;
 921                         };
 922                         spi1_rx: spi1-rx {
 923                                 rockchip,pins = <2 GPIO_A0 RK_FUNC_2 &pcfg_pull_up>;
 924                         };
 925                         spi1_tx: spi1-tx {
 926                                 rockchip,pins = <2 GPIO_A1 RK_FUNC_2 &pcfg_pull_up>;
 927                         };
 928                         spi1_cs1: spi1-cs1 {
 929                                 rockchip,pins = <2 GPIO_A3 RK_FUNC_2 &pcfg_pull_up>;
 930                         };
 931                 };
 932
 933                 i2s {
 934                         i2s_mclk: i2s-mclk {
 935                                 rockchip,pins = <0 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>;
 936                         };
 937
 938                         i2s_sclk:i2s-sclk {
 939                                 rockchip,pins = <0 GPIO_B1 RK_FUNC_1 &pcfg_pull_none>;
 940                         };
 941
 942                         i2s_lrckrx:i2s-lrckrx {
 943                                 rockchip,pins = <0 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>;
 944                         };
 945
 946                         i2s_lrcktx:i2s-lrcktx {
 947                                 rockchip,pins = <0 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>;
 948                         };
 949
 950                         i2s_sdi:i2s-sdi {
 951                                 rockchip,pins = <0 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>;
 952                         };
 953
 954                         i2s_sdo0:i2s-sdo0 {
 955                                 rockchip,pins = <0 GPIO_B5 RK_FUNC_1 &pcfg_pull_none>;
 956                         };
 957
 958                         i2s_sdo1:i2s-sdo1 {
 959                                 rockchip,pins = <1 GPIO_A2 RK_FUNC_2 &pcfg_pull_none>;
 960                         };
 961
 962                         i2s_sdo2:i2s-sdo2 {
 963                                 rockchip,pins = <1 GPIO_A4 RK_FUNC_2 &pcfg_pull_none>;
 964                         };
 965
 966                         i2s_sdo3:i2s-sdo3 {
 967                                 rockchip,pins = <1 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
 968                         };
 969
 970                         i2s_gpio: i2s-gpio {
 971                                 rockchip,pins = <0 GPIO_B0  RK_FUNC_GPIO &pcfg_pull_none>,
 972                                                 <0 GPIO_B1 RK_FUNC_GPIO &pcfg_pull_none>,
 973                                                 <0 GPIO_B3 RK_FUNC_GPIO &pcfg_pull_none>,
 974                                                 <0 GPIO_B4 RK_FUNC_GPIO &pcfg_pull_none>,
 975                                                 <0 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_none>,
 976                                                 <0 GPIO_B5 RK_FUNC_GPIO &pcfg_pull_none>,
 977                                                 <1 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_none>,
 978                                                 <1 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_none>,
 979                                                 <1 GPIO_A5 RK_FUNC_GPIO &pcfg_pull_none>;
 980                         };
 981                 };
 982
 983                 spdif0 {
 984                         spdif0_tx: spdif0-tx {
 985                                 rockchip,pins = <3 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
 986                         };
 987                 };
 988
 989                 spdif1 {
 990                         spdif1_tx: spdif1-tx {
 991                                 rockchip,pins = <3 GPIO_D7 RK_FUNC_2 &pcfg_pull_none>;
 992                         };
 993                 };
 994
 995                 sdmmc {
 996                         sdmmc_clk: sdmmc-clk {
 997                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
 998                         };
 999
1000                         sdmmc_cmd: sdmmc-cmd {
1001                                 rockchip,pins = <1 GPIO_B7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1002                         };
1003
1004                         sdmmc_dectn: sdmmc-dectn {
1005                                 rockchip,pins = <1 GPIO_C1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1006                         };
1007
1008                         sdmmc_wrprt: sdmmc-wrprt {
1009                                 rockchip,pins = <1 GPIO_A7 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1010                         };
1011
1012                         sdmmc_pwren: sdmmc-pwren {
1013                                 rockchip,pins = <1 GPIO_B6 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1014                         };
1015
1016                         sdmmc_bus1: sdmmc-bus1 {
1017                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1018                         };
1019
1020                         sdmmc_bus4: sdmmc-bus4 {
1021                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1022                                                 <1 GPIO_C3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1023                                                 <1 GPIO_C4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1024                                                 <1 GPIO_C5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1025                         };
1026
1027                         sdmmc_gpio: sdmmc-gpio {
1028                                 rockchip,pins = <1 GPIO_C0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1029                                                 <1 GPIO_B7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1030                                                 <1 GPIO_C1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1031                                                 <1 GPIO_A7 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1032                                                 <1 GPIO_B6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1033                                                 <1 GPIO_C2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1034                                                 <1 GPIO_C3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1035                                                 <1 GPIO_C4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1036                                                 <1 GPIO_C5 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;
1037                         };
1038                 };
1039
1040                 sdio0 {
1041                         sdio0_bus1: sdio0-bus1 {
1042                                 rockchip,pins = <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1043                         };
1044
1045                         sdio0_bus4: sdio0-bus4 {
1046                                 rockchip,pins = <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1047                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1048                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1049                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1050                         };
1051
1052                         sdio0_cmd: sdio0-cmd {
1053                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_2 &pcfg_pull_up_drv_4ma>;
1054                         };
1055
1056                         sdio0_clk: sdio0-clk {
1057                                 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1058                         };
1059
1060                         sdio0_pwren: sdio0-pwren {
1061                                 rockchip,pins = <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_up>;
1062                         };
1063
1064                         sdio0_gpio: sdio0-gpio {
1065                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1066                                                 <1 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1067                                                 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1068                                                 <1 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1069                                                 <1 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1070                                                 <1 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1071                                                 <1 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;
1072                         };
1073                 };
1074
1075
1076                 sdio1 {
1077                         sdio1_bus1: sdio1-bus1 {
1078                                 rockchip,pins = <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1079                         };
1080
1081                         sdio1_bus4: sdio1-bus4 {
1082                                 rockchip,pins = <1 GPIO_A1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1083                                                 <1 GPIO_A2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1084                                                 <1 GPIO_A4 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
1085                                                 <1 GPIO_A5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
1086                         };
1087
1088                         sdio1_cmd: sdio1-cmd {
1089                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_2 &pcfg_pull_up_drv_4ma>;
1090                         };
1091
1092                         sdio1_clk: sdio1-clk {
1093                                 rockchip,pins = <1 GPIO_A0 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
1094                         };
1095
1096                         sdio1_pwren: sdio1-pwren {
1097                                 rockchip,pins = <0 GPIO_D6 RK_FUNC_1 &pcfg_pull_up>;
1098                         };
1099
1100                         sdio1_gpio: sdio1-gpio {
1101                                 rockchip,pins = <0 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1102                                                 <1 GPIO_A0 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1103                                                 <0 GPIO_D6 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1104                                                 <1 GPIO_A1 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1105                                                 <1 GPIO_A2 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1106                                                 <1 GPIO_A3 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>,
1107                                                 <1 GPIO_A4 RK_FUNC_GPIO &pcfg_pull_up_drv_4ma>;
1108                         };
1109                 };
1110
1111                 emmc {
1112                         emmc_clk: emmc-clk {
1113                                 rockchip,pins = <2 GPIO_A7 RK_FUNC_2 &pcfg_pull_none_drv_8ma>;
1114                         };
1115
1116                         emmc_cmd: emmc-cmd {
1117                                 rockchip,pins = <1 GPIO_C6 RK_FUNC_2 &pcfg_pull_up_drv_8ma>;
1118                         };
1119
1120                         emmc_pwren: emmc-pwren {
1121                                 rockchip,pins = <2 GPIO_A5 RK_FUNC_2 &pcfg_pull_none>;
1122                         };
1123
1124                         emmc_rstnout: emmc_rstnout {
1125                                 rockchip,pins = <1 GPIO_C7 RK_FUNC_2 &pcfg_pull_none>;
1126                         };
1127
1128                         emmc_bus1: emmc-bus1 {
1129                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
1130                         };
1131
1132                         emmc_bus4: emmc-bus4 {
1133                                 rockchip,pins = <1 GPIO_C2 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
1134                                                 <1 GPIO_C3 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
1135                                                 <1 GPIO_C4 RK_FUNC_1 &pcfg_pull_up_drv_8ma>,
1136                                                 <1 GPIO_C5 RK_FUNC_1 &pcfg_pull_up_drv_8ma>;
1137                         };
1138                 };
1139
1140                 pwm0 {
1141                         pwm0_pin: pwm0-pin {
1142                                 rockchip,pins = <0 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1143                         };
1144                 };
1145
1146                 pwm1 {
1147                         pwm1_pin: pwm1-pin {
1148                                 rockchip,pins = <0 GPIO_D3 RK_FUNC_1 &pcfg_pull_none>;
1149                         };
1150                 };
1151
1152                 pwm2 {
1153                         pwm2_pin: pwm2-pin {
1154                                 rockchip,pins = <0 GPIO_D4 RK_FUNC_1 &pcfg_pull_none>;
1155                         };
1156                 };
1157
1158                 pwmir {
1159                         pwmir_pin: pwmir-pin {
1160                                 rockchip,pins = <3 GPIO_D2 RK_FUNC_1 &pcfg_pull_none>;
1161                         };
1162                 };
1163
1164                 pwm10 {
1165                         pwm10_pin: pwm10-pin {
1166                                 rockchip,pins = <3 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>;
1167                         };
1168                 };
1169
1170                 pwm11 {
1171                         pwm11_pin: pwm11-pin {
1172                                 rockchip,pins = <0 GPIO_D6 RK_FUNC_2 &pcfg_pull_none>;
1173                         };
1174                 };
1175
1176                 pwm12 {
1177                         pwm12_pin: pwm12-pin {
1178                                 rockchip,pins = <1 GPIO_B4 RK_FUNC_2 &pcfg_pull_none>;
1179                         };
1180                 };
1181
1182                 pwm1ir {
1183                         pwm1ir_pin: pwm1ir-pin {
1184                                 rockchip,pins = <1 GPIO_B3 RK_FUNC_2 &pcfg_pull_none>;
1185                         };
1186                 };
1187
1188                 gmac {
1189                         rgmii_pins: rgmii-pins {
1190                                 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,
1191                                                 <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,
1192                                                 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,
1193                                                 <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1194                                                 <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1195                                                 <2 GPIO_C6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1196                                                 <2 GPIO_C7 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1197                                                 <2 GPIO_B1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1198                                                 <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1199                                                 <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,
1200                                                 <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1201                                                 <2 GPIO_C5 RK_FUNC_1 &pcfg_pull_none>,
1202                                                 <2 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>,
1203                                                 <2 GPIO_B3 RK_FUNC_1 &pcfg_pull_none>,
1204                                                 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>;
1205                         };
1206
1207                         rmii_pins: rmii-pins {
1208                                 rockchip,pins = <2 GPIO_B6 RK_FUNC_1 &pcfg_pull_none>,
1209                                                 <2 GPIO_B4 RK_FUNC_1 &pcfg_pull_none>,
1210                                                 <2 GPIO_D1 RK_FUNC_1 &pcfg_pull_none>,
1211                                                 <2 GPIO_C3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1212                                                 <2 GPIO_C2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1213                                                 <2 GPIO_B5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1214                                                 <2 GPIO_C1 RK_FUNC_1 &pcfg_pull_none>,
1215                                                 <2 GPIO_C0 RK_FUNC_1 &pcfg_pull_none>,
1216                                                 <2 GPIO_B0 RK_FUNC_1 &pcfg_pull_none>,
1217                                                 <2 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1218                         };
1219                 };
1220
1221                 tsadc_pin {
1222                         tsadc_int: tsadc-int {
1223                                 rockchip,pins = <0 GPIO_D0 RK_FUNC_2 &pcfg_pull_none>;
1224                         };
1225                         tsadc_gpio: tsadc-gpio {
1226                                 rockchip,pins = <0 GPIO_D0 RK_FUNC_GPIO &pcfg_pull_none>;
1227                         };
1228                 };
1229
1230                 hdmi_pin {
1231                         hdmi_cec: hdmi-cec {
1232                                 rockchip,pins = <0 GPIO_C4 RK_FUNC_1 &pcfg_pull_none>;
1233                         };
1234
1235                         hdmi_hpd: hdmi-hpd {
1236                                 rockchip,pins = <0 GPIO_B7 RK_FUNC_1 &pcfg_pull_none>;
1237                         };
1238                 };
1239
1240                 hdmi_i2c {
1241                         hdmii2c_xfer: hdmii2c-xfer {
1242                                 rockchip,pins = <0 GPIO_A6 RK_FUNC_2 &pcfg_pull_none>,
1243                                                 <0 GPIO_A7 RK_FUNC_2 &pcfg_pull_none>;
1244                         };
1245                 };
1246         };
1247 };