arch/arm/boot/dts/rk322x.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3228-cru.h>
  46 #include <dt-bindings/suspend/rockchip-rk322x.h>
  47 #include <dt-bindings/soc/rockchip,boot-mode.h>
  48 #include <dt-bindings/thermal/thermal.h>
  49 #include "skeleton.dtsi"
  50
  51 / {
  52         interrupt-parent = <&gic>;
  53
  54         aliases {
  55                 serial0 = &uart0;
  56                 serial1 = &uart1;
  57                 serial2 = &uart2;
  58                 spi0 = &spi0;
  59         };
  60
  61         cpus {
  62                 #address-cells = <1>;
  63                 #size-cells = <0>;
  64
  65                 cpu0: cpu@f00 {
  66                         device_type = "cpu";
  67                         compatible = "arm,cortex-a7";
  68                         reg = <0xf00>;
  69                         resets = <&cru SRST_CORE0>;
  70                         operating-points-v2 = <&cpu0_opp_table>;
  71                         #cooling-cells = <2>; /* min followed by max */
  72                         dynamic-power-coefficient = <122>;
  73                         clock-latency = <40000>;
  74                         clocks = <&cru ARMCLK>;
  75                 };
  76
  77                 cpu1: cpu@f01 {
  78                         device_type = "cpu";
  79                         compatible = "arm,cortex-a7";
  80                         reg = <0xf01>;
  81                         resets = <&cru SRST_CORE1>;
  82                         operating-points-v2 = <&cpu0_opp_table>;
  83                 };
  84
  85                 cpu2: cpu@f02 {
  86                         device_type = "cpu";
  87                         compatible = "arm,cortex-a7";
  88                         reg = <0xf02>;
  89                         resets = <&cru SRST_CORE2>;
  90                         operating-points-v2 = <&cpu0_opp_table>;
  91                 };
  92
  93                 cpu3: cpu@f03 {
  94                         device_type = "cpu";
  95                         compatible = "arm,cortex-a7";
  96                         reg = <0xf03>;
  97                         resets = <&cru SRST_CORE3>;
  98                         operating-points-v2 = <&cpu0_opp_table>;
  99                 };
 100         };
 101
 102         cpu0_opp_table: opp_table0 {
 103                 compatible = "operating-points-v2";
 104                 opp-shared;
 105
 106                 nvmem-cells = <&cpu_leakage>;
 107                 nvmem-cell-names = "cpu_leakage";
 108
 109                 opp-408000000 {
 110                         opp-hz = /bits/ 64 <408000000>;
 111                         opp-microvolt = <950000>;
 112                         clock-latency-ns = <40000>;
 113                         opp-suspend;
 114                 };
 115                 opp-600000000 {
 116                         opp-hz = /bits/ 64 <600000000>;
 117                         opp-microvolt = <975000>;
 118                 };
 119                 opp-816000000 {
 120                         opp-hz = /bits/ 64 <816000000>;
 121                         opp-microvolt = <1000000>;
 122                 };
 123                 opp-1008000000 {
 124                         opp-hz = /bits/ 64 <1008000000>;
 125                         opp-microvolt = <1175000>;
 126                 };
 127                 opp-1200000000 {
 128                         opp-hz = /bits/ 64 <1200000000>;
 129                         opp-microvolt = <1275000>;
 130                 };
 131         };
 132
 133         amba {
 134                 compatible = "arm,amba-bus";
 135                 #address-cells = <1>;
 136                 #size-cells = <1>;
 137                 ranges;
 138
 139                 pdma: pdma@110f0000 {
 140                         compatible = "arm,pl330", "arm,primecell";
 141                         reg = <0x110f0000 0x4000>;
 142                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 143                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 144                         #dma-cells = <1>;
 145                         clocks = <&cru ACLK_DMAC>;
 146                         clock-names = "apb_pclk";
 147                         peripherals-req-type-burst;
 148                 };
 149         };
 150
 151         arm-pmu {
 152                 compatible = "arm,cortex-a7-pmu";
 153                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 154                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
 155                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 156                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 157                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 158         };
 159
 160         timer {
 161                 compatible = "arm,armv7-timer";
 162                 arm,cpu-registers-not-fw-configured;
 163                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 164                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 165                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 166                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 167                 clock-frequency = <24000000>;
 168         };
 169
 170         xin24m: oscillator {
 171                 compatible = "fixed-clock";
 172                 clock-frequency = <24000000>;
 173                 clock-output-names = "xin24m";
 174                 #clock-cells = <0>;
 175         };
 176
 177         i2s1: i2s1@100b0000 {
 178                 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
 179                 reg = <0x100b0000 0x4000>;
 180                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 181                 #address-cells = <1>;
 182                 #size-cells = <0>;
 183                 clock-names = "i2s_clk", "i2s_hclk";
 184                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 185                 dmas = <&pdma 14>, <&pdma 15>;
 186                 dma-names = "tx", "rx";
 187                 pinctrl-names = "default";
 188                 pinctrl-0 = <&i2s1_bus>;
 189                 status = "disabled";
 190         };
 191
 192         i2s0: i2s0@100c0000 {
 193                 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
 194                 reg = <0x100c0000 0x4000>;
 195                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 196                 #address-cells = <1>;
 197                 #size-cells = <0>;
 198                 clock-names = "i2s_clk", "i2s_hclk";
 199                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 200                 dmas = <&pdma 11>, <&pdma 12>;
 201                 dma-names = "tx", "rx";
 202                 status = "disabled";
 203         };
 204
 205         spdif: spdif@100d0000 {
 206                 compatible = "rockchip,rk3228-spdif";
 207                 reg = <0x100d0000 0x1000>;
 208                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 209                 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
 210                 clock-names = "mclk", "hclk";
 211                 dmas = <&pdma 10>;
 212                 #dma-cells = <1>;
 213                 dma-names = "tx";
 214                 pinctrl-names = "default";
 215                 pinctrl-0 = <&spdif_tx>;
 216                 status = "disabled";
 217         };
 218
 219         i2s2: i2s2@100e0000 {
 220                 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
 221                 reg = <0x100e0000 0x4000>;
 222                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 223                 #address-cells = <1>;
 224                 #size-cells = <0>;
 225                 clock-names = "i2s_clk", "i2s_hclk";
 226                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 227                 dmas = <&pdma 0>, <&pdma 1>;
 228                 dma-names = "tx", "rx";
 229                 status = "disabled";
 230         };
 231
 232         grf: syscon@11000000 {
 233                 compatible = "syscon", "simple-mfd";
 234                 reg = <0x11000000 0x1000>;
 235                 #address-cells = <1>;
 236                 #size-cells = <1>;
 237
 238                 io_domains: io-domains {
 239                         compatible = "rockchip,rk322x-io-voltage-domain";
 240                         status = "disabled";
 241                 };
 242
 243                 reboot-mode {
 244                         compatible = "syscon-reboot-mode";
 245                         offset = <0x5c8>;
 246                         mode-normal = <BOOT_NORMAL>;
 247                         mode-recovery = <BOOT_RECOVERY>;
 248                         mode-bootloader = <BOOT_FASTBOOT>;
 249                         mode-loader = <BOOT_BL_DOWNLOAD>;
 250                         mode-ums = <BOOT_UMS>;
 251                 };
 252
 253                 u2phy0: usb2-phy@760 {
 254                         compatible = "rockchip,rk322x-usb2phy";
 255                         reg = <0x0760 0x0c>;
 256                         clocks = <&cru SCLK_OTGPHY0>;
 257                         clock-names = "phyclk";
 258                         #clock-cells = <0>;
 259                         clock-output-names = "usb480m_phy0";
 260                         status = "disabled";
 261
 262                         u2phy0_otg: otg-port {
 263                                 #phy-cells = <0>;
 264                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 265                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 266                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 267                                 interrupt-names = "otg-bvalid", "otg-id",
 268                                                   "linestate";
 269                                 status = "disabled";
 270                         };
 271
 272                         u2phy0_host: host-port {
 273                                 #phy-cells = <0>;
 274                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 275                                 interrupt-names = "linestate";
 276                                 status = "disabled";
 277                         };
 278                 };
 279
 280                 u2phy1: usb2-phy@800 {
 281                         compatible = "rockchip,rk322x-usb2phy";
 282                         reg = <0x0800 0x0c>;
 283                         clocks = <&cru SCLK_OTGPHY1>;
 284                         clock-names = "phyclk";
 285                         #clock-cells = <0>;
 286                         clock-output-names = "usb480m_phy1";
 287                         status = "disabled";
 288
 289                         u2phy1_otg: otg-port {
 290                                 #phy-cells = <0>;
 291                                 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 292                                 interrupt-names = "linestate";
 293                                 status = "disabled";
 294                         };
 295
 296                         u2phy1_host: host-port {
 297                                 #phy-cells = <0>;
 298                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 299                                 interrupt-names = "linestate";
 300                                 status = "disabled";
 301                         };
 302                 };
 303         };
 304
 305         uart0: serial@11010000 {
 306                 compatible = "snps,dw-apb-uart";
 307                 reg = <0x11010000 0x100>;
 308                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 309                 clock-frequency = <24000000>;
 310                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 311                 clock-names = "baudclk", "apb_pclk";
 312                 pinctrl-names = "default";
 313                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 314                 reg-shift = <2>;
 315                 reg-io-width = <4>;
 316                 status = "disabled";
 317         };
 318
 319         uart1: serial@11020000 {
 320                 compatible = "snps,dw-apb-uart";
 321                 reg = <0x11020000 0x100>;
 322                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 323                 clock-frequency = <24000000>;
 324                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 325                 clock-names = "baudclk", "apb_pclk";
 326                 pinctrl-names = "default";
 327                 pinctrl-0 = <&uart1_xfer>;
 328                 reg-shift = <2>;
 329                 reg-io-width = <4>;
 330                 status = "disabled";
 331         };
 332
 333         uart2: serial@11030000 {
 334                 compatible = "snps,dw-apb-uart";
 335                 reg = <0x11030000 0x100>;
 336                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 337                 clock-frequency = <24000000>;
 338                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 339                 clock-names = "baudclk", "apb_pclk";
 340                 pinctrl-names = "default";
 341                 pinctrl-0 = <&uart21_xfer>;
 342                 reg-shift = <2>;
 343                 reg-io-width = <4>;
 344                 status = "disabled";
 345         };
 346
 347         efuse: efuse@11040000 {
 348                 compatible = "rockchip,rk322x-efuse";
 349                 reg = <0x11040000 0x20>;
 350                 #address-cells = <1>;
 351                 #size-cells = <1>;
 352                 clocks = <&cru PCLK_EFUSE_256>;
 353                 clock-names = "pclk_efuse";
 354
 355                 /* Data cells */
 356                 efuse_id: id@7 {
 357                         reg = <0x7 0x10>;
 358                 };
 359                 cpu_leakage: cpu_leakage@17 {
 360                         reg = <0x17 0x1>;
 361                 };
 362         };
 363
 364         i2c0: i2c@11050000 {
 365                 compatible = "rockchip,rk3228-i2c";
 366                 reg = <0x11050000 0x1000>;
 367                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 368                 #address-cells = <1>;
 369                 #size-cells = <0>;
 370                 clock-names = "i2c";
 371                 clocks = <&cru PCLK_I2C0>;
 372                 pinctrl-names = "default";
 373                 pinctrl-0 = <&i2c0_xfer>;
 374                 status = "disabled";
 375         };
 376
 377         i2c1: i2c@11060000 {
 378                 compatible = "rockchip,rk3228-i2c";
 379                 reg = <0x11060000 0x1000>;
 380                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 381                 #address-cells = <1>;
 382                 #size-cells = <0>;
 383                 clock-names = "i2c";
 384                 clocks = <&cru PCLK_I2C1>;
 385                 pinctrl-names = "default";
 386                 pinctrl-0 = <&i2c1_xfer>;
 387                 status = "disabled";
 388         };
 389
 390         i2c2: i2c@11070000 {
 391                 compatible = "rockchip,rk3228-i2c";
 392                 reg = <0x11070000 0x1000>;
 393                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 394                 #address-cells = <1>;
 395                 #size-cells = <0>;
 396                 clock-names = "i2c";
 397                 clocks = <&cru PCLK_I2C2>;
 398                 pinctrl-names = "default";
 399                 pinctrl-0 = <&i2c2_xfer>;
 400                 status = "disabled";
 401         };
 402
 403         i2c3: i2c@11080000 {
 404                 compatible = "rockchip,rk3228-i2c";
 405                 reg = <0x11080000 0x1000>;
 406                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 407                 #address-cells = <1>;
 408                 #size-cells = <0>;
 409                 clock-names = "i2c";
 410                 clocks = <&cru PCLK_I2C3>;
 411                 pinctrl-names = "default";
 412                 pinctrl-0 = <&i2c3_xfer>;
 413                 status = "disabled";
 414         };
 415
 416         spi0: spi@11090000 {
 417                 compatible = "rockchip,rk3228-spi";
 418                 reg = <0x11090000 0x1000>;
 419                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
 420                 #address-cells = <1>;
 421                 #size-cells = <0>;
 422                 pinctrl-names = "default";
 423                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0 &spi0_cs1>;
 424                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 425                 clock-names = "spiclk", "apb_pclk";
 426                 status = "disabled";
 427         };
 428
 429         wdt: watchdog@110a0000 {
 430                 compatible = "rockchip,rk322x-wdt", "snps,dw-wdt";
 431                 reg = <0x110a0000 0x100>;
 432                 clocks = <&cru PCLK_CPU>;
 433                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 434                 status = "disabled";
 435         };
 436
 437         pwm0: pwm@110b0000 {
 438                 compatible = "rockchip,rk3288-pwm";
 439                 reg = <0x110b0000 0x10>;
 440                 #pwm-cells = <3>;
 441                 clocks = <&cru PCLK_PWM>;
 442                 clock-names = "pwm";
 443                 pinctrl-names = "default";
 444                 pinctrl-0 = <&pwm0_pin>;
 445                 status = "disabled";
 446         };
 447
 448         pwm1: pwm@110b0010 {
 449                 compatible = "rockchip,rk3288-pwm";
 450                 reg = <0x110b0010 0x10>;
 451                 #pwm-cells = <3>;
 452                 clocks = <&cru PCLK_PWM>;
 453                 clock-names = "pwm";
 454                 pinctrl-names = "default";
 455                 pinctrl-0 = <&pwm1_pin>;
 456                 status = "disabled";
 457         };
 458
 459         pwm2: pwm@110b0020 {
 460                 compatible = "rockchip,rk3288-pwm";
 461                 reg = <0x110b0020 0x10>;
 462                 #pwm-cells = <3>;
 463                 clocks = <&cru PCLK_PWM>;
 464                 clock-names = "pwm";
 465                 pinctrl-names = "default";
 466                 pinctrl-0 = <&pwm2_pin>;
 467                 status = "disabled";
 468         };
 469
 470         pwm3: pwm@110b0030 {
 471                 compatible = "rockchip,rk3288-pwm";
 472                 reg = <0x110b0030 0x10>;
 473                 #pwm-cells = <2>;
 474                 clocks = <&cru PCLK_PWM>;
 475                 clock-names = "pwm";
 476                 pinctrl-names = "default";
 477                 pinctrl-0 = <&pwm3_pin>;
 478                 status = "disabled";
 479         };
 480
 481         timer: timer@110c0000 {
 482                 compatible = "rockchip,rk3288-timer";
 483                 reg = <0x110c0000 0x20>;
 484                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 485                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 486                 clock-names = "timer", "pclk";
 487         };
 488
 489         cru: clock-controller@110e0000 {
 490                 compatible = "rockchip,rk3228-cru";
 491                 reg = <0x110e0000 0x1000>;
 492                 rockchip,grf = <&grf>;
 493                 #clock-cells = <1>;
 494                 #reset-cells = <1>;
 495                 assigned-clocks =
 496                         <&cru PLL_GPLL>, <&cru ARMCLK>,
 497                         <&cru PLL_CPLL>, <&cru ACLK_PERI>,
 498                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 499                         <&cru ACLK_CPU>, <&cru HCLK_CPU>,
 500                         <&cru PCLK_CPU>;
 501                 assigned-clock-rates =
 502                         <594000000>, <816000000>,
 503                         <500000000>, <150000000>,
 504                         <150000000>, <75000000>,
 505                         <150000000>, <150000000>,
 506                         <75000000>;
 507         };
 508
 509         thermal_zones: thermal-zones {
 510                 soc_thermal: soc-thermal {
 511                         polling-delay-passive = <100>; /* milliseconds */
 512                         polling-delay = <5000>; /* milliseconds */
 513                         sustainable-power = <1200>; /* milliwatts */
 514
 515                         thermal-sensors = <&tsadc 0>;
 516
 517                         trips {
 518                                 threshold: trip-point@0 {
 519                                         temperature = <70000>; /* millicelsius */
 520                                         hysteresis = <2000>; /* millicelsius */
 521                                         type = "passive";
 522                                 };
 523                                 target: trip-point@1 {
 524                                         temperature = <85000>; /* millicelsius */
 525                                         hysteresis = <2000>; /* millicelsius */
 526                                         type = "passive";
 527                                 };
 528                                 soc_crit: soc-crit {
 529                                         temperature = <90000>; /* millicelsius */
 530                                         hysteresis = <2000>; /* millicelsius */
 531                                         type = "critical";
 532                                 };
 533                         };
 534
 535                         cooling-maps {
 536                                 map0 {
 537                                         trip = <&target>;
 538                                         cooling-device =
 539                                         <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 540                                         contribution = <1024>;
 541                                 };
 542                                 map1 {
 543                                         trip = <&target>;
 544                                         cooling-device =
 545                                         <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 546                                         contribution = <1024>;
 547                                 };
 548                         };
 549                 };
 550         };
 551
 552         tsadc: tsadc@11150000 {
 553                 compatible = "rockchip,rk3228-tsadc";
 554                 reg = <0x11150000 0x100>;
 555                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 556                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 557                 clock-names = "tsadc", "apb_pclk";
 558                 assigned-clocks = <&cru SCLK_TSADC>;
 559                 assigned-clock-rates = <32768>;
 560                 resets = <&cru SRST_TSADC>;
 561                 reset-names = "tsadc-apb";
 562                 pinctrl-names = "init", "default", "sleep";
 563                 pinctrl-0 = <&otp_gpio>;
 564                 pinctrl-1 = <&otp_out>;
 565                 pinctrl-2 = <&otp_gpio>;
 566                 #thermal-sensor-cells = <0>;
 567                 rockchip,hw-tshut-temp = <95000>;
 568                 status = "disabled";
 569         };
 570
 571         hdmi_phy: hdmi-phy@12030000 {
 572                 compatible = "rockchip,rk3228-hdmi-phy";
 573                 reg = <0x12030000 0x10000>;
 574                 #phy-cells = <0>;
 575                 clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>;
 576                 clock-names = "sysclk", "refclk";
 577                 #clock-cells = <0>;
 578                 clock-output-names = "hdmiphy_phy";
 579                 status = "disabled";
 580         };
 581
 582         gpu: gpu@0x20001000 {
 583                 compatible = "arm,mali400";
 584                 reg = <0x20001000 0x200>,
 585                       <0x20000000 0x100>,
 586                       <0x20003000 0x100>,
 587                       <0x20008000 0x1100>,
 588                       <0x20004000 0x100>,
 589                       <0x2000A000 0x1100>,
 590                       <0x20005000 0x100>;
 591
 592                 reg-names = "Mali_L2",
 593                             "Mali_GP",
 594                             "Mali_GP_MMU",
 595                             "Mali_PP0",
 596                             "Mali_PP0_MMU",
 597                             "Mali_PP1",
 598                             "Mali_PP1_MMU";
 599
 600                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 601                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 602                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 603                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 604                              <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 605                              <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 606
 607                 interrupt-names = "Mali_GP_IRQ",
 608                                   "Mali_GP_MMU_IRQ",
 609                                   "Mali_PP0_IRQ",
 610                                   "Mali_PP0_MMU_IRQ",
 611                                   "Mali_PP1_IRQ",
 612                                   "Mali_PP1_MMU_IRQ";
 613                 clocks = <&cru ACLK_GPU>;
 614                 #cooling-cells = <2>; /* min followed by max */
 615                 clock-names = "clk_mali";
 616                 operating-points-v2 = <&gpu_opp_table>;
 617                 status = "disabled";
 618
 619                 gpu_power_model: power_model {
 620                         compatible = "arm,mali-simple-power-model";
 621                         voltage = <900>;
 622                         frequency = <500>;
 623                         static-power = <300>;
 624                         dynamic-power = <396>;
 625                         ts = <32000 4700 (-80) 2>;
 626                         thermal-zone = "soc-thermal";
 627                 };
 628         };
 629
 630         gpu_opp_table: opp-table2 {
 631                 compatible = "operating-points-v2";
 632
 633                 opp-200000000 {
 634                         opp-hz = /bits/ 64 <200000000>;
 635                         opp-microvolt = <1050000>;
 636                 };
 637                 opp-300000000 {
 638                         opp-hz = /bits/ 64 <300000000>;
 639                         opp-microvolt = <1050000>;
 640                 };
 641                 opp-500000000 {
 642                         opp-hz = /bits/ 64 <500000000>;
 643                         opp-microvolt = <1150000>;
 644                 };
 645         };
 646
 647         vop: vop@20050000 {
 648                 compatible = "rockchip,rk322x-vop";
 649                 reg = <0x20050000 0x1ffc>, <0x20052000 0x1000>;
 650                 reg-names = "regs", "gamma_lut";
 651                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 652                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
 653                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 654                 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
 655                 reset-names = "axi", "ahb", "dclk";
 656                 iommus = <&vop_mmu>;
 657                 status = "disabled";
 658
 659                 vop_out: port {
 660                         #address-cells = <1>;
 661                         #size-cells = <0>;
 662
 663                         vop_out_hdmi: endpoint@0 {
 664                                 reg = <0>;
 665                                 remote-endpoint = <&hdmi_in_vop>;
 666                         };
 667                 };
 668         };
 669
 670         vop_mmu: iommu@20050300 {
 671                 compatible = "rockchip,iommu";
 672                 reg = <0x20053f00 0x100>;
 673                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 674                 interrupt-names = "vop_mmu";
 675                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
 676                 clock-names = "aclk", "hclk";
 677                 #iommu-cells = <0>;
 678                 status = "disabled";
 679         };
 680
 681         display-subsystem {
 682                 compatible = "rockchip,display-subsystem";
 683                 ports = <&vop_out>;
 684         };
 685
 686         hdmi: hdmi@200a0000 {
 687                 compatible = "rockchip,rk3228-dw-hdmi";
 688                 reg = <0x200a0000 0x20000>;
 689                 reg-io-width = <4>;
 690                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
 691                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 692                 clocks = <&cru SCLK_HDMI_HDCP>, <&cru PCLK_HDMI_CTRL>;
 693                 clock-names = "isfr", "iahb";
 694                 pinctrl-names = "default";
 695                 pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd>;
 696                 resets = <&cru SRST_HDMI_P>;
 697                 reset-names = "hdmi";
 698                 phys = <&hdmi_phy>;
 699                 phy-names = "hdmi_phy";
 700                 rockchip,grf = <&grf>;
 701                 status = "disabled";
 702
 703                 port {
 704                         hdmi_in_vop: endpoint {
 705                                 remote-endpoint = <&vop_out_hdmi>;
 706                         };
 707                 };
 708         };
 709
 710         sdmmc: dwmmc@30000000 {
 711                 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
 712                 reg = <0x30000000 0x4000>;
 713                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 714                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 715                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 716                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 717                 fifo-depth = <0x100>;
 718                 pinctrl-names = "default";
 719                 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
 720                 status = "disabled";
 721         };
 722
 723         sdio: dwmmc@30010000 {
 724                 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
 725                 reg = <0x30010000 0x4000>;
 726                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 727                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 728                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 729                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 730                 fifo-depth = <0x100>;
 731                 pinctrl-names = "default";
 732                 pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
 733                 status = "disabled";
 734         };
 735
 736         emmc: dwmmc@30020000 {
 737                 compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
 738                 reg = <0x30020000 0x4000>;
 739                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 740                 clock-frequency = <37500000>;
 741                 clock-freq-min-max = <400000 37500000>;
 742                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 743                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 744                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 745                 bus-width = <8>;
 746                 default-sample-phase = <158>;
 747                 num-slots = <1>;
 748                 fifo-depth = <0x100>;
 749                 pinctrl-names = "default";
 750                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 751                 status = "disabled";
 752         };
 753
 754         nandc: nandc@30030000 {
 755                 compatible = "rockchip,rk-nandc";
 756                 reg = <0x30030000 0x4000>;
 757                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 758                 nandc_id = <0>;
 759                 clocks = <&cru SCLK_NANDC>, <&cru HCLK_NANDC>;
 760                 clock-names = "clk_nandc", "hclk_nandc";
 761                 status = "disabled";
 762         };
 763
 764         usb_otg: usb@30040000 {
 765                 compatible = "rockchip,rk322x-usb", "rockchip,rk3066-usb",
 766                              "snps,dwc2";
 767                 reg = <0x30040000 0x40000>;
 768                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 769                 clocks = <&cru HCLK_OTG>;
 770                 clock-names = "otg";
 771                 dr_mode = "otg";
 772                 g-np-tx-fifo-size = <16>;
 773                 g-rx-fifo-size = <275>;
 774                 g-tx-fifo-size = <256 128 128 64 64 32>;
 775                 g-use-dma;
 776                 phys = <&u2phy0_otg>;
 777                 phy-names = "usb2-phy";
 778                 status = "disabled";
 779         };
 780
 781         usb_host0_ehci: usb@30080000 {
 782                 compatible = "generic-ehci";
 783                 reg = <0x30080000 0x20000>;
 784                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 785                 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
 786                 clock-names = "usbhost", "utmi";
 787                 phys = <&u2phy0_host>;
 788                 phy-names = "usb";
 789                 status = "disabled";
 790         };
 791
 792         usb_host0_ohci: usb@300a0000 {
 793                 compatible = "generic-ohci";
 794                 reg = <0x300a0000 0x20000>;
 795                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 796                 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
 797                 clock-names = "usbhost", "utmi";
 798                 phys = <&u2phy0_host>;
 799                 phy-names = "usb";
 800                 status = "disabled";
 801         };
 802
 803         usb_host1_ehci: usb@300c0000 {
 804                 compatible = "generic-ehci";
 805                 reg = <0x300c0000 0x20000>;
 806                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 807                 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
 808                 clock-names = "usbhost", "utmi";
 809                 phys = <&u2phy1_host>;
 810                 phy-names = "usb";
 811                 status = "disabled";
 812         };
 813
 814         usb_host1_ohci: usb@300e0000 {
 815                 compatible = "generic-ohci";
 816                 reg = <0x300e0000 0x20000>;
 817                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 818                 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
 819                 clock-names = "usbhost", "utmi";
 820                 phys = <&u2phy1_host>;
 821                 phy-names = "usb";
 822                 status = "disabled";
 823         };
 824
 825         usb_host2_ehci: usb@30100000 {
 826                 compatible = "generic-ehci";
 827                 reg = <0x30100000 0x20000>;
 828                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 829                 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
 830                 phys = <&u2phy1_otg>;
 831                 phy-names = "usb";
 832                 clock-names = "usbhost", "utmi";
 833                 status = "disabled";
 834         };
 835
 836         usb_host2_ohci: usb@30120000 {
 837                 compatible = "generic-ohci";
 838                 reg = <0x30120000 0x20000>;
 839                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 840                 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
 841                 clock-names = "usbhost", "utmi";
 842                 phys = <&u2phy1_otg>;
 843                 phy-names = "usb";
 844                 status = "disabled";
 845         };
 846
 847         gmac: ethernet@30200000 {
 848                 compatible = "rockchip,rk3228-gmac";
 849                 reg = <0x30200000 0x10000>;
 850                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 851                 interrupt-names = "macirq";
 852                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 853                         <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
 854                         <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
 855                         <&cru PCLK_GMAC>;
 856                 clock-names = "stmmaceth", "mac_clk_rx",
 857                         "mac_clk_tx", "clk_mac_ref",
 858                         "clk_mac_refout", "aclk_mac",
 859                         "pclk_mac";
 860                 resets = <&cru SRST_GMAC>;
 861                 reset-names = "stmmaceth";
 862                 rockchip,grf = <&grf>;
 863                 status = "disabled";
 864         };
 865
 866         gic: interrupt-controller@32010000 {
 867                 compatible = "arm,gic-400";
 868                 interrupt-controller;
 869                 #interrupt-cells = <3>;
 870                 #address-cells = <0>;
 871
 872                 reg = <0x32011000 0x1000>,
 873                       <0x32012000 0x2000>,
 874                       <0x32014000 0x2000>,
 875                       <0x32016000 0x2000>;
 876                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 877         };
 878
 879         pinctrl: pinctrl {
 880                 compatible = "rockchip,rk3228-pinctrl";
 881                 rockchip,grf = <&grf>;
 882                 #address-cells = <1>;
 883                 #size-cells = <1>;
 884                 ranges;
 885
 886                 gpio0: gpio0@11110000 {
 887                         compatible = "rockchip,gpio-bank";
 888                         reg = <0x11110000 0x100>;
 889                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 890                         clocks = <&cru PCLK_GPIO0>;
 891
 892                         gpio-controller;
 893                         #gpio-cells = <2>;
 894
 895                         interrupt-controller;
 896                         #interrupt-cells = <2>;
 897                 };
 898
 899                 gpio1: gpio1@11120000 {
 900                         compatible = "rockchip,gpio-bank";
 901                         reg = <0x11120000 0x100>;
 902                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 903                         clocks = <&cru PCLK_GPIO1>;
 904
 905                         gpio-controller;
 906                         #gpio-cells = <2>;
 907
 908                         interrupt-controller;
 909                         #interrupt-cells = <2>;
 910                 };
 911
 912                 gpio2: gpio2@11130000 {
 913                         compatible = "rockchip,gpio-bank";
 914                         reg = <0x11130000 0x100>;
 915                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 916                         clocks = <&cru PCLK_GPIO2>;
 917
 918                         gpio-controller;
 919                         #gpio-cells = <2>;
 920
 921                         interrupt-controller;
 922                         #interrupt-cells = <2>;
 923                 };
 924
 925                 gpio3: gpio3@11140000 {
 926                         compatible = "rockchip,gpio-bank";
 927                         reg = <0x11140000 0x100>;
 928                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 929                         clocks = <&cru PCLK_GPIO3>;
 930
 931                         gpio-controller;
 932                         #gpio-cells = <2>;
 933
 934                         interrupt-controller;
 935                         #interrupt-cells = <2>;
 936                 };
 937
 938                 pcfg_pull_up: pcfg-pull-up {
 939                         bias-pull-up;
 940                 };
 941
 942                 pcfg_pull_down: pcfg-pull-down {
 943                         bias-pull-down;
 944                 };
 945
 946                 pcfg_pull_none: pcfg-pull-none {
 947                         bias-disable;
 948                 };
 949
 950                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
 951                         drive-strength = <12>;
 952                 };
 953
 954                 sdmmc {
 955                         sdmmc_clk: sdmmc-clk {
 956                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
 957                         };
 958
 959                         sdmmc_cmd: sdmmc-cmd {
 960                                 rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
 961                         };
 962
 963                         sdmmc_bus4: sdmmc-bus4 {
 964                                 rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 965                                                 <1 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 966                                                 <1 20 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 967                                                 <1 21 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
 968                         };
 969                 };
 970
 971                 sdio {
 972                         sdio_clk: sdio-clk {
 973                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
 974                         };
 975
 976                         sdio_cmd: sdio-cmd {
 977                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
 978                         };
 979
 980                         sdio_bus4: sdio-bus4 {
 981                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 982                                                 <3 3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 983                                                 <3 4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 984                                                 <3 5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
 985                         };
 986                 };
 987
 988                 emmc {
 989                         emmc_clk: emmc-clk {
 990                                 rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
 991                         };
 992
 993                         emmc_cmd: emmc-cmd {
 994                                 rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>;
 995                         };
 996
 997                         emmc_bus8: emmc-bus8 {
 998                                 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
 999                                                 <1 25 RK_FUNC_2 &pcfg_pull_none>,
1000                                                 <1 26 RK_FUNC_2 &pcfg_pull_none>,
1001                                                 <1 27 RK_FUNC_2 &pcfg_pull_none>,
1002                                                 <1 28 RK_FUNC_2 &pcfg_pull_none>,
1003                                                 <1 29 RK_FUNC_2 &pcfg_pull_none>,
1004                                                 <1 30 RK_FUNC_2 &pcfg_pull_none>,
1005                                                 <1 31 RK_FUNC_2 &pcfg_pull_none>;
1006                         };
1007                 };
1008
1009                 gmac {
1010                         rgmii_pins: rgmii-pins {
1011                                 rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
1012                                                 <2 12 RK_FUNC_1 &pcfg_pull_none>,
1013                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>,
1014                                                 <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1015                                                 <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1016                                                 <2 22 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1017                                                 <2 23 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1018                                                 <2 9 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1019                                                 <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1020                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1021                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1022                                                 <2 21 RK_FUNC_2 &pcfg_pull_none>,
1023                                                 <2 20 RK_FUNC_2 &pcfg_pull_none>,
1024                                                 <2 11 RK_FUNC_1 &pcfg_pull_none>,
1025                                                 <2 8 RK_FUNC_1 &pcfg_pull_none>;
1026                         };
1027
1028                         rmii_pins: rmii-pins {
1029                                 rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
1030                                                 <2 12 RK_FUNC_1 &pcfg_pull_none>,
1031                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>,
1032                                                 <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1033                                                 <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1034                                                 <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
1035                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
1036                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
1037                                                 <2 8 RK_FUNC_1 &pcfg_pull_none>,
1038                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>;
1039                         };
1040
1041                         phy_pins: phy-pins {
1042                                 rockchip,pins = <2 14 RK_FUNC_2 &pcfg_pull_none>,
1043                                                 <2 8 RK_FUNC_2 &pcfg_pull_none>;
1044                         };
1045                 };
1046
1047                 hdmi {
1048                         hdmi_hpd: hdmi-hpd {
1049                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_down>;
1050                         };
1051
1052                         hdmii2c_xfer: hdmii2c-xfer {
1053                                 rockchip,pins = <0 6 RK_FUNC_2 &pcfg_pull_none>,
1054                                                 <0 7 RK_FUNC_2 &pcfg_pull_none>;
1055                         };
1056                 };
1057
1058                 i2c0 {
1059                         i2c0_xfer: i2c0-xfer {
1060                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
1061                                                 <0 1 RK_FUNC_1 &pcfg_pull_none>;
1062                         };
1063                 };
1064
1065                 i2c1 {
1066                         i2c1_xfer: i2c1-xfer {
1067                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
1068                                                 <0 3 RK_FUNC_1 &pcfg_pull_none>;
1069                         };
1070                 };
1071
1072                 i2c2 {
1073                         i2c2_xfer: i2c2-xfer {
1074                                 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
1075                                                 <2 21 RK_FUNC_1 &pcfg_pull_none>;
1076                         };
1077                 };
1078
1079                 i2c3 {
1080                         i2c3_xfer: i2c3-xfer {
1081                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
1082                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
1083                         };
1084                 };
1085
1086                 spi-0 {
1087                         spi0_clk: spi0-clk {
1088                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_up>;
1089                         };
1090                         spi0_cs0: spi0-cs0 {
1091                                 rockchip,pins = <0 14 RK_FUNC_2 &pcfg_pull_up>;
1092                         };
1093                         spi0_tx: spi0-tx {
1094                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1095                         };
1096                         spi0_rx: spi0-rx {
1097                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1098                         };
1099                         spi0_cs1: spi0-cs1 {
1100                                 rockchip,pins = <1 12 RK_FUNC_1 &pcfg_pull_up>;
1101                         };
1102                 };
1103
1104                 spi-1 {
1105                         spi1_clk: spi1-clk {
1106                                 rockchip,pins = <0 23 RK_FUNC_2 &pcfg_pull_up>;
1107                         };
1108                         spi1_cs0: spi1-cs0 {
1109                                 rockchip,pins = <2 2 RK_FUNC_2 &pcfg_pull_up>;
1110                         };
1111                         spi1_rx: spi1-rx {
1112                                 rockchip,pins = <2 0 RK_FUNC_2 &pcfg_pull_up>;
1113                         };
1114                         spi1_tx: spi1-tx {
1115                                 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_up>;
1116                         };
1117                         spi1_cs1: spi1-cs1 {
1118                                 rockchip,pins = <2 3 RK_FUNC_2 &pcfg_pull_up>;
1119                         };
1120                 };
1121
1122                 i2s1 {
1123                         i2s1_bus: i2s1-bus {
1124                                 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>,
1125                                                 <0 9 RK_FUNC_1 &pcfg_pull_none>,
1126                                                 <0 11 RK_FUNC_1 &pcfg_pull_none>,
1127                                                 <0 12 RK_FUNC_1 &pcfg_pull_none>,
1128                                                 <0 13 RK_FUNC_1 &pcfg_pull_none>,
1129                                                 <0 14 RK_FUNC_1 &pcfg_pull_none>,
1130                                                 <1 2 RK_FUNC_2 &pcfg_pull_none>,
1131                                                 <1 4 RK_FUNC_2 &pcfg_pull_none>,
1132                                                 <1 5 RK_FUNC_2 &pcfg_pull_none>;
1133                         };
1134                 };
1135
1136                 pwm0 {
1137                         pwm0_pin: pwm0-pin {
1138                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>;
1139                         };
1140                 };
1141
1142                 pwm1 {
1143                         pwm1_pin: pwm1-pin {
1144                                 rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>;
1145                         };
1146                 };
1147
1148                 pwm2 {
1149                         pwm2_pin: pwm2-pin {
1150                                 rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>;
1151                         };
1152                 };
1153
1154                 pwm3 {
1155                         pwm3_pin: pwm3-pin {
1156                                 rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>;
1157                         };
1158                 };
1159
1160                 spdif {
1161                         spdif_tx: spdif-tx {
1162                                 rockchip,pins = <3 31 RK_FUNC_2 &pcfg_pull_none>;
1163                         };
1164                 };
1165
1166                 tsadc {
1167                         otp_gpio: otp-gpio {
1168                                 rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
1169                         };
1170
1171                         otp_out: otp-out {
1172                                 rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>;
1173                         };
1174                 };
1175
1176                 uart0 {
1177                         uart0_xfer: uart0-xfer {
1178                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>,
1179                                                 <2 27 RK_FUNC_1 &pcfg_pull_none>;
1180                         };
1181
1182                         uart0_cts: uart0-cts {
1183                                 rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>;
1184                         };
1185
1186                         uart0_rts: uart0-rts {
1187                                 rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>;
1188                         };
1189                 };
1190
1191                 uart1 {
1192                         uart1_xfer: uart1-xfer {
1193                                 rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>,
1194                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>;
1195                         };
1196
1197                         uart1_cts: uart1-cts {
1198                                 rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>;
1199                         };
1200
1201                         uart1_rts: uart1-rts {
1202                                 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;
1203                         };
1204                 };
1205
1206                 uart1-1 {
1207                         uart11_xfer: uart11-xfer {
1208                                 rockchip,pins = <3 14 RK_FUNC_1 &pcfg_pull_up>,
1209                                                 <3 13 RK_FUNC_1 &pcfg_pull_none>;
1210                         };
1211
1212                         uart11_cts: uart11-cts {
1213                                 rockchip,pins = <3 7 RK_FUNC_1 &pcfg_pull_none>;
1214                         };
1215
1216                         uart11_rts: uart11-rts {
1217                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_none>;
1218                         };
1219
1220                         uart11_rts_gpio: uart11-rts-gpio {
1221                                 rockchip,pins = <3 6 RK_FUNC_GPIO &pcfg_pull_none>;
1222                         };
1223                 };
1224
1225                 uart2 {
1226                         uart2_xfer: uart2-xfer {
1227                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
1228                                                 <1 19 RK_FUNC_2 &pcfg_pull_none>;
1229                         };
1230
1231                         uart2_cts: uart2-cts {
1232                                 rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>;
1233                         };
1234
1235                         uart2_rts: uart2-rts {
1236                                 rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>;
1237                         };
1238                 };
1239
1240                 uart2-1 {
1241                         uart21_xfer: uart21-xfer {
1242                                 rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>,
1243                                                 <1 9 RK_FUNC_2 &pcfg_pull_none>;
1244                         };
1245                 };
1246         };
1247
1248         rockchip_suspend: rockchip-suspend {
1249                 compatible = "rockchip,pm-rk322x";
1250                 status = "disabled";
1251                 rockchip,sleep-mode-config = <
1252                         (0
1253                         |RKPM_CTR_GTCLKS
1254                         |RKPM_CTR_IDLESRAM_MD
1255                         )
1256                 >;
1257         };
1258 };