arch/arm/boot/dts/rk322x.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3228-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include "skeleton.dtsi"
  48
  49 / {
  50         interrupt-parent = <&gic>;
  51
  52         aliases {
  53                 serial0 = &uart0;
  54                 serial1 = &uart1;
  55                 serial2 = &uart2;
  56         };
  57
  58         cpus {
  59                 #address-cells = <1>;
  60                 #size-cells = <0>;
  61
  62                 cpu0: cpu@f00 {
  63                         device_type = "cpu";
  64                         compatible = "arm,cortex-a7";
  65                         reg = <0xf00>;
  66                         resets = <&cru SRST_CORE0>;
  67                         operating-points = <
  68                                 /* KHz    uV */
  69                                  816000 1000000
  70                         >;
  71                         #cooling-cells = <2>; /* min followed by max */
  72                         clock-latency = <40000>;
  73                         clocks = <&cru ARMCLK>;
  74                 };
  75
  76                 cpu1: cpu@f01 {
  77                         device_type = "cpu";
  78                         compatible = "arm,cortex-a7";
  79                         reg = <0xf01>;
  80                         resets = <&cru SRST_CORE1>;
  81                 };
  82
  83                 cpu2: cpu@f02 {
  84                         device_type = "cpu";
  85                         compatible = "arm,cortex-a7";
  86                         reg = <0xf02>;
  87                         resets = <&cru SRST_CORE2>;
  88                 };
  89
  90                 cpu3: cpu@f03 {
  91                         device_type = "cpu";
  92                         compatible = "arm,cortex-a7";
  93                         reg = <0xf03>;
  94                         resets = <&cru SRST_CORE3>;
  95                 };
  96         };
  97
  98         amba {
  99                 compatible = "arm,amba-bus";
 100                 #address-cells = <1>;
 101                 #size-cells = <1>;
 102                 ranges;
 103
 104                 pdma: pdma@110f0000 {
 105                         compatible = "arm,pl330", "arm,primecell";
 106                         reg = <0x110f0000 0x4000>;
 107                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 108                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 109                         #dma-cells = <1>;
 110                         clocks = <&cru ACLK_DMAC>;
 111                         clock-names = "apb_pclk";
 112                 };
 113         };
 114
 115         arm-pmu {
 116                 compatible = "arm,cortex-a7-pmu";
 117                 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 118                              <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
 119                              <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
 120                              <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 121                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 122         };
 123
 124         timer {
 125                 compatible = "arm,armv7-timer";
 126                 arm,cpu-registers-not-fw-configured;
 127                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 128                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 129                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 130                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 131                 clock-frequency = <24000000>;
 132         };
 133
 134         xin24m: oscillator {
 135                 compatible = "fixed-clock";
 136                 clock-frequency = <24000000>;
 137                 clock-output-names = "xin24m";
 138                 #clock-cells = <0>;
 139         };
 140
 141         i2s1: i2s1@100b0000 {
 142                 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
 143                 reg = <0x100b0000 0x4000>;
 144                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 145                 #address-cells = <1>;
 146                 #size-cells = <0>;
 147                 clock-names = "i2s_clk", "i2s_hclk";
 148                 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
 149                 dmas = <&pdma 14>, <&pdma 15>;
 150                 dma-names = "tx", "rx";
 151                 pinctrl-names = "default";
 152                 pinctrl-0 = <&i2s1_bus>;
 153                 status = "disabled";
 154         };
 155
 156         i2s0: i2s0@100c0000 {
 157                 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
 158                 reg = <0x100c0000 0x4000>;
 159                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 160                 #address-cells = <1>;
 161                 #size-cells = <0>;
 162                 clock-names = "i2s_clk", "i2s_hclk";
 163                 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
 164                 dmas = <&pdma 11>, <&pdma 12>;
 165                 dma-names = "tx", "rx";
 166                 status = "disabled";
 167         };
 168
 169         i2s2: i2s2@100e0000 {
 170                 compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
 171                 reg = <0x100e0000 0x4000>;
 172                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 173                 #address-cells = <1>;
 174                 #size-cells = <0>;
 175                 clock-names = "i2s_clk", "i2s_hclk";
 176                 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
 177                 dmas = <&pdma 0>, <&pdma 1>;
 178                 dma-names = "tx", "rx";
 179                 status = "disabled";
 180         };
 181
 182         grf: syscon@11000000 {
 183                 compatible = "syscon", "simple-mfd";
 184                 reg = <0x11000000 0x1000>;
 185                 #address-cells = <1>;
 186                 #size-cells = <1>;
 187
 188                 u2phy0: usb2-phy@760 {
 189                         compatible = "rockchip,rk322x-usb2phy";
 190                         reg = <0x0760 0x0c>;
 191                         clocks = <&cru SCLK_OTGPHY0>;
 192                         clock-names = "phyclk";
 193                         #clock-cells = <0>;
 194                         clock-output-names = "usb480m_phy0";
 195                         status = "disabled";
 196
 197                         u2phy0_otg: otg-port {
 198                                 #phy-cells = <0>;
 199                                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 200                                              <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 201                                              <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 202                                 interrupt-names = "otg-bvalid", "otg-id",
 203                                                   "linestate";
 204                                 status = "disabled";
 205                         };
 206
 207                         u2phy0_host: host-port {
 208                                 #phy-cells = <0>;
 209                                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 210                                 interrupt-names = "linestate";
 211                                 status = "disabled";
 212                         };
 213                 };
 214
 215                 u2phy1: usb2-phy@800 {
 216                         compatible = "rockchip,rk322x-usb2phy";
 217                         reg = <0x0800 0x0c>;
 218                         clocks = <&cru SCLK_OTGPHY1>;
 219                         clock-names = "phyclk";
 220                         #clock-cells = <0>;
 221                         clock-output-names = "usb480m_phy1";
 222                         status = "disabled";
 223
 224                         u2phy1_host: host-port {
 225                                 #phy-cells = <0>;
 226                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 227                                 interrupt-names = "linestate";
 228                                 status = "disabled";
 229                         };
 230                 };
 231         };
 232
 233         uart0: serial@11010000 {
 234                 compatible = "snps,dw-apb-uart";
 235                 reg = <0x11010000 0x100>;
 236                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 237                 clock-frequency = <24000000>;
 238                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 239                 clock-names = "baudclk", "apb_pclk";
 240                 pinctrl-names = "default";
 241                 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
 242                 reg-shift = <2>;
 243                 reg-io-width = <4>;
 244                 status = "disabled";
 245         };
 246
 247         uart1: serial@11020000 {
 248                 compatible = "snps,dw-apb-uart";
 249                 reg = <0x11020000 0x100>;
 250                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 251                 clock-frequency = <24000000>;
 252                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 253                 clock-names = "baudclk", "apb_pclk";
 254                 pinctrl-names = "default";
 255                 pinctrl-0 = <&uart1_xfer>;
 256                 reg-shift = <2>;
 257                 reg-io-width = <4>;
 258                 status = "disabled";
 259         };
 260
 261         uart2: serial@11030000 {
 262                 compatible = "snps,dw-apb-uart";
 263                 reg = <0x11030000 0x100>;
 264                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 265                 clock-frequency = <24000000>;
 266                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 267                 clock-names = "baudclk", "apb_pclk";
 268                 pinctrl-names = "default";
 269                 pinctrl-0 = <&uart21_xfer>;
 270                 reg-shift = <2>;
 271                 reg-io-width = <4>;
 272                 status = "disabled";
 273         };
 274
 275         i2c0: i2c@11050000 {
 276                 compatible = "rockchip,rk3228-i2c";
 277                 reg = <0x11050000 0x1000>;
 278                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 279                 #address-cells = <1>;
 280                 #size-cells = <0>;
 281                 clock-names = "i2c";
 282                 clocks = <&cru PCLK_I2C0>;
 283                 pinctrl-names = "default";
 284                 pinctrl-0 = <&i2c0_xfer>;
 285                 status = "disabled";
 286         };
 287
 288         i2c1: i2c@11060000 {
 289                 compatible = "rockchip,rk3228-i2c";
 290                 reg = <0x11060000 0x1000>;
 291                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 292                 #address-cells = <1>;
 293                 #size-cells = <0>;
 294                 clock-names = "i2c";
 295                 clocks = <&cru PCLK_I2C1>;
 296                 pinctrl-names = "default";
 297                 pinctrl-0 = <&i2c1_xfer>;
 298                 status = "disabled";
 299         };
 300
 301         i2c2: i2c@11070000 {
 302                 compatible = "rockchip,rk3228-i2c";
 303                 reg = <0x11070000 0x1000>;
 304                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 305                 #address-cells = <1>;
 306                 #size-cells = <0>;
 307                 clock-names = "i2c";
 308                 clocks = <&cru PCLK_I2C2>;
 309                 pinctrl-names = "default";
 310                 pinctrl-0 = <&i2c2_xfer>;
 311                 status = "disabled";
 312         };
 313
 314         i2c3: i2c@11080000 {
 315                 compatible = "rockchip,rk3228-i2c";
 316                 reg = <0x11080000 0x1000>;
 317                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 318                 #address-cells = <1>;
 319                 #size-cells = <0>;
 320                 clock-names = "i2c";
 321                 clocks = <&cru PCLK_I2C3>;
 322                 pinctrl-names = "default";
 323                 pinctrl-0 = <&i2c3_xfer>;
 324                 status = "disabled";
 325         };
 326
 327         wdt: watchdog@110a0000 {
 328                 compatible = "rockchip,rk322x-wdt", "snps,dw-wdt";
 329                 reg = <0x110a0000 0x100>;
 330                 clocks = <&cru PCLK_CPU>;
 331                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 332                 status = "disabled";
 333         };
 334
 335         pwm0: pwm@110b0000 {
 336                 compatible = "rockchip,rk3288-pwm";
 337                 reg = <0x110b0000 0x10>;
 338                 #pwm-cells = <3>;
 339                 clocks = <&cru PCLK_PWM>;
 340                 clock-names = "pwm";
 341                 pinctrl-names = "default";
 342                 pinctrl-0 = <&pwm0_pin>;
 343                 status = "disabled";
 344         };
 345
 346         pwm1: pwm@110b0010 {
 347                 compatible = "rockchip,rk3288-pwm";
 348                 reg = <0x110b0010 0x10>;
 349                 #pwm-cells = <3>;
 350                 clocks = <&cru PCLK_PWM>;
 351                 clock-names = "pwm";
 352                 pinctrl-names = "default";
 353                 pinctrl-0 = <&pwm1_pin>;
 354                 status = "disabled";
 355         };
 356
 357         pwm2: pwm@110b0020 {
 358                 compatible = "rockchip,rk3288-pwm";
 359                 reg = <0x110b0020 0x10>;
 360                 #pwm-cells = <3>;
 361                 clocks = <&cru PCLK_PWM>;
 362                 clock-names = "pwm";
 363                 pinctrl-names = "default";
 364                 pinctrl-0 = <&pwm2_pin>;
 365                 status = "disabled";
 366         };
 367
 368         pwm3: pwm@110b0030 {
 369                 compatible = "rockchip,rk3288-pwm";
 370                 reg = <0x110b0030 0x10>;
 371                 #pwm-cells = <2>;
 372                 clocks = <&cru PCLK_PWM>;
 373                 clock-names = "pwm";
 374                 pinctrl-names = "default";
 375                 pinctrl-0 = <&pwm3_pin>;
 376                 status = "disabled";
 377         };
 378
 379         timer: timer@110c0000 {
 380                 compatible = "rockchip,rk3288-timer";
 381                 reg = <0x110c0000 0x20>;
 382                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 383                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 384                 clock-names = "timer", "pclk";
 385         };
 386
 387         cru: clock-controller@110e0000 {
 388                 compatible = "rockchip,rk3228-cru";
 389                 reg = <0x110e0000 0x1000>;
 390                 rockchip,grf = <&grf>;
 391                 #clock-cells = <1>;
 392                 #reset-cells = <1>;
 393                 assigned-clocks =
 394                         <&cru PLL_GPLL>, <&cru ARMCLK>,
 395                         <&cru PLL_CPLL>, <&cru ACLK_PERI>,
 396                         <&cru HCLK_PERI>, <&cru PCLK_PERI>,
 397                         <&cru ACLK_CPU>, <&cru HCLK_CPU>,
 398                         <&cru PCLK_CPU>;
 399                 assigned-clock-rates =
 400                         <594000000>, <816000000>,
 401                         <500000000>, <150000000>,
 402                         <150000000>, <75000000>,
 403                         <150000000>, <150000000>,
 404                         <75000000>;
 405         };
 406
 407         thermal-zones {
 408                 cpu_thermal: cpu-thermal {
 409                         polling-delay-passive = <100>; /* milliseconds */
 410                         polling-delay = <5000>; /* milliseconds */
 411
 412                         thermal-sensors = <&tsadc 0>;
 413
 414                         trips {
 415                                 cpu_alert0: cpu_alert0 {
 416                                         temperature = <70000>; /* millicelsius */
 417                                         hysteresis = <2000>; /* millicelsius */
 418                                         type = "passive";
 419                                 };
 420                                 cpu_alert1: cpu_alert1 {
 421                                         temperature = <75000>; /* millicelsius */
 422                                         hysteresis = <2000>; /* millicelsius */
 423                                         type = "passive";
 424                                 };
 425                                 cpu_crit: cpu_crit {
 426                                         temperature = <90000>; /* millicelsius */
 427                                         hysteresis = <2000>; /* millicelsius */
 428                                         type = "critical";
 429                                 };
 430                         };
 431
 432                         cooling-maps {
 433                                 map0 {
 434                                         trip = <&cpu_alert0>;
 435                                         cooling-device =
 436                                                 <&cpu0 THERMAL_NO_LIMIT 6>;
 437                                 };
 438                                 map1 {
 439                                         trip = <&cpu_alert1>;
 440                                         cooling-device =
 441                                                 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 442                                 };
 443                         };
 444                 };
 445         };
 446
 447         tsadc: tsadc@11150000 {
 448                 compatible = "rockchip,rk3228-tsadc";
 449                 reg = <0x11150000 0x100>;
 450                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 451                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 452                 clock-names = "tsadc", "apb_pclk";
 453                 resets = <&cru SRST_TSADC>;
 454                 reset-names = "tsadc-apb";
 455                 pinctrl-names = "init", "default", "sleep";
 456                 pinctrl-0 = <&otp_gpio>;
 457                 pinctrl-1 = <&otp_out>;
 458                 pinctrl-2 = <&otp_gpio>;
 459                 #thermal-sensor-cells = <0>;
 460                 rockchip,hw-tshut-temp = <95000>;
 461                 status = "disabled";
 462         };
 463
 464         vop: vop@20050000 {
 465                 compatible = "rockchip,rk322x-vop";
 466                 reg = <0x20050000 0x1ffc>, <0x20052000 0x1000>;
 467                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 468                 clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
 469                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 470                 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
 471                 reset-names = "axi", "ahb", "dclk";
 472                 iommus = <&vop_mmu>;
 473                 status = "disabled";
 474
 475                 vop_out: port {
 476                         #address-cells = <1>;
 477                         #size-cells = <0>;
 478                 };
 479         };
 480
 481         vop_mmu: iommu@20050300 {
 482                 compatible = "rockchip,iommu";
 483                 reg = <0x20053f00 0x100>;
 484                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 485                 interrupt-names = "vop_mmu";
 486                 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
 487                 clock-names = "aclk", "hclk";
 488                 #iommu-cells = <0>;
 489                 status = "disabled";
 490         };
 491
 492         display-subsystem {
 493                 compatible = "rockchip,display-subsystem";
 494                 ports = <&vop_out>;
 495         };
 496
 497         emmc: dwmmc@30020000 {
 498                 compatible = "rockchip,rk3288-dw-mshc";
 499                 reg = <0x30020000 0x4000>;
 500                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 501                 clock-frequency = <37500000>;
 502                 clock-freq-min-max = <400000 37500000>;
 503                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 504                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 505                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 506                 bus-width = <8>;
 507                 default-sample-phase = <158>;
 508                 num-slots = <1>;
 509                 fifo-depth = <0x100>;
 510                 pinctrl-names = "default";
 511                 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
 512                 status = "disabled";
 513         };
 514
 515         usb_otg: usb@30040000 {
 516                 compatible = "rockchip,rk322x-usb", "rockchip,rk3066-usb",
 517                              "snps,dwc2";
 518                 reg = <0x30040000 0x40000>;
 519                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 520                 clocks = <&cru HCLK_OTG>;
 521                 clock-names = "otg";
 522                 dr_mode = "otg";
 523                 g-np-tx-fifo-size = <16>;
 524                 g-rx-fifo-size = <275>;
 525                 g-tx-fifo-size = <256 128 128 64 64 32>;
 526                 g-use-dma;
 527                 phys = <&u2phy0_otg>;
 528                 phy-names = "usb2-phy";
 529                 status = "disabled";
 530         };
 531
 532         usb_host0_ehci: usb@30080000 {
 533                 compatible = "generic-ehci";
 534                 reg = <0x30080000 0x20000>;
 535                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 536                 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
 537                 clock-names = "usbhost", "utmi";
 538                 phys = <&u2phy0_host>;
 539                 phy-names = "usb";
 540                 status = "disabled";
 541         };
 542
 543         usb_host0_ohci: usb@300a0000 {
 544                 compatible = "generic-ohci";
 545                 reg = <0x300a0000 0x20000>;
 546                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 547                 clocks = <&cru HCLK_HOST0>, <&u2phy0>;
 548                 clock-names = "usbhost", "utmi";
 549                 phys = <&u2phy0_host>;
 550                 phy-names = "usb";
 551                 status = "disabled";
 552         };
 553
 554         usb_host1_ehci: usb@300c0000 {
 555                 compatible = "generic-ehci";
 556                 reg = <0x300c0000 0x20000>;
 557                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 558                 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
 559                 clock-names = "usbhost", "utmi";
 560                 phys = <&u2phy1_host>;
 561                 phy-names = "usb";
 562                 status = "disabled";
 563         };
 564
 565         usb_host1_ohci: usb@300e0000 {
 566                 compatible = "generic-ohci";
 567                 reg = <0x300e0000 0x20000>;
 568                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 569                 clocks = <&cru HCLK_HOST1>, <&u2phy1>;
 570                 clock-names = "usbhost", "utmi";
 571                 phys = <&u2phy1_host>;
 572                 phy-names = "usb";
 573                 status = "disabled";
 574         };
 575
 576         usb_host2_ehci: usb@30100000 {
 577                 compatible = "generic-ehci";
 578                 reg = <0x30100000 0x20000>;
 579                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 580                 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
 581                 clock-names = "usbhost", "utmi";
 582                 status = "disabled";
 583         };
 584
 585         usb_host2_ohci: usb@30120000 {
 586                 compatible = "generic-ohci";
 587                 reg = <0x30120000 0x20000>;
 588                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 589                 clocks = <&cru HCLK_HOST2>, <&u2phy1>;
 590                 clock-names = "usbhost", "utmi";
 591                 status = "disabled";
 592         };
 593
 594         gmac: ethernet@30200000 {
 595                 compatible = "rockchip,rk3228-gmac";
 596                 reg = <0x30200000 0x10000>;
 597                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 598                 interrupt-names = "macirq";
 599                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 600                         <&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
 601                         <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
 602                         <&cru PCLK_GMAC>;
 603                 clock-names = "stmmaceth", "mac_clk_rx",
 604                         "mac_clk_tx", "clk_mac_ref",
 605                         "clk_mac_refout", "aclk_mac",
 606                         "pclk_mac";
 607                 resets = <&cru SRST_GMAC>;
 608                 reset-names = "stmmaceth";
 609                 rockchip,grf = <&grf>;
 610                 status = "disabled";
 611         };
 612
 613         gic: interrupt-controller@32010000 {
 614                 compatible = "arm,gic-400";
 615                 interrupt-controller;
 616                 #interrupt-cells = <3>;
 617                 #address-cells = <0>;
 618
 619                 reg = <0x32011000 0x1000>,
 620                       <0x32012000 0x2000>,
 621                       <0x32014000 0x2000>,
 622                       <0x32016000 0x2000>;
 623                 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 624         };
 625
 626         pinctrl: pinctrl {
 627                 compatible = "rockchip,rk3228-pinctrl";
 628                 rockchip,grf = <&grf>;
 629                 #address-cells = <1>;
 630                 #size-cells = <1>;
 631                 ranges;
 632
 633                 gpio0: gpio0@11110000 {
 634                         compatible = "rockchip,gpio-bank";
 635                         reg = <0x11110000 0x100>;
 636                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
 637                         clocks = <&cru PCLK_GPIO0>;
 638
 639                         gpio-controller;
 640                         #gpio-cells = <2>;
 641
 642                         interrupt-controller;
 643                         #interrupt-cells = <2>;
 644                 };
 645
 646                 gpio1: gpio1@11120000 {
 647                         compatible = "rockchip,gpio-bank";
 648                         reg = <0x11120000 0x100>;
 649                         interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
 650                         clocks = <&cru PCLK_GPIO1>;
 651
 652                         gpio-controller;
 653                         #gpio-cells = <2>;
 654
 655                         interrupt-controller;
 656                         #interrupt-cells = <2>;
 657                 };
 658
 659                 gpio2: gpio2@11130000 {
 660                         compatible = "rockchip,gpio-bank";
 661                         reg = <0x11130000 0x100>;
 662                         interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 663                         clocks = <&cru PCLK_GPIO2>;
 664
 665                         gpio-controller;
 666                         #gpio-cells = <2>;
 667
 668                         interrupt-controller;
 669                         #interrupt-cells = <2>;
 670                 };
 671
 672                 gpio3: gpio3@11140000 {
 673                         compatible = "rockchip,gpio-bank";
 674                         reg = <0x11140000 0x100>;
 675                         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 676                         clocks = <&cru PCLK_GPIO3>;
 677
 678                         gpio-controller;
 679                         #gpio-cells = <2>;
 680
 681                         interrupt-controller;
 682                         #interrupt-cells = <2>;
 683                 };
 684
 685                 pcfg_pull_up: pcfg-pull-up {
 686                         bias-pull-up;
 687                 };
 688
 689                 pcfg_pull_down: pcfg-pull-down {
 690                         bias-pull-down;
 691                 };
 692
 693                 pcfg_pull_none: pcfg-pull-none {
 694                         bias-disable;
 695                 };
 696
 697                 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
 698                         drive-strength = <12>;
 699                 };
 700
 701                 emmc {
 702                         emmc_clk: emmc-clk {
 703                                 rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
 704                         };
 705
 706                         emmc_cmd: emmc-cmd {
 707                                 rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>;
 708                         };
 709
 710                         emmc_bus8: emmc-bus8 {
 711                                 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
 712                                                 <1 25 RK_FUNC_2 &pcfg_pull_none>,
 713                                                 <1 26 RK_FUNC_2 &pcfg_pull_none>,
 714                                                 <1 27 RK_FUNC_2 &pcfg_pull_none>,
 715                                                 <1 28 RK_FUNC_2 &pcfg_pull_none>,
 716                                                 <1 29 RK_FUNC_2 &pcfg_pull_none>,
 717                                                 <1 30 RK_FUNC_2 &pcfg_pull_none>,
 718                                                 <1 31 RK_FUNC_2 &pcfg_pull_none>;
 719                         };
 720                 };
 721
 722                 gmac {
 723                         rgmii_pins: rgmii-pins {
 724                                 rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
 725                                                 <2 12 RK_FUNC_1 &pcfg_pull_none>,
 726                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>,
 727                                                 <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 728                                                 <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 729                                                 <2 22 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 730                                                 <2 23 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 731                                                 <2 9 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 732                                                 <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 733                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
 734                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
 735                                                 <2 21 RK_FUNC_2 &pcfg_pull_none>,
 736                                                 <2 20 RK_FUNC_2 &pcfg_pull_none>,
 737                                                 <2 11 RK_FUNC_1 &pcfg_pull_none>,
 738                                                 <2 8 RK_FUNC_1 &pcfg_pull_none>;
 739                         };
 740
 741                         rmii_pins: rmii-pins {
 742                                 rockchip,pins = <2 14 RK_FUNC_1 &pcfg_pull_none>,
 743                                                 <2 12 RK_FUNC_1 &pcfg_pull_none>,
 744                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>,
 745                                                 <2 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 746                                                 <2 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 747                                                 <2 13 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
 748                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
 749                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
 750                                                 <2 8 RK_FUNC_1 &pcfg_pull_none>,
 751                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>;
 752                         };
 753
 754                         phy_pins: phy-pins {
 755                                 rockchip,pins = <2 14 RK_FUNC_2 &pcfg_pull_none>,
 756                                                 <2 8 RK_FUNC_2 &pcfg_pull_none>;
 757                         };
 758                 };
 759
 760                 i2c0 {
 761                         i2c0_xfer: i2c0-xfer {
 762                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>,
 763                                                 <0 1 RK_FUNC_1 &pcfg_pull_none>;
 764                         };
 765                 };
 766
 767                 i2c1 {
 768                         i2c1_xfer: i2c1-xfer {
 769                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
 770                                                 <0 3 RK_FUNC_1 &pcfg_pull_none>;
 771                         };
 772                 };
 773
 774                 i2c2 {
 775                         i2c2_xfer: i2c2-xfer {
 776                                 rockchip,pins = <2 20 RK_FUNC_1 &pcfg_pull_none>,
 777                                                 <2 21 RK_FUNC_1 &pcfg_pull_none>;
 778                         };
 779                 };
 780
 781                 i2c3 {
 782                         i2c3_xfer: i2c3-xfer {
 783                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
 784                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
 785                         };
 786                 };
 787
 788                 i2s1 {
 789                         i2s1_bus: i2s1-bus {
 790                                 rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_none>,
 791                                                 <0 9 RK_FUNC_1 &pcfg_pull_none>,
 792                                                 <0 11 RK_FUNC_1 &pcfg_pull_none>,
 793                                                 <0 12 RK_FUNC_1 &pcfg_pull_none>,
 794                                                 <0 13 RK_FUNC_1 &pcfg_pull_none>,
 795                                                 <0 14 RK_FUNC_1 &pcfg_pull_none>,
 796                                                 <1 2 RK_FUNC_1 &pcfg_pull_none>,
 797                                                 <1 4 RK_FUNC_1 &pcfg_pull_none>,
 798                                                 <1 5 RK_FUNC_1 &pcfg_pull_none>;
 799                         };
 800                 };
 801
 802                 pwm0 {
 803                         pwm0_pin: pwm0-pin {
 804                                 rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>;
 805                         };
 806                 };
 807
 808                 pwm1 {
 809                         pwm1_pin: pwm1-pin {
 810                                 rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>;
 811                         };
 812                 };
 813
 814                 pwm2 {
 815                         pwm2_pin: pwm2-pin {
 816                                 rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>;
 817                         };
 818                 };
 819
 820                 pwm3 {
 821                         pwm3_pin: pwm3-pin {
 822                                 rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>;
 823                         };
 824                 };
 825
 826                 tsadc {
 827                         otp_gpio: otp-gpio {
 828                                 rockchip,pins = <0 24 RK_FUNC_GPIO &pcfg_pull_none>;
 829                         };
 830
 831                         otp_out: otp-out {
 832                                 rockchip,pins = <0 24 RK_FUNC_2 &pcfg_pull_none>;
 833                         };
 834                 };
 835
 836                 uart0 {
 837                         uart0_xfer: uart0-xfer {
 838                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>,
 839                                                 <2 27 RK_FUNC_1 &pcfg_pull_none>;
 840                         };
 841
 842                         uart0_cts: uart0-cts {
 843                                 rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>;
 844                         };
 845
 846                         uart0_rts: uart0-rts {
 847                                 rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>;
 848                         };
 849                 };
 850
 851                 uart1 {
 852                         uart1_xfer: uart1-xfer {
 853                                 rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>,
 854                                                 <1 10 RK_FUNC_1 &pcfg_pull_none>;
 855                         };
 856
 857                         uart1_cts: uart1-cts {
 858                                 rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>;
 859                         };
 860
 861                         uart1_rts: uart1-rts {
 862                                 rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;
 863                         };
 864                 };
 865
 866                 uart2 {
 867                         uart2_xfer: uart2-xfer {
 868                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
 869                                                 <1 19 RK_FUNC_2 &pcfg_pull_none>;
 870                         };
 871
 872                         uart2_cts: uart2-cts {
 873                                 rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>;
 874                         };
 875
 876                         uart2_rts: uart2-rts {
 877                                 rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>;
 878                         };
 879                 };
 880
 881                 uart2-1 {
 882                         uart21_xfer: uart21-xfer {
 883                                 rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>,
 884                                                 <1 9 RK_FUNC_2 &pcfg_pull_none>;
 885                         };
 886                 };
 887         };
 888 };