2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
42 #include <dt-bindings/pwm/pwm.h>
43 #include <dt-bindings/input/input.h>
44 #include <dt-bindings/soc/rockchip-system-status.h>
45 #include "rk3288-dram-default-timing.dtsi"
49 bootargs = "earlycon=uart8250,mmio32,0xff690000";
52 /delete-node/ dmc@ff610000;
55 compatible = "rockchip,rk3288-dfi";
56 rockchip,pmu = <&pmu>;
57 rockchip,grf = <&grf>;
62 compatible = "rockchip,rk3288-dmc";
63 devfreq-events = <&dfi>;
64 clocks = <&cru SCLK_DDRCLK>, <&cru PCLK_PUBL0>,
65 <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL1>,
66 <&cru PCLK_DDRUPCTL1>;
67 clock-names = "dmc_clk", "pclk_phy0", "pclk_upctl0",
68 "pclk_phy1", "pclk_upctl1";
70 downdifferential = <10>;
71 operating-points-v2 = <&dmc_opp_table>;
73 min-cpu-freq = <600000>;
74 rockchip,ddr_timing = <&ddr_timing>;
75 system-status-freq = <
76 /*system status freq(KHz)*/
77 SYS_STATUS_NORMAL 396000
78 SYS_STATUS_REBOOT 396000
79 SYS_STATUS_SUSPEND 192000
80 SYS_STATUS_VIDEO_1080P 300000
81 SYS_STATUS_VIDEO_4K 396000
82 SYS_STATUS_PERFORMANCE 528000
83 SYS_STATUS_BOOST 396000
84 SYS_STATUS_DUALVIEW 396000
87 auto-min-freq = <400000>;
92 dmc_opp_table: opp_table2 {
93 compatible = "operating-points-v2";
96 opp-hz = /bits/ 64 <192000000>;
97 opp-microvolt = <1100000>;
100 opp-hz = /bits/ 64 <300000000>;
101 opp-microvolt = <1100000>;
104 opp-hz = /bits/ 64 <396000000>;
105 opp-microvolt = <1100000>;
108 opp-hz = /bits/ 64 <528000000>;
109 opp-microvolt = <1150000>;
114 ramoops_mem: ramoops@00000000 {
115 reg = <0x0 0x8000000 0x0 0xF0000>;
118 drm_logo: drm-logo@00000000 {
119 compatible = "rockchip,drm-logo";
120 reg = <0x0 0x0 0x0 0x0>;
125 compatible = "ramoops";
126 record-size = <0x0 0x20000>;
127 console-size = <0x0 0x80000>;
128 ftrace-size = <0x0 0x00000>;
129 pmsg-size = <0x0 0x50000>;
130 memory-region = <&ramoops_mem>;
134 compatible = "rockchip,fiq-debugger";
135 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>;
136 rockchip,serial-id = <2>;
137 rockchip,wake-irq = <0>;
138 rockchip,irq-mode-enable = <0>; /* If enable uart uses irq instead of fiq */
139 rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */
140 pinctrl-names = "default";
141 pinctrl-0 = <&uart2_xfer>;
145 compatible = "arm,psci-1.0";
149 /delete-node/ timer@ff810000;
151 backlight: backlight {
152 compatible = "pwm-backlight";
153 brightness-levels = <
155 8 9 10 11 12 13 14 15
156 16 17 18 19 20 21 22 23
157 24 25 26 27 28 29 30 31
158 32 33 34 35 36 37 38 39
159 40 41 42 43 44 45 46 47
160 48 49 50 51 52 53 54 55
161 56 57 58 59 60 61 62 63
162 64 65 66 67 68 69 70 71
163 72 73 74 75 76 77 78 79
164 80 81 82 83 84 85 86 87
165 88 89 90 91 92 93 94 95
166 96 97 98 99 100 101 102 103
167 104 105 106 107 108 109 110 111
168 112 113 114 115 116 117 118 119
169 120 121 122 123 124 125 126 127
170 128 129 130 131 132 133 134 135
171 136 137 138 139 140 141 142 143
172 144 145 146 147 148 149 150 151
173 152 153 154 155 156 157 158 159
174 160 161 162 163 164 165 166 167
175 168 169 170 171 172 173 174 175
176 176 177 178 179 180 181 182 183
177 184 185 186 187 188 189 190 191
178 192 193 194 195 196 197 198 199
179 200 201 202 203 204 205 206 207
180 208 209 210 211 212 213 214 215
181 216 217 218 219 220 221 222 223
182 224 225 226 227 228 229 230 231
183 232 233 234 235 236 237 238 239
184 240 241 242 243 244 245 246 247
185 248 249 250 251 252 253 254 255>;
186 default-brightness-level = <128>;
187 enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
188 pinctrl-names = "default";
189 pinctrl-0 = <&bl_en>;
190 pwms = <&pwm0 0 1000000 0>;
196 ports = <&vopb_out>, <&vopl_out>;
197 memory-region = <&drm_logo>;
200 route_edp: route-edp {
202 logo,uboot = "logo.bmp";
203 logo,kernel = "logo_kernel.bmp";
204 logo,mode = "center";
205 charge_logo,mode = "center";
206 connect = <&vopb_out_edp>;
209 route_mipi: route-mipi {
211 logo,uboot = "logo.bmp";
212 logo,kernel = "logo_kernel.bmp";
213 logo,mode = "center";
214 charge_logo,mode = "center";
215 connect = <&vopb_out_mipi>;
220 rk_key: rockchip-key {
221 compatible = "rockchip,key";
224 io-channels = <&saradc 1>;
229 rockchip,adc_value = <1>;
234 label = "volume down";
235 rockchip,adc_value = <170>;
239 gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
241 pinctrl-names = "default";
242 pinctrl-0 = <&pwrbtn>;
250 rockchip,adc_value = <355>;
256 rockchip,adc_value = <746>;
262 rockchip,adc_value = <560>;
268 rockchip,adc_value = <450>;
272 dwc_control_usb: dwc-control-usb@ff770284 {
273 compatible = "rockchip,rk3288-dwc-control-usb";
275 reg = <0x0 0xff770284 0x0 0x04>, <0x0 0xff770288 0x0 0x04>,
276 <0x0 0xff7702cc 0x0 0x04>, <0x0 0xff7702d4 0x0 0x04>,
277 <0x0 0xff770320 0x0 0x14>, <0x0 0xff770334 0x0 0x14>,
278 <0x0 0xff770348 0x0 0x10>, <0x0 0xff770358 0x0 0x08>,
279 <0x0 0xff770360 0x0 0x08>;
280 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
281 "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
282 "GRF_UOC0_BASE", "GRF_UOC1_BASE",
283 "GRF_UOC2_BASE", "GRF_UOC3_BASE",
285 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
290 interrupt-names = "otg_id", "otg_bvalid",
291 "otg_linestate", "host0_linestate",
293 clocks = <&cru HCLK_USB_PERI>;
294 clock-names = "hclk_usb_peri";
296 otg_drv_gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
297 rockchip,remote_wakeup;
298 rockchip,usb_irq_wakeup;
301 compatible = "synopsys,phy";
302 rk_usb,bvalid = <0x288 14 1>;
303 rk_usb,iddig = <0x288 17 1>;
304 rk_usb,dcdenb = <0x328 14 1>;
305 rk_usb,vdatsrcenb = <0x328 7 1>;
306 rk_usb,vdatdetenb = <0x328 6 1>;
307 rk_usb,chrgsel = <0x328 5 1>;
308 rk_usb,chgdet = <0x2cc 23 1>;
309 rk_usb,fsvminus = <0x2cc 25 1>;
310 rk_usb,fsvplus = <0x2cc 24 1>;
314 nandc0: nandc@ff400000 {
315 compatible = "rockchip,rk-nandc";
316 reg = <0x0 0xff400000 0x0 0x4000>;
317 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
319 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
320 clock-names = "clk_nandc", "hclk_nandc";
324 hdmi_analog_sound: hdmi-analog-sound {
326 compatible = "rockchip,rk3288-hdmi-analog",
327 "rockchip,rk3368-hdmi-analog";
328 rockchip,model = "rockchip,rt5640-codec";
329 rockchip,cpu = <&i2s>;
330 rockchip,codec = <&rt5640>, <&hdmi>;
332 "Microphone", "Microphone Jack",
333 "Headphone", "Headphone Jack";
335 "MIC1", "Microphone Jack",
336 "MIC2", "Microphone Jack",
337 "Microphone Jack", "micbias1",
338 "Headphone Jack", "HPOL",
339 "Headphone Jack", "HPOR";
344 backlight = <&backlight>;
348 enable-method = "psci";
352 clocks = <&cru PLL_APLL>;
353 leakage-scaling-sel = <0 254 25>;
356 opp-hz = /bits/ 64 <1800000000>;
357 opp-microvolt = <1350000>;
358 clock-latency-ns = <40000>;
364 enable-method = "psci";
368 enable-method = "psci";
372 enable-method = "psci";
376 /* change to non-secure dmac */
377 reg = <0x0 0xff600000 0x0 0x4000>;
381 compatible = "rockchip,rk3288-secure-efuse";
395 mipi_in_vopl: endpoint@1 {
403 compatible = "rockchip,rga2";
404 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
405 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
409 compatible = "rockchip,rk3288_usb20_otg";
410 clocks = <&usbphy0>, <&cru HCLK_OTG0>;
411 clock-names = "clk_usbphy0", "hclk_usb0";
412 resets = <&cru SRST_USBOTG_AHB>,
413 <&cru SRST_USBOTG_PHY>,
414 <&cru SRST_USBOTG_CON>;
415 reset-names = "otg_ahb", "otg_phy", "otg_controller";
416 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
417 rockchip,usb-mode = <0>;
424 rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
430 rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;