2 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
42 #include <dt-bindings/pwm/pwm.h>
43 #include <dt-bindings/input/input.h>
47 bootargs = "earlycon=uart8250,mmio32,0xff690000";
51 ramoops_mem: ramoops@00000000 {
52 reg = <0x0 0x8000000 0x0 0xF0000>;
55 drm_logo: drm-logo@00000000 {
56 compatible = "rockchip,drm-logo";
57 reg = <0x0 0x0 0x0 0x0>;
62 compatible = "ramoops";
63 record-size = <0x0 0x20000>;
64 console-size = <0x0 0x80000>;
65 ftrace-size = <0x0 0x00000>;
66 pmsg-size = <0x0 0x50000>;
67 memory-region = <&ramoops_mem>;
71 compatible = "rockchip,fiq-debugger";
72 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>;
73 rockchip,serial-id = <2>;
74 rockchip,wake-irq = <0>;
75 rockchip,irq-mode-enable = <0>; /* If enable uart uses irq instead of fiq */
76 rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */
77 pinctrl-names = "default";
78 pinctrl-0 = <&uart2_xfer>;
82 compatible = "arm,psci-1.0";
86 /delete-node/ timer@ff810000;
88 backlight: backlight {
89 compatible = "pwm-backlight";
93 16 17 18 19 20 21 22 23
94 24 25 26 27 28 29 30 31
95 32 33 34 35 36 37 38 39
96 40 41 42 43 44 45 46 47
97 48 49 50 51 52 53 54 55
98 56 57 58 59 60 61 62 63
99 64 65 66 67 68 69 70 71
100 72 73 74 75 76 77 78 79
101 80 81 82 83 84 85 86 87
102 88 89 90 91 92 93 94 95
103 96 97 98 99 100 101 102 103
104 104 105 106 107 108 109 110 111
105 112 113 114 115 116 117 118 119
106 120 121 122 123 124 125 126 127
107 128 129 130 131 132 133 134 135
108 136 137 138 139 140 141 142 143
109 144 145 146 147 148 149 150 151
110 152 153 154 155 156 157 158 159
111 160 161 162 163 164 165 166 167
112 168 169 170 171 172 173 174 175
113 176 177 178 179 180 181 182 183
114 184 185 186 187 188 189 190 191
115 192 193 194 195 196 197 198 199
116 200 201 202 203 204 205 206 207
117 208 209 210 211 212 213 214 215
118 216 217 218 219 220 221 222 223
119 224 225 226 227 228 229 230 231
120 232 233 234 235 236 237 238 239
121 240 241 242 243 244 245 246 247
122 248 249 250 251 252 253 254 255>;
123 default-brightness-level = <128>;
124 enable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
125 pinctrl-names = "default";
126 pinctrl-0 = <&bl_en>;
127 pwms = <&pwm0 0 1000000 0>;
133 ports = <&vopb_out>, <&vopl_out>;
134 memory-region = <&drm_logo>;
137 route_edp: route-edp {
139 logo,uboot = "logo.bmp";
140 logo,kernel = "logo_kernel.bmp";
141 logo,mode = "center";
142 charge_logo,mode = "center";
143 connect = <&vopb_out_edp>;
146 route_mipi: route-mipi {
148 logo,uboot = "logo.bmp";
149 logo,kernel = "logo_kernel.bmp";
150 logo,mode = "center";
151 charge_logo,mode = "center";
152 connect = <&vopb_out_mipi>;
157 rk_key: rockchip-key {
158 compatible = "rockchip,key";
161 io-channels = <&saradc 1>;
166 rockchip,adc_value = <1>;
171 label = "volume down";
172 rockchip,adc_value = <170>;
176 gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
178 pinctrl-names = "default";
179 pinctrl-0 = <&pwrbtn>;
187 rockchip,adc_value = <355>;
193 rockchip,adc_value = <746>;
199 rockchip,adc_value = <560>;
205 rockchip,adc_value = <450>;
209 dwc_control_usb: dwc-control-usb@ff770284 {
210 compatible = "rockchip,rk3288-dwc-control-usb";
212 reg = <0x0 0xff770284 0x0 0x04>, <0x0 0xff770288 0x0 0x04>,
213 <0x0 0xff7702cc 0x0 0x04>, <0x0 0xff7702d4 0x0 0x04>,
214 <0x0 0xff770320 0x0 0x14>, <0x0 0xff770334 0x0 0x14>,
215 <0x0 0xff770348 0x0 0x10>, <0x0 0xff770358 0x0 0x08>,
216 <0x0 0xff770360 0x0 0x08>;
217 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
218 "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
219 "GRF_UOC0_BASE", "GRF_UOC1_BASE",
220 "GRF_UOC2_BASE", "GRF_UOC3_BASE",
222 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
227 interrupt-names = "otg_id", "otg_bvalid",
228 "otg_linestate", "host0_linestate",
230 clocks = <&cru HCLK_USB_PERI>;
231 clock-names = "hclk_usb_peri";
233 otg_drv_gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>;
234 rockchip,remote_wakeup;
235 rockchip,usb_irq_wakeup;
238 compatible = "synopsys,phy";
239 rk_usb,bvalid = <0x288 14 1>;
240 rk_usb,iddig = <0x288 17 1>;
241 rk_usb,dcdenb = <0x328 14 1>;
242 rk_usb,vdatsrcenb = <0x328 7 1>;
243 rk_usb,vdatdetenb = <0x328 6 1>;
244 rk_usb,chrgsel = <0x328 5 1>;
245 rk_usb,chgdet = <0x2cc 23 1>;
246 rk_usb,fsvminus = <0x2cc 25 1>;
247 rk_usb,fsvplus = <0x2cc 24 1>;
251 nandc0: nandc@ff400000 {
252 compatible = "rockchip,rk-nandc";
253 reg = <0x0 0xff400000 0x0 0x4000>;
254 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
256 clocks = <&cru SCLK_NANDC0>, <&cru HCLK_NANDC0>;
257 clock-names = "clk_nandc", "hclk_nandc";
263 backlight = <&backlight>;
267 enable-method = "psci";
271 enable-method = "psci";
275 enable-method = "psci";
279 enable-method = "psci";
283 /* change to non-secure dmac */
284 reg = <0x0 0xff600000 0x0 0x4000>;
288 compatible = "rockchip,rk3288-secure-efuse";
300 compatible = "rockchip,rga2";
301 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
302 clock-names = "aclk_rga", "hclk_rga", "clk_rga";
306 compatible = "rockchip,rk3288_usb20_otg";
307 clocks = <&usbphy0>, <&cru HCLK_OTG0>;
308 clock-names = "clk_usbphy0", "hclk_usb0";
309 resets = <&cru SRST_USBOTG_AHB>,
310 <&cru SRST_USBOTG_PHY>,
311 <&cru SRST_USBOTG_CON>;
312 reset-names = "otg_ahb", "otg_phy", "otg_controller";
313 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
314 rockchip,usb-mode = <0>;
321 rockchip,pins = <7 2 RK_FUNC_GPIO &pcfg_pull_none>;
327 rockchip,pins = <0 5 RK_FUNC_GPIO &pcfg_pull_up>;