arch/arm/boot/dts/rk3288.dtsi

   1 #include <dt-bindings/clock/ddr.h>
   2 #include <dt-bindings/interrupt-controller/arm-gic.h>
   3 #include <dt-bindings/rkfb/rk_fb.h>
   4 #include <dt-bindings/suspend/rockchip-pm.h>
   5 #include <dt-bindings/sensor-dev.h>
   6
   7 #include "skeleton.dtsi"
   8 #include "rk3288-pinctrl.dtsi"
   9 #include "rk3288-clocks.dtsi"
  10
  11 / {
  12         compatible = "rockchip,rk3288";
  13         interrupt-parent = <&gic>;
  14
  15         aliases {
  16                 serial2 = &uart_dbg;
  17                 i2c0 = &i2c0;
  18                 i2c1 = &i2c1;
  19                 i2c2 = &i2c2;
  20                 i2c3 = &i2c3;
  21                 i2c4 = &i2c4;
  22                 i2c5 = &i2c5;
  23                 lcdc0 = &lcdc0;
  24                 lcdc1 = &lcdc1;
  25         };
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 cpu@0 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a15";
  34                         reg = <0x500>;
  35                 };
  36                 cpu@1 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a15";
  39                         reg = <0x501>;
  40                 };
  41                 cpu@2 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x502>;
  45                 };
  46                 cpu@3 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a15";
  49                         reg = <0x503>;
  50                 };
  51         };
  52
  53         gic: interrupt-controller@ffc01000 {
  54                 compatible = "arm,cortex-a15-gic";
  55                 interrupt-controller;
  56                 #interrupt-cells = <3>;
  57                 #address-cells = <0>;
  58                 reg = <0xffc01000 0x1000>,
  59                       <0xffc02000 0x1000>;
  60         };
  61
  62         cpu_axi_bus: cpu_axi_bus {
  63                 compatible = "rockchip,cpu_axi_bus";
  64                 #address-cells = <1>;
  65                 #size-cells = <1>;
  66                 ranges;
  67                 qos {
  68                         #address-cells = <1>;
  69                         #size-cells = <1>;
  70                         ranges;
  71                         /* service core */
  72                         cpup {
  73                                 reg = <0xffa80000 0x20>;
  74                         };
  75                         cpum_r {
  76                                 reg = <0xffa80080 0x20>;
  77                         };
  78                         cpum_w {
  79                                 reg = <0xffa80100 0x20>;
  80                         };
  81                         /* service dmac */
  82                         bus_dmac {
  83                                 reg = <0xffa90000 0x20>;
  84                         };
  85                         host {
  86                                 reg = <0xffa90080 0x20>;
  87                         };
  88                         crypto {
  89                                 reg = <0xffa90100 0x20>;
  90                         };
  91                         ccp {
  92                                 reg = <0xffa90180 0x20>;
  93                         };
  94                         ccs {
  95                                 reg = <0xffa90200 0x20>;
  96                         };
  97                         /* service gpu */
  98                         gpu_r {
  99                                 reg = <0xffaa0000 0x20>;
 100                         };
 101                         gpu_w {
 102                                 reg = <0xffaa0080 0x20>;
 103                         };
 104                         /* service peri */
 105                         peri {
 106                                 reg = <0xffab0000 0x20>;
 107                         };
 108                         /* service vio */
 109                         vio1_vop {
 110                                 reg = <0xffad0000 0x20>;
 111                         };
 112                         vio1_isp_w0 {
 113                                 reg = <0xffad0100 0x20>;
 114                         };
 115                         vio1_isp_w1 {
 116                                 reg = <0xffad0180 0x20>;
 117                         };
 118                         vio0_vop {
 119                                 reg = <0xffad0400 0x20>;
 120                         };
 121                         vio0_vip {
 122                                 reg = <0xffad0480 0x20>;
 123                         };
 124                         vio0_iep {
 125                                 reg = <0xffad0500 0x20>;
 126                         };
 127                         vio2_rga_r {
 128                                 reg = <0xffad0800 0x20>;
 129                         };
 130                         vio2_rga_w {
 131                                 reg = <0xffad0880 0x20>;
 132                         };
 133                         vio1_isp_r {
 134                                 reg = <0xffad0900 0x20>;
 135                         };
 136                         /* service video */
 137                         video {
 138                                 reg = <0xffae0000 0x20>;
 139                         };
 140                         /* service hevc */
 141                         hevc_r {
 142                                 reg = <0xffaf0000 0x20>;
 143                         };
 144                         hevc_w {
 145                                 reg = <0xffaf0080 0x20>;
 146                         };
 147                 };
 148                 msch {
 149                         #address-cells = <1>;
 150                         #size-cells = <1>;
 151                         ranges;
 152                         msch@0 {
 153                                 reg = <0xffac0000 0x40>;
 154                                 rockchip,read-latency = <0xff>;
 155                         };
 156                         msch@1 {
 157                                 reg = <0xffac0080 0x40>;
 158                                 rockchip,read-latency = <0xff>;
 159                         };
 160                 };
 161         };
 162
 163         sram: sram@ff710000 {
 164                 compatible = "mmio-sram";
 165                 reg = <0xff710000 0x8000>; /* 32k */
 166                 map-exec;
 167         };
 168
 169         timer {
 170                 compatible = "arm,armv7-timer";
 171                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 172                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 173                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 174                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 175                 clock-frequency = <24000000>;
 176         };
 177
 178         timer@ff810000 {
 179                 compatible = "rockchip,timer";
 180                 reg = <0xff810000 0x20>;
 181                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 182                 rockchip,broadcast = <1>;
 183         };
 184
 185         timer@ff810020 {
 186                 compatible = "rockchip,timer";
 187                 reg = <0xff810020 0x20>;
 188                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 189                 rockchip,clocksource = <1>;
 190                 rockchip,count-up = <1>;
 191         };
 192
 193
 194         emmc: rksdmmc@ff0f0000 {
 195                 compatible = "rockchip,rk_mmc";
 196                 reg = <0xff0f0000 0x4000>;
 197                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;/*irq=67*/
 198                 #address-cells = <1>;
 199                 #size-cells = <0>;
 200                 //pinctrl-names = "default",,"suspend";
 201                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 202
 203                 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_3 --clk_emmc_src_gate_en*/
 204                 //clocks = <&clk_gates8 0>, <&clk_gates8 0>;
 205                 num-slots = <1>;
 206                 fifo-depth = <0x80>;
 207                 bus-width = <4>;
 208         };
 209
 210         sdmmc: rksdmmc@ff0c0000 {
 211                 compatible = "rockchip,rk_mmc";
 212                 reg = <0xff0c0000 0x4000>;
 213                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; /*irq=64*/
 214                 #address-cells = <1>;
 215                 #size-cells = <0>;
 216
 217                 //pinctrl-names = "default","suspend";
 218                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 219                 //pinctrl-1 = <&sd0_cd_gpio>; //for int gpio?
 220
 221                 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_0 --clk_mmc0_src_gate_en*/
 222                 //clocks = <&clk_gates8 0>, <&clk_gates13 0>;
 223                 num-slots = <1>;
 224                 fifo-depth = <0x100>;
 225                 bus-width = <4>;
 226
 227         };
 228
 229         sdio: rksdmmc@ff0d0000 {
 230                 compatible = "rockchip,rk_mmc";
 231                 reg = <0xff0d0000 0x4000>;
 232                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 233                 #address-cells = <1>;
 234                 #size-cells = <0>;
 235                 //pinctrl-names = "default","suspend";
 236                 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 237
 238                 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_1 --clk_sdio0_src_gate_en*/
 239                 //clocks = <&clk_gates8 0>, <&clk_gates13 1>;
 240                 num-slots = <1>;
 241
 242                 fifo-depth = <0x100>;
 243                 bus-width = <4>;
 244         };
 245
 246         sdio1: rksdmmc@ff0e0000 {
 247                 compatible = "rockchip,rk_mmc";
 248                 reg = <0xff0e0000 0x4000>;
 249                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 250                 #address-cells = <1>;
 251                 #size-cells = <0>;
 252                 //pinctrl-names = "default","suspend";
 253                 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 254
 255                 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_2 --clk_sdio1_src_gate_en*/
 256                 //clocks = <&clk_gates8 0>, <&clk_gates13 2>;
 257                 num-slots = <1>;
 258
 259                 fifo-depth = <0x100>;
 260                 bus-width = <4>;
 261         };
 262
 263
 264         uart_dbg: serial@ff690000 {
 265                 compatible = "rockchip,serial";
 266                 reg = <0xff690000 0x100>;
 267                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 268                 clock-frequency = <24000000>;
 269                 reg-shift = <2>;
 270                 reg-io-width = <4>;
 271                 status = "disabled";
 272         };
 273
 274         fiq-debugger {
 275                 compatible = "rockchip,fiq-debugger";
 276                 rockchip,serial-id = <2>;
 277                 rockchip,signal-irq = <106>;
 278                 rockchip,wake-irq = <0>;
 279                 status = "disabled";
 280         };
 281
 282         clocks-init{
 283                 compatible = "rockchip,clocks-init";
 284                 rockchip,clocks-init-parent =
 285                         <&clk_core &clk_apll>,  <&aclk_bus_src &clk_gpll>,
 286                         <&aclk_peri &clk_gpll>, <&uart_pll_mux &clk_gpll>,
 287                         <&clk_i2s_pll &clk_cpll>;
 288                 rockchip,clocks-init-rate =
 289                         <&clk_core 792000000>,  <&clk_gpll 594000000>,
 290                         <&clk_cpll 384000000>,  <&clk_npll 500000000>,
 291                         <&aclk_bus_src 300000000>,      <&aclk_bus 300000000>,
 292                         <&hclk_bus 150000000>,  <&pclk_bus 75000000>,
 293                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 294                         <&hclk_peri 150000000>, <&pclk_peri 75000000>,
 295                         <&clk_gpu 200000000>,   <&aclk_vio0 300000000>,
 296                         <&aclk_vio1 300000000>, <&hclk_vio 75000000>,
 297                         <&pclk_pd_alive 100000000>,     <&pclk_pd_pmu 100000000>;
 298         };
 299
 300         i2c0: i2c@ff650000 {
 301                 compatible = "rockchip,rk30-i2c";
 302                 reg = <0xff650000 0x1000>;
 303                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 304                 #address-cells = <1>;
 305                 #size-cells = <0>;
 306                 //pinctrl-names = "default", "gpio";
 307                 //pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 308                 //pinctrl-1 = <&i2c0_gpio>;
 309                 //gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
 310                 //clocks = <&clk_gates8 4>;
 311                 rockchip,check-idle = <1>;
 312                 status = "disabled";
 313         };
 314
 315         i2c1: i2c@ff140000 {
 316                 compatible = "rockchip,rk30-i2c";
 317                 reg = <0xff140000 0x1000>;
 318                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 319                 #address-cells = <1>;
 320                 #size-cells = <0>;
 321                 //pinctrl-names = "default", "gpio";
 322                 //pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 323                 //pinctrl-1 = <&i2c1_gpio>;
 324                 //gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
 325                 //clocks = <&clk_gates8 5>;
 326                 rockchip,check-idle = <1>;
 327                 status = "disabled";
 328         };
 329
 330         i2c2: i2c@ff660000 {
 331                 compatible = "rockchip,rk30-i2c";
 332                 reg = <0xff660000 0x1000>;
 333                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 334                 #address-cells = <1>;
 335                 #size-cells = <0>;
 336                 //pinctrl-names = "default", "gpio";
 337                 //pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 338                 //pinctrl-1 = <&i2c2_gpio>;
 339                 //gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
 340                 //clocks = <&clk_gates8 6>;
 341                 rockchip,check-idle = <1>;
 342                 status = "disabled";
 343         };
 344
 345         i2c3: i2c@ff150000 {
 346                 compatible = "rockchip,rk30-i2c";
 347                 reg = <0xff150000 0x1000>;
 348                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 349                 #address-cells = <1>;
 350                 #size-cells = <0>;
 351                 //pinctrl-names = "default", "gpio";
 352                 //pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 353                 //pinctrl-1 = <&i2c3_gpio>;
 354                 //gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
 355                 //clocks = <&clk_gates8 7>;
 356                 rockchip,check-idle = <1>;
 357                 status = "disabled";
 358         };
 359
 360         i2c4: i2c@ff160000 {
 361                 compatible = "rockchip,rk30-i2c";
 362                 reg = <0xff160000 0x1000>;
 363                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 364                 #address-cells = <1>;
 365                 #size-cells = <0>;
 366                 //pinctrl-names = "default", "gpio";
 367                 //pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 368                 //pinctrl-1 = <&i2c4_gpio>;
 369                 //gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
 370                 //clocks = <&clk_gates8 8>;
 371                 rockchip,check-idle = <1>;
 372                 status = "disabled";
 373         };
 374
 375         i2c5: i2c@ff170000 {
 376                 compatible = "rockchip,rk30-i2c";
 377                 reg = <0xff170000 0x1000>;
 378                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 379                 #address-cells = <1>;
 380                 #size-cells = <0>;
 381                 //pinctrl-names = "default", "gpio";
 382                 //pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 383                 //pinctrl-1 = <&i2c5_gpio>;
 384                 //gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
 385                 //clocks = <&clk_gates8 8>;
 386                 rockchip,check-idle = <1>;
 387                 status = "disabled";
 388         };
 389
 390
 391         fb: fb{
 392                 compatible = "rockchip,rk-fb";
 393                 rockchip,disp-mode = <DUAL>;
 394         };
 395
 396         rk_screen: rk_screen{
 397                         compatible = "rockchip,screen";
 398         };
 399
 400         lvds: lvds@ff96c000 {
 401                 compatible = "rockchip, rk32-lvds";
 402                 reg = <0xff960000 0x20000>;
 403         };
 404
 405         edp: edp@ff970000 {
 406                 compatible = "rockchip,rk32-edp";
 407                 reg = <0xff970000 0x4000>;
 408                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 409         };
 410
 411         hdmi: hdmi@ff980000 {
 412                 compatible = "rockchip,rk3288-hdmi";
 413                 reg = <0xff980000 0x20000>;
 414                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 415                 pinctrl-names = "default", "gpio";
 416                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 417                 pinctrl-1 = <&i2c5_gpio>;
 418                 clocks = <&clk_gates16 9>;
 419                 clock-names = "pclk_hdmi";
 420                 status = "disabled";
 421         };
 422
 423         lcdc1: lcdc@ff940000 {
 424                 compatible = "rockchip,rk3288-lcdc";
 425                 rockchip,prop = <PRMRY>;
 426                 rochchip,pwr18 = <0>;
 427                 reg = <0xff940000 0x10000>;
 428                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 429                 pinctrl-names = "default", "gpio";
 430                 pinctrl-0 = <&lcdc0_lcdc>;
 431                 pinctrl-1 = <&lcdc0_gpio>;
 432                 status = "disabled";
 433         };
 434
 435         lcdc0: lcdc@ff930000 {
 436                 compatible = "rockchip,rk3288-lcdc";
 437                 rockchip,prop = <EXTEND>;
 438                 rockchip,pwr18 = <0>;
 439                 reg = <0xff930000 0x10000>;
 440                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 441                 //pinctrl-names = "default", "gpio";
 442                 //pinctrl-0 = <&lcdc0_lcdc>;
 443                 //pinctrl-1 = <&lcdc0_gpio>;
 444                 status = "disabled";
 445         };
 446
 447         adc: adc@ff100000 {
 448                 compatible = "rockchip,saradc";
 449                 reg = <0xff100000 0x100>;
 450                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 451                 #io-channel-cells = <1>;
 452                 io-channel-ranges;
 453                 rockchip,adc-vref = <1800>;
 454                 clock-frequency = <1000000>;
 455                 clock-names = "saradc", "pclk_saradc";
 456                 status = "disabled";
 457         };
 458
 459         rga@ff920000 {
 460                 compatible = "rockchip,rga";
 461                 reg = <0xff920000 0x1000>;
 462                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 463                 clock-names = "hclk_rga", "aclk_rga";
 464         };
 465
 466         i2s: rockchip-i2s@0xff890000 {
 467                 compatible = "rockchip-i2s";
 468                 reg = <0xff890000 0x10000>;
 469                 i2s-id = <0>;
 470         //      clocks = <&clk_i2s>;
 471         //      clock-names = "i2s_clk","i2s_mclk";
 472                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 473         //      dmas = <&pdma0 0>,
 474         //              <&pdma0 1>;
 475                 //#dma-cells = <2>;
 476         //      dma-names = "tx", "rx";
 477         //      pinctrl-names = "default", "sleep";
 478         //      pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo0 &i2s0_sdo1 &i2s0_sdo2 &i2s0_sdo3>;
 479         //      pinctrl-1 = <&i2s0_gpio>;
 480         };
 481
 482         spdif: rockchip-spdif@0xff8b0000 {
 483                 compatible = "rockchip-spdif";
 484                 reg = <0xff8b0000 0x10000>;     //8channel
 485                 //reg = <ff880000 0x2000>;//2channel
 486         //      clocks = <&clk_spdif>;
 487         //      clock-names = "spdif_mclk";
 488                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 489         //      dmas = <&pdma0 8>;
 490                 //#dma-cells = <1>;
 491         //      dma-names = "tx";
 492         //      pinctrl-names = "default";
 493         //      pinctrl-0 = <&spdif_tx>;
 494         };
 495
 496         pwm0: pwm@ff680000 {
 497                 reg = <0xff680000 0x10>;
 498                 status = "disabled";
 499         };
 500
 501         pwm1: pwm@ff680010 {
 502                 reg = <0xff680010 0x10>;
 503                 status = "disabled";
 504         };
 505
 506         pwm2: pwm@ff680020 {
 507                 reg = <0xff680020 0x10>;
 508                 status = "disabled";
 509         };
 510
 511         pwm3: pwm@ff680030 {
 512                 reg = <0xff680030 0x10>;
 513                 status = "disabled";
 514         };
 515
 516         ion {
 517                 compatible = "rockchip,ion";
 518                 #address-cells = <1>;
 519                 #size-cells = <0>;
 520                 rockchip,ion-heap@1 { /* CMA HEAP */
 521                         compatible = "rockchip,ion-reserve";
 522                         reg = <1>;
 523                         memory-reservation = <0x00000000 0x10000000>; /* 256MB */
 524                 };
 525                 rockchip,ion-heap@3 { /* SYSTEM HEAP */
 526                         reg = <3>;
 527                 };
 528         };
 529
 530
 531         vpu: vpu_service@ff9a0000 {
 532                 compatible = "vpu_service";
 533                 reg = <0xff9a0000 0x800>;
 534                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 535                 interrupt-names = "irq_enc", "irq_dec";
 536                 /*clocks = <&clk_gates3 9>, <&clk_gates3 10>;
 537                 clock-names = "aclk_vcodec", "hclk_vcodec"; */
 538                 name = "vpu_service";
 539                 status = "disabled";
 540         };
 541
 542         hevc: hevc_service@ff9c0000 {
 543                 compatible = "rockchip,hevc_service";
 544                 reg = <0xff9c0000 0x800>;
 545                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 546                 interrupt-names = "irq_dec";
 547                 /*clocks = <&clk_gates3 9>, <&clk_gates3 10>;
 548                 clock-names = "aclk_vcodec", "hclk_vcodec";*/
 549                 name = "hevc_service";
 550                 status = "disabled";
 551         };
 552
 553         iep: iep@ff900000 {
 554                 compatible = "rockchip,iep";
 555                 reg = <0xff900000 0x800>;
 556                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 557                 /*clocks = <&clk_gate3 9>, <&clk_gate3 10>;
 558                 clock_names = "aclk_iep", "hclk_iep";*/
 559                 status = "disabled";
 560         };
 561
 562         dwc_control_usb: dwc-control-usb@ff770284 {
 563                 compatible = "rockchip,rk3288-dwc-control-usb";
 564                 reg = <0xff770284 0x04>, <0xff770288 0x04>,
 565                       <0xff7702cc 0x04>, <0xff7702d4 0x04>,
 566                       <0xff770320 0x14>, <0xff770334 0x14>,
 567                       <0xff770348 0x10>, <0xff770358 0x08>,
 568                       <0xff770360 0x08>;
 569                 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
 570                             "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
 571                             "GRF_UOC0_BASE", "GRF_UOC1_BASE",
 572                             "GRF_UOC2_BASE", "GRF_UOC3_BASE",
 573                             "GRF_UOC4_BASE";
 574                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
 575                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 576                              <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 577                 interrupt-names = "otg_id", "otg_bvalid",
 578                                   "otg_linestate", "host0_linestate",
 579                                   "host1_linestate";
 580                 /*gpios = <&gpio0 GPIO_B6 GPIO_ACTIVE_LOW>,*//*HOST_VBUS_DRV*/
 581                 /*      <&gpio0 GPIO_B4 GPIO_ACTIVE_LOW>;*//*OTG_VBUS_DRV*/
 582                 /*clocks = <&clk_gates4 5>;*/
 583                 /*clock-names = "hclk_usb_peri";*/
 584
 585                 usb_bc{
 586                         compatible = "rockchip,ctrl";
 587                                         /* offset bit mask */
 588                         rk_usb,bvalid     = <0x288 14 1>;
 589                         rk_usb,dcdenb     = <0x328 14 1>;
 590                         rk_usb,vdatsrcenb = <0x328  7 1>;
 591                         rk_usb,vdatdetenb = <0x328  6 1>;
 592                         rk_usb,chrgsel    = <0x328  5 1>;
 593                         rk_usb,chgdet     = <0x2cc 23 1>;
 594                         rk_usb,fsvminus   = <0x2cc 25 1>;
 595                         rk_usb,fsvplus    = <0x2cc 24 1>;
 596                 };
 597         };
 598
 599         usb1: usb@ff580000 {
 600                 compatible = "rockchip,rk3288_usb20_otg";
 601                 reg = <0xff580000 0x40000>;
 602                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 603                 /*clocks = <&clk_otgphy0_480m>, <&clk_gates5 13>;*/
 604                 /*clock-names = "otgphy0", "hclk_otg0";*/
 605         };
 606
 607         usb2: usb@ff540000 {
 608                 compatible = "rockchip,rk3288_usb20_host";
 609                 reg = <0xff540000 0x40000>;
 610                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 611                 /*clocks = <&clk_otgphy1_480m>, <&clk_gates7 3>;*/
 612                 /*clock-names = "otgphy1", "hclk_otg1";*/
 613         };
 614
 615         usb3: usb@ff520000 {
 616                 compatible = "rockchip,rk3288_rk_ohci_host";
 617                 reg = <0xff520000 0x20000>;
 618                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 619                 /*clocks = ;*/
 620                 /*clock-names = ;*/
 621         };
 622
 623         usb4: usb@ff500000 {
 624                 compatible = "rockchip,rk3288_rk_ehci_host";
 625                 reg = <0xff500000 0x20000>;
 626                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 627                 /*clocks = ;*/
 628                 /*clock-names = ;*/
 629         };
 630
 631         usb5: hsic@ff5c0000 {
 632                 compatible = "rockchip,rk3288_rk_hsic_host";
 633                 reg = <0xff5c0000 0x40000>;
 634                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 635                 /*clocks = <&clk_hsicphy480m>, <&clk_gates7 4>,*/
 636                 /*       <&clk_hsicphy12m>, <&clk_otgphy1_480m>;*/
 637                 /*clock-names = "hsicphy480m", "hclk_hsic",*/
 638                 /*            "hsicphy12m", "hsic_otgphy1";*/
 639         };
 640
 641         gmac: eth@ff290000 {
 642                 compatible = "rockchip,gmac";
 643                 reg = <0xff290000 0x10000>;
 644                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
 645                 interrupt-names = "macirq";
 646                 phy-mode = "rmii";
 647                 //phy-mode = "gmii";
 648                 pinctrl-names = "default";
 649                 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
 650         };
 651     gpu{
 652         compatible = "arm,malit764",
 653                      "arm,malit76x",
 654                      "arm,malit7xx",
 655                      "arm,mali-midgard";
 656         reg = <0xffa40000 0x1000>;
 657         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
 658                      <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 659                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 660         interrupt-names = "JOB",
 661                           "MMU",
 662                           "GPU";
 663     };
 664
 665     iep_mmu{
 666         dbgname = "iep";
 667         compatible = "iommu,iep_mmu";
 668         reg = <0xffa40000 0x10000>;
 669         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 670         interrupt-names = "iep_mmu";
 671     };
 672
 673     vip_mmu{
 674         dbgname = "vip";
 675         compatible = "iommu,vip_mmu";
 676         reg = <0xffa40000 0x10000>;
 677         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 678         interrupt-names = "vip_mmu";
 679     };
 680
 681     isp0_mmu{
 682         dbgname = "isp0";
 683         compatible = "iommu,isp0_mmu";
 684         reg = <0xffa40000 0x10000>;
 685         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 686         interrupt-names = "isp0_mmu";
 687     };
 688
 689     isp1_mmu{
 690         dbgname = "isp1";
 691         compatible = "iommu,isp1_mmu";
 692         reg = <0xffa40000 0x10000>;
 693         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 694         interrupt-names = "isp1_mmu";
 695     };
 696
 697     vopb_mmu{
 698         dbgname = "vopb";
 699         compatible = "iommu,vopb_mmu";
 700         reg = <0xffa40000 0x10000>;
 701         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 702         interrupt-names = "vopb_mmu";
 703     };
 704
 705     vopl_mmu{
 706         dbgname = "vopl";
 707         compatible = "iommu,vopl_mmu";
 708         reg = <0xffa40000 0x10000>;
 709         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 710         interrupt-names = "vopl_mmu";
 711     };
 712 };