arch/arm/boot/dts/rk3288.dtsi

   1 #include <dt-bindings/clock/ddr.h>
   2 #include <dt-bindings/interrupt-controller/arm-gic.h>
   3 #include <dt-bindings/rkfb/rk_fb.h>
   4 #include <dt-bindings/suspend/rockchip-pm.h>
   5 #include <dt-bindings/sensor-dev.h>
   6
   7 #include "skeleton.dtsi"
   8 #include "rk3288-pinctrl.dtsi"
   9 #include "rk3288-clocks.dtsi"
  10
  11 / {
  12         compatible = "rockchip,rk3288";
  13         interrupt-parent = <&gic>;
  14
  15         aliases {
  16                 serial2 = &uart_dbg;
  17                 i2c0 = &i2c0;
  18                 i2c1 = &i2c1;
  19                 i2c2 = &i2c2;
  20                 i2c3 = &i2c3;
  21                 i2c4 = &i2c4;
  22                 i2c5 = &i2c5;
  23                 lcdc0 = &lcdc0;
  24                 lcdc1 = &lcdc1;
  25         };
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 cpu@0 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a15";
  34                         reg = <0x500>;
  35                 };
  36                 cpu@1 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a15";
  39                         reg = <0x501>;
  40                 };
  41                 cpu@2 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x502>;
  45                 };
  46                 cpu@3 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a15";
  49                         reg = <0x503>;
  50                 };
  51         };
  52
  53         gic: interrupt-controller@ffc01000 {
  54                 compatible = "arm,cortex-a15-gic";
  55                 interrupt-controller;
  56                 #interrupt-cells = <3>;
  57                 #address-cells = <0>;
  58                 reg = <0xffc01000 0x1000>,
  59                       <0xffc02000 0x1000>;
  60         };
  61
  62         cpu_axi_bus: cpu_axi_bus {
  63                 compatible = "rockchip,cpu_axi_bus";
  64                 #address-cells = <1>;
  65                 #size-cells = <1>;
  66                 ranges;
  67                 qos {
  68                         #address-cells = <1>;
  69                         #size-cells = <1>;
  70                         ranges;
  71                         /* service core */
  72                         cpup {
  73                                 reg = <0xffa80000 0x20>;
  74                         };
  75                         cpum_r {
  76                                 reg = <0xffa80080 0x20>;
  77                         };
  78                         cpum_w {
  79                                 reg = <0xffa80100 0x20>;
  80                         };
  81                         /* service dmac */
  82                         bus_dmac {
  83                                 reg = <0xffa90000 0x20>;
  84                         };
  85                         host {
  86                                 reg = <0xffa90080 0x20>;
  87                         };
  88                         crypto {
  89                                 reg = <0xffa90100 0x20>;
  90                         };
  91                         ccp {
  92                                 reg = <0xffa90180 0x20>;
  93                         };
  94                         ccs {
  95                                 reg = <0xffa90200 0x20>;
  96                         };
  97                         /* service gpu */
  98                         gpu_r {
  99                                 reg = <0xffaa0000 0x20>;
 100                         };
 101                         gpu_w {
 102                                 reg = <0xffaa0080 0x20>;
 103                         };
 104                         /* service peri */
 105                         peri {
 106                                 reg = <0xffab0000 0x20>;
 107                         };
 108                         /* service vio */
 109                         vio1_vop {
 110                                 reg = <0xffad0000 0x20>;
 111                         };
 112                         vio1_isp_w0 {
 113                                 reg = <0xffad0100 0x20>;
 114                         };
 115                         vio1_isp_w1 {
 116                                 reg = <0xffad0180 0x20>;
 117                         };
 118                         vio0_vop {
 119                                 reg = <0xffad0400 0x20>;
 120                         };
 121                         vio0_vip {
 122                                 reg = <0xffad0480 0x20>;
 123                         };
 124                         vio0_iep {
 125                                 reg = <0xffad0500 0x20>;
 126                         };
 127                         vio2_rga_r {
 128                                 reg = <0xffad0800 0x20>;
 129                         };
 130                         vio2_rga_w {
 131                                 reg = <0xffad0880 0x20>;
 132                         };
 133                         vio1_isp_r {
 134                                 reg = <0xffad0900 0x20>;
 135                         };
 136                         /* service video */
 137                         video {
 138                                 reg = <0xffae0000 0x20>;
 139                         };
 140                         /* service hevc */
 141                         hevc_r {
 142                                 reg = <0xffaf0000 0x20>;
 143                         };
 144                         hevc_w {
 145                                 reg = <0xffaf0080 0x20>;
 146                         };
 147                 };
 148                 msch {
 149                         #address-cells = <1>;
 150                         #size-cells = <1>;
 151                         ranges;
 152                         msch@0 {
 153                                 reg = <0xffac0000 0x40>;
 154                                 rockchip,read-latency = <0xff>;
 155                         };
 156                         msch@1 {
 157                                 reg = <0xffac0080 0x40>;
 158                                 rockchip,read-latency = <0xff>;
 159                         };
 160                 };
 161         };
 162
 163         sram: sram@ff710000 {
 164                 compatible = "mmio-sram";
 165                 reg = <0xff710000 0x8000>; /* 32k */
 166                 map-exec;
 167         };
 168
 169         timer {
 170                 compatible = "arm,armv7-timer";
 171                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 172                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 173                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 174                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 175                 clock-frequency = <24000000>;
 176         };
 177
 178         timer@ff810000 {
 179                 compatible = "rockchip,timer";
 180                 reg = <0xff810000 0x20>;
 181                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 182                 rockchip,broadcast = <1>;
 183         };
 184
 185         timer@ff810020 {
 186                 compatible = "rockchip,timer";
 187                 reg = <0xff810020 0x20>;
 188                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 189                 rockchip,clocksource = <1>;
 190                 rockchip,count-up = <1>;
 191         };
 192
 193
 194         emmc: rksdmmc@ff0f0000 {
 195                 compatible = "rockchip,rk_mmc";
 196                 reg = <0xff0f0000 0x4000>;
 197                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;/*irq=67*/
 198                 #address-cells = <1>;
 199                 #size-cells = <0>;
 200                 //pinctrl-names = "default",,"suspend";
 201                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 202
 203                 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_3 --clk_emmc_src_gate_en*/
 204                 //clocks = <&clk_gates8 0>, <&clk_gates8 0>;
 205                 num-slots = <1>;
 206                 fifo-depth = <0x80>;
 207                 bus-width = <4>;
 208         };
 209
 210         sdmmc: rksdmmc@ff0c0000 {
 211                 compatible = "rockchip,rk_mmc";
 212                 reg = <0xff0c0000 0x4000>;
 213                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; /*irq=64*/
 214                 #address-cells = <1>;
 215                 #size-cells = <0>;
 216
 217                 //pinctrl-names = "default","suspend";
 218                 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
 219                 //pinctrl-1 = <&sd0_cd_gpio>; //for int gpio?
 220
 221                 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_0 --clk_mmc0_src_gate_en*/
 222                 //clocks = <&clk_gates8 0>, <&clk_gates13 0>;
 223                 num-slots = <1>;
 224                 fifo-depth = <0x100>;
 225                 bus-width = <4>;
 226
 227         };
 228
 229         sdio: rksdmmc@ff0d0000 {
 230                 compatible = "rockchip,rk_mmc";
 231                 reg = <0xff0d0000 0x4000>;
 232                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 233                 #address-cells = <1>;
 234                 #size-cells = <0>;
 235                 //pinctrl-names = "default","suspend";
 236                 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 237
 238                 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_1 --clk_sdio0_src_gate_en*/
 239                 //clocks = <&clk_gates8 0>, <&clk_gates13 1>;
 240                 num-slots = <1>;
 241
 242                 fifo-depth = <0x100>;
 243                 bus-width = <4>;
 244         };
 245
 246         sdio1: rksdmmc@ff0e0000 {
 247                 compatible = "rockchip,rk_mmc";
 248                 reg = <0xff0e0000 0x4000>;
 249                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 250                 #address-cells = <1>;
 251                 #size-cells = <0>;
 252                 //pinctrl-names = "default","suspend";
 253                 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 254
 255                 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_2 --clk_sdio1_src_gate_en*/
 256                 //clocks = <&clk_gates8 0>, <&clk_gates13 2>;
 257                 num-slots = <1>;
 258
 259                 fifo-depth = <0x100>;
 260                 bus-width = <4>;
 261         };
 262
 263         spi0: spi@ff110000 {
 264                 compatible = "rockchip,rockchip-spi";
 265                 reg = <0xff110000 0x1000>;
 266                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 267                 #address-cells = <1>;
 268                 #size-cells = <0>;
 269                 pinctrl-names = "default";
 270                 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
 271                 rockchip,spi-src-clk = <0>;
 272                 num-cs = <2>;
 273                 clocks =<&clk_spi0>, <&clk_gates6 4>;
 274                 clock-names = "spi","pclk_spi0";
 275                 //dmas = <&pdma1 11>, <&pdma1 12>;
 276                 //#dma-cells = <2>;
 277                 //dma-names = "tx", "rx";
 278                 status = "disabled";
 279         };
 280
 281         spi1: spi@ff120000 {
 282                 compatible = "rockchip,rockchip-spi";
 283                 reg = <0xff120000 0x1000>;
 284                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 285                 #address-cells = <1>;
 286                 #size-cells = <0>;
 287                 pinctrl-names = "default";
 288                 pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0>;
 289                 rockchip,spi-src-clk = <1>;
 290                 num-cs = <1>;
 291                 clocks = <&clk_spi1>, <&clk_gates6 5>;
 292                 clock-names = "spi","pclk_spi1";
 293                 //dmas = <&pdma1 13>, <&pdma1 14>;
 294                 //#dma-cells = <2>;
 295                 //dma-names = "tx", "rx";
 296                 status = "disabled";
 297         };
 298
 299         spi2: spi@ff130000 {
 300                 compatible = "rockchip,rockchip-spi";
 301                 reg = <0xff130000 0x1000>;
 302                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 303                 #address-cells = <1>;
 304                 #size-cells = <0>;
 305                 pinctrl-names = "default";
 306                 pinctrl-0 = <&spi2_txd &spi2_rxd &spi2_clk &spi2_cs0 &spi2_cs1>;
 307                 rockchip,spi-src-clk = <1>;
 308                 num-cs = <2>;
 309                 clocks = <&clk_spi2>, <&clk_gates6 6>;
 310                 clock-names = "spi","pclk_spi2";
 311                 //dmas = <&pdma1 15>, <&pdma1 16>;
 312                 //#dma-cells = <2>;
 313                 //dma-names = "tx", "rx";
 314                 status = "disabled";
 315         };
 316
 317
 318         uart_dbg: serial@ff690000 {
 319                 compatible = "rockchip,serial";
 320                 reg = <0xff690000 0x100>;
 321                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 322                 clock-frequency = <24000000>;
 323                 reg-shift = <2>;
 324                 reg-io-width = <4>;
 325                 status = "disabled";
 326         };
 327
 328         fiq-debugger {
 329                 compatible = "rockchip,fiq-debugger";
 330                 rockchip,serial-id = <2>;
 331                 rockchip,signal-irq = <106>;
 332                 rockchip,wake-irq = <0>;
 333                 status = "disabled";
 334         };
 335
 336         clocks-init{
 337                 compatible = "rockchip,clocks-init";
 338                 rockchip,clocks-init-parent =
 339                         <&clk_core &clk_apll>,  <&aclk_bus_src &clk_gpll>,
 340                         <&aclk_peri &clk_gpll>, <&uart_pll_mux &clk_gpll>,
 341                         <&clk_i2s_pll &clk_cpll>;
 342                 rockchip,clocks-init-rate =
 343                         <&clk_core 792000000>,  <&clk_gpll 594000000>,
 344                         <&clk_cpll 384000000>,  <&clk_npll 500000000>,
 345                         <&aclk_bus_src 300000000>,      <&aclk_bus 300000000>,
 346                         <&hclk_bus 150000000>,  <&pclk_bus 75000000>,
 347                         <&clk_crypto 150000000>,        <&aclk_peri 300000000>,
 348                         <&hclk_peri 150000000>, <&pclk_peri 75000000>,
 349                         <&clk_gpu 200000000>,   <&aclk_vio0 300000000>,
 350                         <&aclk_vio1 300000000>, <&hclk_vio 75000000>,
 351                         <&pclk_pd_alive 100000000>,     <&pclk_pd_pmu 100000000>;
 352         };
 353
 354         i2c0: i2c@ff650000 {
 355                 compatible = "rockchip,rk30-i2c";
 356                 reg = <0xff650000 0x1000>;
 357                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 358                 #address-cells = <1>;
 359                 #size-cells = <0>;
 360                 //pinctrl-names = "default", "gpio";
 361                 //pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 362                 //pinctrl-1 = <&i2c0_gpio>;
 363                 //gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
 364                 //clocks = <&clk_gates8 4>;
 365                 rockchip,check-idle = <1>;
 366                 status = "disabled";
 367         };
 368
 369         i2c1: i2c@ff140000 {
 370                 compatible = "rockchip,rk30-i2c";
 371                 reg = <0xff140000 0x1000>;
 372                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 373                 #address-cells = <1>;
 374                 #size-cells = <0>;
 375                 //pinctrl-names = "default", "gpio";
 376                 //pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 377                 //pinctrl-1 = <&i2c1_gpio>;
 378                 //gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
 379                 //clocks = <&clk_gates8 5>;
 380                 rockchip,check-idle = <1>;
 381                 status = "disabled";
 382         };
 383
 384         i2c2: i2c@ff660000 {
 385                 compatible = "rockchip,rk30-i2c";
 386                 reg = <0xff660000 0x1000>;
 387                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 388                 #address-cells = <1>;
 389                 #size-cells = <0>;
 390                 //pinctrl-names = "default", "gpio";
 391                 //pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 392                 //pinctrl-1 = <&i2c2_gpio>;
 393                 //gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
 394                 //clocks = <&clk_gates8 6>;
 395                 rockchip,check-idle = <1>;
 396                 status = "disabled";
 397         };
 398
 399         i2c3: i2c@ff150000 {
 400                 compatible = "rockchip,rk30-i2c";
 401                 reg = <0xff150000 0x1000>;
 402                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 403                 #address-cells = <1>;
 404                 #size-cells = <0>;
 405                 //pinctrl-names = "default", "gpio";
 406                 //pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 407                 //pinctrl-1 = <&i2c3_gpio>;
 408                 //gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
 409                 //clocks = <&clk_gates8 7>;
 410                 rockchip,check-idle = <1>;
 411                 status = "disabled";
 412         };
 413
 414         i2c4: i2c@ff160000 {
 415                 compatible = "rockchip,rk30-i2c";
 416                 reg = <0xff160000 0x1000>;
 417                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 418                 #address-cells = <1>;
 419                 #size-cells = <0>;
 420                 //pinctrl-names = "default", "gpio";
 421                 //pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 422                 //pinctrl-1 = <&i2c4_gpio>;
 423                 //gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
 424                 //clocks = <&clk_gates8 8>;
 425                 rockchip,check-idle = <1>;
 426                 status = "disabled";
 427         };
 428
 429         i2c5: i2c@ff170000 {
 430                 compatible = "rockchip,rk30-i2c";
 431                 reg = <0xff170000 0x1000>;
 432                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 433                 #address-cells = <1>;
 434                 #size-cells = <0>;
 435                 //pinctrl-names = "default", "gpio";
 436                 //pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 437                 //pinctrl-1 = <&i2c5_gpio>;
 438                 //gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
 439                 //clocks = <&clk_gates8 8>;
 440                 rockchip,check-idle = <1>;
 441                 status = "disabled";
 442         };
 443
 444
 445         fb: fb{
 446                 compatible = "rockchip,rk-fb";
 447                 rockchip,disp-mode = <DUAL>;
 448         };
 449
 450         rk_screen: rk_screen{
 451                         compatible = "rockchip,screen";
 452         };
 453
 454         lvds: lvds@ff96c000 {
 455                 compatible = "rockchip, rk32-lvds";
 456                 reg = <0xff960000 0x20000>;
 457                 clocks = <&clk_gates16 7>;
 458                 clock-names = "pclk_lvds";
 459         };
 460
 461         edp: edp@ff970000 {
 462                 compatible = "rockchip,rk32-edp";
 463                 reg = <0xff970000 0x4000>;
 464                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 465                 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates16 8>;
 466                 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
 467         };
 468
 469         hdmi: hdmi@ff980000 {
 470                 compatible = "rockchip,rk3288-hdmi";
 471                 reg = <0xff980000 0x20000>;
 472                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 473                 pinctrl-names = "default", "gpio";
 474                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 475                 pinctrl-1 = <&i2c5_gpio>;
 476                 clocks = <&clk_gates16 9>;
 477                 clock-names = "pclk_hdmi";
 478                 status = "disabled";
 479         };
 480
 481         lcdc1: lcdc@ff940000 {
 482                 compatible = "rockchip,rk3288-lcdc";
 483                 rockchip,prop = <PRMRY>;
 484                 rochchip,pwr18 = <0>;
 485                 reg = <0xff940000 0x10000>;
 486                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 487                 pinctrl-names = "default", "gpio";
 488                 pinctrl-0 = <&lcdc0_lcdc>;
 489                 pinctrl-1 = <&lcdc0_gpio>;
 490                 status = "disabled";
 491         };
 492
 493         lcdc0: lcdc@ff930000 {
 494                 compatible = "rockchip,rk3288-lcdc";
 495                 rockchip,prop = <EXTEND>;
 496                 rockchip,pwr18 = <0>;
 497                 reg = <0xff930000 0x10000>;
 498                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 499                 //pinctrl-names = "default", "gpio";
 500                 //pinctrl-0 = <&lcdc0_lcdc>;
 501                 //pinctrl-1 = <&lcdc0_gpio>;
 502                 status = "disabled";
 503         };
 504
 505         adc: adc@ff100000 {
 506                 compatible = "rockchip,saradc";
 507                 reg = <0xff100000 0x100>;
 508                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 509                 #io-channel-cells = <1>;
 510                 io-channel-ranges;
 511                 rockchip,adc-vref = <1800>;
 512                 clock-frequency = <1000000>;
 513                 clock-names = "saradc", "pclk_saradc";
 514                 status = "disabled";
 515         };
 516
 517         rga@ff920000 {
 518                 compatible = "rockchip,rga";
 519                 reg = <0xff920000 0x1000>;
 520                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 521                 clock-names = "hclk_rga", "aclk_rga";
 522         };
 523
 524         i2s: rockchip-i2s@0xff890000 {
 525                 compatible = "rockchip-i2s";
 526                 reg = <0xff890000 0x10000>;
 527                 i2s-id = <0>;
 528         //      clocks = <&clk_i2s>;
 529         //      clock-names = "i2s_clk","i2s_mclk";
 530                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 531         //      dmas = <&pdma0 0>,
 532         //              <&pdma0 1>;
 533                 //#dma-cells = <2>;
 534         //      dma-names = "tx", "rx";
 535         //      pinctrl-names = "default", "sleep";
 536         //      pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo0 &i2s0_sdo1 &i2s0_sdo2 &i2s0_sdo3>;
 537         //      pinctrl-1 = <&i2s0_gpio>;
 538         };
 539
 540         spdif: rockchip-spdif@0xff8b0000 {
 541                 compatible = "rockchip-spdif";
 542                 reg = <0xff8b0000 0x10000>;     //8channel
 543                 //reg = <ff880000 0x2000>;//2channel
 544         //      clocks = <&clk_spdif>;
 545         //      clock-names = "spdif_mclk";
 546                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 547         //      dmas = <&pdma0 8>;
 548                 //#dma-cells = <1>;
 549         //      dma-names = "tx";
 550         //      pinctrl-names = "default";
 551         //      pinctrl-0 = <&spdif_tx>;
 552         };
 553
 554         pwm0: pwm@ff680000 {
 555                 compatible = "rockchip,rk-pwm";
 556                 reg = <0xff680000 0x10>;
 557                 #pwm-cells = <2>;
 558                 pinctrl-names = "default";
 559                 pinctrl-0 = <&pwm0_pin>;
 560                 status = "okay";
 561         };
 562
 563         pwm1: pwm@ff680010 {
 564                 compatible = "rockchip,rk-pwm";
 565                 reg = <0xff680010 0x10>;
 566                 #pwm-cells = <2>;
 567                 pinctrl-names = "default";
 568                 pinctrl-0 = <&pwm1_pin>;
 569                 status = "disabled";
 570         };
 571
 572         pwm2: pwm@ff680020 {
 573                 compatible = "rockchip,rk-pwm";
 574                 reg = <0xff680020 0x10>;
 575                 #pwm-cells = <2>;
 576                 pinctrl-names = "default";
 577                 pinctrl-0 = <&pwm2_pin>;
 578                 status = "disabled";
 579         };
 580
 581         pwm3: pwm@ff680030 {
 582                 compatible = "rockchip,rk-pwm";
 583                 reg = <0xff680030 0x10>;
 584                 #pwm-cells = <2>;
 585                 pinctrl-names = "default";
 586                 pinctrl-0 = <&pwm3_pin>;
 587                 status = "disabled";
 588         };
 589
 590         ion {
 591                 compatible = "rockchip,ion";
 592                 #address-cells = <1>;
 593                 #size-cells = <0>;
 594                 rockchip,ion-heap@1 { /* CMA HEAP */
 595                         compatible = "rockchip,ion-reserve";
 596                         reg = <1>;
 597                         memory-reservation = <0x00000000 0x10000000>; /* 256MB */
 598                 };
 599                 rockchip,ion-heap@3 { /* SYSTEM HEAP */
 600                         reg = <3>;
 601                 };
 602         };
 603
 604
 605         vpu: vpu_service@ff9a0000 {
 606                 compatible = "vpu_service";
 607                 reg = <0xff9a0000 0x800>;
 608                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 609                 interrupt-names = "irq_enc", "irq_dec";
 610
 611                 clock-names = "aclk_vcodec", "hclk_vcodec";
 612                 name = "vpu_service";
 613                 status = "disabled";
 614         };
 615
 616         hevc: hevc_service@ff9c0000 {
 617                 compatible = "rockchip,hevc_service";
 618                 reg = <0xff9c0000 0x800>;
 619                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 620                 interrupt-names = "irq_dec";
 621
 622                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
 623                 name = "hevc_service";
 624                 status = "disabled";
 625         };
 626
 627         iep: iep@ff900000 {
 628                 compatible = "rockchip,iep";
 629                 reg = <0xff900000 0x800>;
 630                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 631
 632                 clock_names = "aclk_iep", "hclk_iep";
 633                 status = "disabled";
 634         };
 635
 636         dwc_control_usb: dwc-control-usb@ff770284 {
 637                 compatible = "rockchip,rk3288-dwc-control-usb";
 638                 reg = <0xff770284 0x04>, <0xff770288 0x04>,
 639                       <0xff7702cc 0x04>, <0xff7702d4 0x04>,
 640                       <0xff770320 0x14>, <0xff770334 0x14>,
 641                       <0xff770348 0x10>, <0xff770358 0x08>,
 642                       <0xff770360 0x08>;
 643                 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
 644                             "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
 645                             "GRF_UOC0_BASE", "GRF_UOC1_BASE",
 646                             "GRF_UOC2_BASE", "GRF_UOC3_BASE",
 647                             "GRF_UOC4_BASE";
 648                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
 649                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 650                              <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 651                 interrupt-names = "otg_id", "otg_bvalid",
 652                                   "otg_linestate", "host0_linestate",
 653                                   "host1_linestate";
 654                 /*gpios = <&gpio0 GPIO_B6 GPIO_ACTIVE_LOW>,*//*HOST_VBUS_DRV*/
 655                 /*      <&gpio0 GPIO_B4 GPIO_ACTIVE_LOW>;*//*OTG_VBUS_DRV*/
 656                 /*clocks = <&clk_gates4 5>;*/
 657                 /*clock-names = "hclk_usb_peri";*/
 658
 659                 usb_bc{
 660                         compatible = "rockchip,ctrl";
 661                                         /* offset bit mask */
 662                         rk_usb,bvalid     = <0x288 14 1>;
 663                         rk_usb,dcdenb     = <0x328 14 1>;
 664                         rk_usb,vdatsrcenb = <0x328  7 1>;
 665                         rk_usb,vdatdetenb = <0x328  6 1>;
 666                         rk_usb,chrgsel    = <0x328  5 1>;
 667                         rk_usb,chgdet     = <0x2cc 23 1>;
 668                         rk_usb,fsvminus   = <0x2cc 25 1>;
 669                         rk_usb,fsvplus    = <0x2cc 24 1>;
 670                 };
 671         };
 672
 673         usb1: usb@ff580000 {
 674                 compatible = "rockchip,rk3288_usb20_otg";
 675                 reg = <0xff580000 0x40000>;
 676                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 677                 /*clocks = <&clk_otgphy0_480m>, <&clk_gates5 13>;*/
 678                 /*clock-names = "otgphy0", "hclk_otg0";*/
 679         };
 680
 681         usb2: usb@ff540000 {
 682                 compatible = "rockchip,rk3288_usb20_host";
 683                 reg = <0xff540000 0x40000>;
 684                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 685                 /*clocks = <&clk_otgphy1_480m>, <&clk_gates7 3>;*/
 686                 /*clock-names = "otgphy1", "hclk_otg1";*/
 687         };
 688
 689         usb3: usb@ff520000 {
 690                 compatible = "rockchip,rk3288_rk_ohci_host";
 691                 reg = <0xff520000 0x20000>;
 692                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 693                 /*clocks = ;*/
 694                 /*clock-names = ;*/
 695         };
 696
 697         usb4: usb@ff500000 {
 698                 compatible = "rockchip,rk3288_rk_ehci_host";
 699                 reg = <0xff500000 0x20000>;
 700                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 701                 /*clocks = ;*/
 702                 /*clock-names = ;*/
 703         };
 704
 705         usb5: hsic@ff5c0000 {
 706                 compatible = "rockchip,rk3288_rk_hsic_host";
 707                 reg = <0xff5c0000 0x40000>;
 708                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 709                 /*clocks = <&clk_hsicphy480m>, <&clk_gates7 4>,*/
 710                 /*       <&clk_hsicphy12m>, <&clk_otgphy1_480m>;*/
 711                 /*clock-names = "hsicphy480m", "hclk_hsic",*/
 712                 /*            "hsicphy12m", "hsic_otgphy1";*/
 713         };
 714
 715         gmac: eth@ff290000 {
 716                 compatible = "rockchip,gmac";
 717                 reg = <0xff290000 0x10000>;
 718                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
 719                 interrupt-names = "macirq";
 720                 phy-mode = "rmii";
 721                 //phy-mode = "gmii";
 722                 pinctrl-names = "default";
 723                 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
 724         };
 725     gpu{
 726         compatible = "arm,malit764",
 727                      "arm,malit76x",
 728                      "arm,malit7xx",
 729                      "arm,mali-midgard";
 730         reg = <0xffa40000 0x1000>;
 731         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
 732                      <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 733                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 734         interrupt-names = "JOB",
 735                           "MMU",
 736                           "GPU";
 737     };
 738
 739     iep_mmu{
 740         dbgname = "iep";
 741         compatible = "iommu,iep_mmu";
 742         reg = <0xffa40000 0x10000>;
 743         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 744         interrupt-names = "iep_mmu";
 745     };
 746
 747     vip_mmu{
 748         dbgname = "vip";
 749         compatible = "iommu,vip_mmu";
 750         reg = <0xffa40000 0x10000>;
 751         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 752         interrupt-names = "vip_mmu";
 753     };
 754
 755     isp0_mmu{
 756         dbgname = "isp0";
 757         compatible = "iommu,isp0_mmu";
 758         reg = <0xffa40000 0x10000>;
 759         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 760         interrupt-names = "isp0_mmu";
 761     };
 762
 763     isp1_mmu{
 764         dbgname = "isp1";
 765         compatible = "iommu,isp1_mmu";
 766         reg = <0xffa40000 0x10000>;
 767         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 768         interrupt-names = "isp1_mmu";
 769     };
 770
 771     vopb_mmu{
 772         dbgname = "vopb";
 773         compatible = "iommu,vopb_mmu";
 774         reg = <0xffa40000 0x10000>;
 775         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 776         interrupt-names = "vopb_mmu";
 777     };
 778
 779     vopl_mmu{
 780         dbgname = "vopl";
 781         compatible = "iommu,vopl_mmu";
 782         reg = <0xffa40000 0x10000>;
 783         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 784         interrupt-names = "vopl_mmu";
 785     };
 786 };