2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3288-cru.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include "skeleton.dtsi"
50 compatible = "rockchip,rk3288";
52 interrupt-parent = <&gic>;
76 compatible = "arm,cortex-a12-pmu";
77 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
81 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
87 enable-method = "rockchip,rk3066-smp";
88 rockchip,pmu = <&pmu>;
92 compatible = "arm,cortex-a12";
94 resets = <&cru SRST_CORE0>;
110 #cooling-cells = <2>; /* min followed by max */
111 clock-latency = <40000>;
112 clocks = <&cru ARMCLK>;
116 compatible = "arm,cortex-a12";
118 resets = <&cru SRST_CORE1>;
122 compatible = "arm,cortex-a12";
124 resets = <&cru SRST_CORE2>;
128 compatible = "arm,cortex-a12";
130 resets = <&cru SRST_CORE3>;
135 compatible = "arm,amba-bus";
136 #address-cells = <1>;
140 dmac_peri: dma-controller@ff250000 {
141 compatible = "arm,pl330", "arm,primecell";
142 reg = <0xff250000 0x4000>;
143 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
146 clocks = <&cru ACLK_DMAC2>;
147 clock-names = "apb_pclk";
150 dmac_bus_ns: dma-controller@ff600000 {
151 compatible = "arm,pl330", "arm,primecell";
152 reg = <0xff600000 0x4000>;
153 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&cru ACLK_DMAC1>;
157 clock-names = "apb_pclk";
161 dmac_bus_s: dma-controller@ffb20000 {
162 compatible = "arm,pl330", "arm,primecell";
163 reg = <0xffb20000 0x4000>;
164 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
167 clocks = <&cru ACLK_DMAC1>;
168 clock-names = "apb_pclk";
173 #address-cells = <1>;
178 * The rk3288 cannot use the memory area above 0xfe000000
179 * for dma operations for some reason. While there is
180 * probably a better solution available somewhere, we
181 * haven't found it yet and while devices with 2GB of ram
182 * are not affected, this issue prevents 4GB from booting.
183 * So to make these devices at least bootable, block
184 * this area for the time being until the real solution
187 dma-unusable@fe000000 {
188 reg = <0xfe000000 0x1000000>;
193 compatible = "fixed-clock";
194 clock-frequency = <24000000>;
195 clock-output-names = "xin24m";
200 compatible = "arm,armv7-timer";
201 arm,cpu-registers-not-fw-configured;
202 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
203 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
204 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
205 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
206 clock-frequency = <24000000>;
209 timer: timer@ff810000 {
210 compatible = "rockchip,rk3288-timer";
211 reg = <0xff810000 0x20>;
212 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&xin24m>, <&cru PCLK_TIMER>;
214 clock-names = "timer", "pclk";
218 compatible = "rockchip,display-subsystem";
219 ports = <&vopl_out>, <&vopb_out>;
222 sdmmc: dwmmc@ff0c0000 {
223 compatible = "rockchip,rk3288-dw-mshc";
224 clock-freq-min-max = <400000 150000000>;
225 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
226 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
227 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
228 fifo-depth = <0x100>;
229 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
230 reg = <0xff0c0000 0x4000>;
234 sdio0: dwmmc@ff0d0000 {
235 compatible = "rockchip,rk3288-dw-mshc";
236 clock-freq-min-max = <400000 150000000>;
237 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
238 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
239 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
240 fifo-depth = <0x100>;
241 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
242 reg = <0xff0d0000 0x4000>;
246 sdio1: dwmmc@ff0e0000 {
247 compatible = "rockchip,rk3288-dw-mshc";
248 clock-freq-min-max = <400000 150000000>;
249 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
250 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
251 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
252 fifo-depth = <0x100>;
253 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
254 reg = <0xff0e0000 0x4000>;
258 emmc: dwmmc@ff0f0000 {
259 compatible = "rockchip,rk3288-dw-mshc";
260 clock-freq-min-max = <400000 150000000>;
261 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
262 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
263 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
264 fifo-depth = <0x100>;
265 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
266 reg = <0xff0f0000 0x4000>;
270 saradc: saradc@ff100000 {
271 compatible = "rockchip,saradc";
272 reg = <0xff100000 0x100>;
273 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
274 #io-channel-cells = <1>;
275 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
276 clock-names = "saradc", "apb_pclk";
281 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
282 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
283 clock-names = "spiclk", "apb_pclk";
284 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
285 dma-names = "tx", "rx";
286 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
287 pinctrl-names = "default";
288 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
289 reg = <0xff110000 0x1000>;
290 #address-cells = <1>;
296 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
297 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
298 clock-names = "spiclk", "apb_pclk";
299 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
300 dma-names = "tx", "rx";
301 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
302 pinctrl-names = "default";
303 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
304 reg = <0xff120000 0x1000>;
305 #address-cells = <1>;
311 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
312 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
313 clock-names = "spiclk", "apb_pclk";
314 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
315 dma-names = "tx", "rx";
316 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
317 pinctrl-names = "default";
318 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
319 reg = <0xff130000 0x1000>;
320 #address-cells = <1>;
326 compatible = "rockchip,rk3288-i2c";
327 reg = <0xff140000 0x1000>;
328 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
329 #address-cells = <1>;
332 clocks = <&cru PCLK_I2C1>;
333 pinctrl-names = "default";
334 pinctrl-0 = <&i2c1_xfer>;
339 compatible = "rockchip,rk3288-i2c";
340 reg = <0xff150000 0x1000>;
341 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
342 #address-cells = <1>;
345 clocks = <&cru PCLK_I2C3>;
346 pinctrl-names = "default";
347 pinctrl-0 = <&i2c3_xfer>;
352 compatible = "rockchip,rk3288-i2c";
353 reg = <0xff160000 0x1000>;
354 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
355 #address-cells = <1>;
358 clocks = <&cru PCLK_I2C4>;
359 pinctrl-names = "default";
360 pinctrl-0 = <&i2c4_xfer>;
365 compatible = "rockchip,rk3288-i2c";
366 reg = <0xff170000 0x1000>;
367 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
368 #address-cells = <1>;
371 clocks = <&cru PCLK_I2C5>;
372 pinctrl-names = "default";
373 pinctrl-0 = <&i2c5_xfer>;
377 uart0: serial@ff180000 {
378 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
379 reg = <0xff180000 0x100>;
380 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
384 clock-names = "baudclk", "apb_pclk";
385 pinctrl-names = "default";
386 pinctrl-0 = <&uart0_xfer>;
390 uart1: serial@ff190000 {
391 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
392 reg = <0xff190000 0x100>;
393 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
396 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
397 clock-names = "baudclk", "apb_pclk";
398 pinctrl-names = "default";
399 pinctrl-0 = <&uart1_xfer>;
403 uart2: serial@ff690000 {
404 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
405 reg = <0xff690000 0x100>;
406 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
410 clock-names = "baudclk", "apb_pclk";
411 pinctrl-names = "default";
412 pinctrl-0 = <&uart2_xfer>;
416 uart3: serial@ff1b0000 {
417 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
418 reg = <0xff1b0000 0x100>;
419 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
423 clock-names = "baudclk", "apb_pclk";
424 pinctrl-names = "default";
425 pinctrl-0 = <&uart3_xfer>;
429 uart4: serial@ff1c0000 {
430 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
431 reg = <0xff1c0000 0x100>;
432 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
436 clock-names = "baudclk", "apb_pclk";
437 pinctrl-names = "default";
438 pinctrl-0 = <&uart4_xfer>;
443 #include "rk3288-thermal.dtsi"
446 tsadc: tsadc@ff280000 {
447 compatible = "rockchip,rk3288-tsadc";
448 reg = <0xff280000 0x100>;
449 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
450 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
451 clock-names = "tsadc", "apb_pclk";
452 resets = <&cru SRST_TSADC>;
453 reset-names = "tsadc-apb";
454 pinctrl-names = "default";
455 pinctrl-0 = <&otp_out>;
456 #thermal-sensor-cells = <1>;
457 rockchip,hw-tshut-temp = <95000>;
461 gmac: ethernet@ff290000 {
462 compatible = "rockchip,rk3288-gmac";
463 reg = <0xff290000 0x10000>;
464 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
465 interrupt-names = "macirq";
466 rockchip,grf = <&grf>;
467 clocks = <&cru SCLK_MAC>,
468 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
469 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
470 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
471 clock-names = "stmmaceth",
472 "mac_clk_rx", "mac_clk_tx",
473 "clk_mac_ref", "clk_mac_refout",
474 "aclk_mac", "pclk_mac";
475 resets = <&cru SRST_MAC>;
476 reset-names = "stmmaceth";
480 usb_host0_ehci: usb@ff500000 {
481 compatible = "generic-ehci";
482 reg = <0xff500000 0x100>;
483 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&cru HCLK_USBHOST0>;
485 clock-names = "usbhost";
491 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
493 usb_host1: usb@ff540000 {
494 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
496 reg = <0xff540000 0x40000>;
497 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&cru HCLK_USBHOST1>;
502 phy-names = "usb2-phy";
506 usb_otg: usb@ff580000 {
507 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
509 reg = <0xff580000 0x40000>;
510 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&cru HCLK_OTG0>;
514 g-np-tx-fifo-size = <16>;
515 g-rx-fifo-size = <275>;
516 g-tx-fifo-size = <256 128 128 64 64 32>;
519 phy-names = "usb2-phy";
523 usb_hsic: usb@ff5c0000 {
524 compatible = "generic-ehci";
525 reg = <0xff5c0000 0x100>;
526 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
527 clocks = <&cru HCLK_HSIC>;
528 clock-names = "usbhost";
533 compatible = "rockchip,rk3288-i2c";
534 reg = <0xff650000 0x1000>;
535 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
536 #address-cells = <1>;
539 clocks = <&cru PCLK_I2C0>;
540 pinctrl-names = "default";
541 pinctrl-0 = <&i2c0_xfer>;
546 compatible = "rockchip,rk3288-i2c";
547 reg = <0xff660000 0x1000>;
548 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
549 #address-cells = <1>;
552 clocks = <&cru PCLK_I2C2>;
553 pinctrl-names = "default";
554 pinctrl-0 = <&i2c2_xfer>;
559 compatible = "rockchip,rk3288-pwm";
560 reg = <0xff680000 0x10>;
562 pinctrl-names = "default";
563 pinctrl-0 = <&pwm0_pin>;
564 clocks = <&cru PCLK_PWM>;
570 compatible = "rockchip,rk3288-pwm";
571 reg = <0xff680010 0x10>;
573 pinctrl-names = "default";
574 pinctrl-0 = <&pwm1_pin>;
575 clocks = <&cru PCLK_PWM>;
581 compatible = "rockchip,rk3288-pwm";
582 reg = <0xff680020 0x10>;
584 pinctrl-names = "default";
585 pinctrl-0 = <&pwm2_pin>;
586 clocks = <&cru PCLK_PWM>;
592 compatible = "rockchip,rk3288-pwm";
593 reg = <0xff680030 0x10>;
595 pinctrl-names = "default";
596 pinctrl-0 = <&pwm3_pin>;
597 clocks = <&cru PCLK_PWM>;
602 bus_intmem@ff700000 {
603 compatible = "mmio-sram";
604 reg = <0xff700000 0x18000>;
605 #address-cells = <1>;
607 ranges = <0 0xff700000 0x18000>;
609 compatible = "rockchip,rk3066-smp-sram";
615 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
616 reg = <0xff720000 0x1000>;
619 pmu: power-management@ff730000 {
620 compatible = "rockchip,rk3288-pmu", "syscon";
621 reg = <0xff730000 0x100>;
624 sgrf: syscon@ff740000 {
625 compatible = "rockchip,rk3288-sgrf", "syscon";
626 reg = <0xff740000 0x1000>;
629 cru: clock-controller@ff760000 {
630 compatible = "rockchip,rk3288-cru";
631 reg = <0xff760000 0x1000>;
632 rockchip,grf = <&grf>;
635 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
636 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
637 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
638 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
640 assigned-clock-rates = <594000000>, <400000000>,
641 <500000000>, <300000000>,
642 <150000000>, <75000000>,
643 <300000000>, <150000000>,
647 grf: syscon@ff770000 {
648 compatible = "rockchip,rk3288-grf", "syscon";
649 reg = <0xff770000 0x1000>;
652 wdt: watchdog@ff800000 {
653 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
654 reg = <0xff800000 0x100>;
655 clocks = <&cru PCLK_WDT>;
656 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
661 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
662 reg = <0xff890000 0x10000>;
663 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
664 #address-cells = <1>;
666 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
667 dma-names = "tx", "rx";
668 clock-names = "i2s_hclk", "i2s_clk";
669 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
670 pinctrl-names = "default";
671 pinctrl-0 = <&i2s0_bus>;
676 compatible = "rockchip,rk3288-vop";
677 reg = <0xff930000 0x19c>;
678 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
679 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
680 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
681 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
682 reset-names = "axi", "ahb", "dclk";
683 iommus = <&vopb_mmu>;
687 #address-cells = <1>;
690 vopb_out_hdmi: endpoint@0 {
692 remote-endpoint = <&hdmi_in_vopb>;
697 vopb_mmu: iommu@ff930300 {
698 compatible = "rockchip,iommu";
699 reg = <0xff930300 0x100>;
700 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
701 interrupt-names = "vopb_mmu";
707 compatible = "rockchip,rk3288-vop";
708 reg = <0xff940000 0x19c>;
709 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
710 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
711 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
712 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
713 reset-names = "axi", "ahb", "dclk";
714 iommus = <&vopl_mmu>;
718 #address-cells = <1>;
721 vopl_out_hdmi: endpoint@0 {
723 remote-endpoint = <&hdmi_in_vopl>;
728 vopl_mmu: iommu@ff940300 {
729 compatible = "rockchip,iommu";
730 reg = <0xff940300 0x100>;
731 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
732 interrupt-names = "vopl_mmu";
737 hdmi: hdmi@ff980000 {
738 compatible = "rockchip,rk3288-dw-hdmi";
739 reg = <0xff980000 0x20000>;
741 rockchip,grf = <&grf>;
742 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
743 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
744 clock-names = "iahb", "isfr";
749 #address-cells = <1>;
751 hdmi_in_vopb: endpoint@0 {
753 remote-endpoint = <&vopb_out_hdmi>;
755 hdmi_in_vopl: endpoint@1 {
757 remote-endpoint = <&vopl_out_hdmi>;
763 gic: interrupt-controller@ffc01000 {
764 compatible = "arm,gic-400";
765 interrupt-controller;
766 #interrupt-cells = <3>;
767 #address-cells = <0>;
769 reg = <0xffc01000 0x1000>,
773 interrupts = <GIC_PPI 9 0xf04>;
777 compatible = "rockchip,rk3288-usb-phy";
778 rockchip,grf = <&grf>;
779 #address-cells = <1>;
786 clocks = <&cru SCLK_OTGPHY0>;
787 clock-names = "phyclk";
793 clocks = <&cru SCLK_OTGPHY1>;
794 clock-names = "phyclk";
800 clocks = <&cru SCLK_OTGPHY2>;
801 clock-names = "phyclk";
806 compatible = "rockchip,rk3288-pinctrl";
807 rockchip,grf = <&grf>;
808 rockchip,pmu = <&pmu>;
809 #address-cells = <1>;
813 gpio0: gpio0@ff750000 {
814 compatible = "rockchip,gpio-bank";
815 reg = <0xff750000 0x100>;
816 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
817 clocks = <&cru PCLK_GPIO0>;
822 interrupt-controller;
823 #interrupt-cells = <2>;
826 gpio1: gpio1@ff780000 {
827 compatible = "rockchip,gpio-bank";
828 reg = <0xff780000 0x100>;
829 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
830 clocks = <&cru PCLK_GPIO1>;
835 interrupt-controller;
836 #interrupt-cells = <2>;
839 gpio2: gpio2@ff790000 {
840 compatible = "rockchip,gpio-bank";
841 reg = <0xff790000 0x100>;
842 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
843 clocks = <&cru PCLK_GPIO2>;
848 interrupt-controller;
849 #interrupt-cells = <2>;
852 gpio3: gpio3@ff7a0000 {
853 compatible = "rockchip,gpio-bank";
854 reg = <0xff7a0000 0x100>;
855 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
856 clocks = <&cru PCLK_GPIO3>;
861 interrupt-controller;
862 #interrupt-cells = <2>;
865 gpio4: gpio4@ff7b0000 {
866 compatible = "rockchip,gpio-bank";
867 reg = <0xff7b0000 0x100>;
868 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
869 clocks = <&cru PCLK_GPIO4>;
874 interrupt-controller;
875 #interrupt-cells = <2>;
878 gpio5: gpio5@ff7c0000 {
879 compatible = "rockchip,gpio-bank";
880 reg = <0xff7c0000 0x100>;
881 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
882 clocks = <&cru PCLK_GPIO5>;
887 interrupt-controller;
888 #interrupt-cells = <2>;
891 gpio6: gpio6@ff7d0000 {
892 compatible = "rockchip,gpio-bank";
893 reg = <0xff7d0000 0x100>;
894 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
895 clocks = <&cru PCLK_GPIO6>;
900 interrupt-controller;
901 #interrupt-cells = <2>;
904 gpio7: gpio7@ff7e0000 {
905 compatible = "rockchip,gpio-bank";
906 reg = <0xff7e0000 0x100>;
907 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
908 clocks = <&cru PCLK_GPIO7>;
913 interrupt-controller;
914 #interrupt-cells = <2>;
917 gpio8: gpio8@ff7f0000 {
918 compatible = "rockchip,gpio-bank";
919 reg = <0xff7f0000 0x100>;
920 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&cru PCLK_GPIO8>;
926 interrupt-controller;
927 #interrupt-cells = <2>;
930 pcfg_pull_up: pcfg-pull-up {
934 pcfg_pull_down: pcfg-pull-down {
938 pcfg_pull_none: pcfg-pull-none {
942 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
944 drive-strength = <12>;
948 global_pwroff: global-pwroff {
949 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
952 ddrio_pwroff: ddrio-pwroff {
953 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
956 ddr0_retention: ddr0-retention {
957 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
960 ddr1_retention: ddr1-retention {
961 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
966 i2c0_xfer: i2c0-xfer {
967 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
968 <0 16 RK_FUNC_1 &pcfg_pull_none>;
973 i2c1_xfer: i2c1-xfer {
974 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
975 <8 5 RK_FUNC_1 &pcfg_pull_none>;
980 i2c2_xfer: i2c2-xfer {
981 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
982 <6 10 RK_FUNC_1 &pcfg_pull_none>;
987 i2c3_xfer: i2c3-xfer {
988 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
989 <2 17 RK_FUNC_1 &pcfg_pull_none>;
994 i2c4_xfer: i2c4-xfer {
995 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
996 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1001 i2c5_xfer: i2c5-xfer {
1002 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1003 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1008 i2s0_bus: i2s0-bus {
1009 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1010 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1011 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1012 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1013 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1014 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1019 sdmmc_clk: sdmmc-clk {
1020 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1023 sdmmc_cmd: sdmmc-cmd {
1024 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1027 sdmmc_cd: sdmcc-cd {
1028 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1031 sdmmc_bus1: sdmmc-bus1 {
1032 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1035 sdmmc_bus4: sdmmc-bus4 {
1036 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1037 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1038 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1039 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1044 sdio0_bus1: sdio0-bus1 {
1045 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1048 sdio0_bus4: sdio0-bus4 {
1049 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1050 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1051 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1052 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1055 sdio0_cmd: sdio0-cmd {
1056 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1059 sdio0_clk: sdio0-clk {
1060 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1063 sdio0_cd: sdio0-cd {
1064 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1067 sdio0_wp: sdio0-wp {
1068 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1071 sdio0_pwr: sdio0-pwr {
1072 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1075 sdio0_bkpwr: sdio0-bkpwr {
1076 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1079 sdio0_int: sdio0-int {
1080 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1085 sdio1_bus1: sdio1-bus1 {
1086 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1089 sdio1_bus4: sdio1-bus4 {
1090 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1091 <3 25 4 &pcfg_pull_up>,
1092 <3 26 4 &pcfg_pull_up>,
1093 <3 27 4 &pcfg_pull_up>;
1096 sdio1_cd: sdio1-cd {
1097 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1100 sdio1_wp: sdio1-wp {
1101 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1104 sdio1_bkpwr: sdio1-bkpwr {
1105 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1108 sdio1_int: sdio1-int {
1109 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1112 sdio1_cmd: sdio1-cmd {
1113 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1116 sdio1_clk: sdio1-clk {
1117 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1120 sdio1_pwr: sdio1-pwr {
1121 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1126 emmc_clk: emmc-clk {
1127 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1130 emmc_cmd: emmc-cmd {
1131 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1134 emmc_pwr: emmc-pwr {
1135 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1138 emmc_bus1: emmc-bus1 {
1139 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1142 emmc_bus4: emmc-bus4 {
1143 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1144 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1145 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1146 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1149 emmc_bus8: emmc-bus8 {
1150 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1151 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1152 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1153 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1154 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1155 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1156 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1157 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1162 spi0_clk: spi0-clk {
1163 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1165 spi0_cs0: spi0-cs0 {
1166 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1169 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1172 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1174 spi0_cs1: spi0-cs1 {
1175 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1179 spi1_clk: spi1-clk {
1180 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1182 spi1_cs0: spi1-cs0 {
1183 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1186 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1189 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1194 spi2_cs1: spi2-cs1 {
1195 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1197 spi2_clk: spi2-clk {
1198 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1200 spi2_cs0: spi2-cs0 {
1201 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1204 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1207 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1212 uart0_xfer: uart0-xfer {
1213 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1214 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1217 uart0_cts: uart0-cts {
1218 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
1221 uart0_rts: uart0-rts {
1222 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1227 uart1_xfer: uart1-xfer {
1228 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1229 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1232 uart1_cts: uart1-cts {
1233 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1236 uart1_rts: uart1-rts {
1237 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1242 uart2_xfer: uart2-xfer {
1243 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1244 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1246 /* no rts / cts for uart2 */
1250 uart3_xfer: uart3-xfer {
1251 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1252 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1255 uart3_cts: uart3-cts {
1256 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1259 uart3_rts: uart3-rts {
1260 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1265 uart4_xfer: uart4-xfer {
1266 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1267 <5 13 3 &pcfg_pull_none>;
1270 uart4_cts: uart4-cts {
1271 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1274 uart4_rts: uart4-rts {
1275 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1281 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1286 pwm0_pin: pwm0-pin {
1287 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1292 pwm1_pin: pwm1-pin {
1293 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1298 pwm2_pin: pwm2-pin {
1299 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1304 pwm3_pin: pwm3-pin {
1305 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1310 rgmii_pins: rgmii-pins {
1311 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1312 <3 31 3 &pcfg_pull_none>,
1313 <3 26 3 &pcfg_pull_none>,
1314 <3 27 3 &pcfg_pull_none>,
1315 <3 28 3 &pcfg_pull_none_12ma>,
1316 <3 29 3 &pcfg_pull_none_12ma>,
1317 <3 24 3 &pcfg_pull_none_12ma>,
1318 <3 25 3 &pcfg_pull_none_12ma>,
1319 <4 0 3 &pcfg_pull_none>,
1320 <4 5 3 &pcfg_pull_none>,
1321 <4 6 3 &pcfg_pull_none>,
1322 <4 9 3 &pcfg_pull_none_12ma>,
1323 <4 4 3 &pcfg_pull_none_12ma>,
1324 <4 1 3 &pcfg_pull_none>,
1325 <4 3 3 &pcfg_pull_none>;
1328 rmii_pins: rmii-pins {
1329 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1330 <3 31 3 &pcfg_pull_none>,
1331 <3 28 3 &pcfg_pull_none>,
1332 <3 29 3 &pcfg_pull_none>,
1333 <4 0 3 &pcfg_pull_none>,
1334 <4 5 3 &pcfg_pull_none>,
1335 <4 4 3 &pcfg_pull_none>,
1336 <4 1 3 &pcfg_pull_none>,
1337 <4 2 3 &pcfg_pull_none>,
1338 <4 3 3 &pcfg_pull_none>;