1 #include <dt-bindings/clock/rk_system_status.h>
2 #include <dt-bindings/interrupt-controller/arm-gic.h>
3 #include <dt-bindings/rkfb/rk_fb.h>
4 #include <dt-bindings/rkmipi/mipi_dsi.h>
5 #include <dt-bindings/suspend/rockchip-pm.h>
6 #include <dt-bindings/sensor-dev.h>
8 #include "skeleton.dtsi"
9 #include "rk3288-pinctrl.dtsi"
10 #include "rk3288-clocks.dtsi"
13 compatible = "rockchip,rk3288";
14 rockchip,sram = <&sram>;
15 interrupt-parent = <&gic>;
42 compatible = "arm,cortex-a15";
47 compatible = "arm,cortex-a15";
52 compatible = "arm,cortex-a15";
57 compatible = "arm,cortex-a15";
62 gic: interrupt-controller@ffc01000 {
63 compatible = "arm,cortex-a15-gic";
65 #interrupt-cells = <3>;
67 reg = <0xffc01000 0x1000>,
72 compatible = "arm,cortex-a12-pmu";
73 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
74 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
75 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
79 cpu_axi_bus: cpu_axi_bus {
80 compatible = "rockchip,cpu_axi_bus";
91 reg = <0xffa80000 0x20>;
94 reg = <0xffa80080 0x20>;
97 reg = <0xffa80100 0x20>;
101 reg = <0xffa90000 0x20>;
104 reg = <0xffa90080 0x20>;
107 reg = <0xffa90100 0x20>;
110 reg = <0xffa90180 0x20>;
113 reg = <0xffa90200 0x20>;
117 reg = <0xffaa0000 0x20>;
120 reg = <0xffaa0080 0x20>;
124 reg = <0xffab0000 0x20>;
128 reg = <0xffad0000 0x20>;
129 rockchip,priority = <2 2>;
132 reg = <0xffad0100 0x20>;
133 rockchip,priority = <2 2>;
136 reg = <0xffad0180 0x20>;
139 reg = <0xffad0400 0x20>;
140 rockchip,priority = <2 2>;
143 reg = <0xffad0480 0x20>;
146 reg = <0xffad0500 0x20>;
149 reg = <0xffad0800 0x20>;
152 reg = <0xffad0880 0x20>;
155 reg = <0xffad0900 0x20>;
159 reg = <0xffae0000 0x20>;
163 reg = <0xffaf0000 0x20>;
166 reg = <0xffaf0080 0x20>;
171 #address-cells = <1>;
176 reg = <0xffac0000 0x40>;
177 rockchip,read-latency = <0x34>;
180 reg = <0xffac0080 0x40>;
181 rockchip,read-latency = <0x34>;
186 sram: sram@ff710000 {
187 compatible = "mmio-sram";
188 reg = <0xff710000 0x8000>; /* 32k */
193 compatible = "arm,armv7-timer";
194 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
195 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
196 clock-frequency = <24000000>;
200 compatible = "rockchip,timer";
201 reg = <0xff810000 0x20>;
202 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
203 rockchip,broadcast = <1>;
206 watchdog: wdt@2004c000 {
207 compatible = "rockchip,watch dog";
208 reg = <0xff800000 0x100>;
209 clocks = <&pclk_pd_alive>;
210 clock-names = "pclk_wdt";
211 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
213 rockchip,timeout = <60>;
214 rockchip,atboot = <1>;
215 rockchip,debug = <0>;
220 #address-cells = <1>;
222 compatible = "arm,amba-bus";
223 interrupt-parent = <&gic>;
226 pdma0: pdma@ffb20000 {
227 compatible = "arm,pl330", "arm,primecell";
228 reg = <0xffb20000 0x4000>;
229 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
230 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
234 pdma1: pdma@ff250000 {
235 compatible = "arm,pl330", "arm,primecell";
236 reg = <0xff250000 0x4000>;
237 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
238 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
243 reset: reset@ff7601b8{
244 compatible = "rockchip,reset";
245 reg = <0xff7601b8 0x30>;
246 rockchip,reset-flag = <ROCKCHIP_RESET_HIWORD_MASK>;
250 nandc0: nandc@0xff400000 {
251 compatible = "rockchip,rk-nandc";
252 reg = <0xff400000 0x4000>;
253 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&clk_nandc0>, <&clk_gates5 5>, <&clk_gates7 14>;
256 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
259 nandc1: nandc@0xff410000 {
260 compatible = "rockchip,rk-nandc";
261 reg = <0xff410000 0x4000>;
262 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&clk_nandc1>, <&clk_gates5 6>, <&clk_gates7 15>;
265 clock-names = "clk_nandc", "g_clk_nandc", "hclk_nandc";
268 nandc0reg: nandc0@0xff400000 {
269 compatible = "rockchip,rk-nandc";
270 reg = <0xff400000 0x4000>;
273 emmc: rksdmmc@ff0f0000 {
274 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
275 reg = <0xff0f0000 0x4000>;
276 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
277 #address-cells = <1>;
279 //pinctrl-names = "default",,"suspend";
280 //pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_cd &sd0_wp &sd0_pwr &sd0_bus1 &sd0_bus4>;
281 clocks = <&clk_emmc>, <&clk_gates8 6>;
282 clock-names = "clk_mmc", "hclk_mmc";
284 fifo-depth = <0x100>;
288 sdmmc: rksdmmc@ff0c0000 {
289 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
290 reg = <0xff0c0000 0x4000>;
291 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
292 #address-cells = <1>;
294 pinctrl-names = "default", "idle";
295 pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>;
296 pinctrl-1 = <&sdmmc0_gpio>;
297 cd-gpios = <&gpio6 GPIO_C6 GPIO_ACTIVE_HIGH>;/*CD GPIO*/
298 clocks = <&clk_sdmmc>, <&clk_gates8 3>;
299 clock-names = "clk_mmc", "hclk_mmc";
301 fifo-depth = <0x100>;
305 sdio: rksdmmc@ff0d0000 {
306 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
307 reg = <0xff0d0000 0x4000>;
308 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
309 #address-cells = <1>;
311 pinctrl-names = "default","idle";
312 pinctrl-0 = <&sdio0_clk &sdio0_cmd &sdio0_wrprt &sdio0_pwr &sdio0_bkpwr
313 &sdio0_intn &sdio0_bus4>;
314 pinctrl-1 = <&sdio0_gpio>;
315 clocks = <&clk_sdio0>, <&clk_gates8 4>;
316 clock-names = "clk_mmc", "hclk_mmc";
318 fifo-depth = <0x100>;
322 sdio1: rksdmmc@ff0e0000 {
323 compatible = "rockchip,rk_mmc", "rockchip,rk32xx-sdmmc";
324 reg = <0xff0e0000 0x4000>;
325 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
326 #address-cells = <1>;
328 //pinctrl-names = "default","suspend";
329 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
330 /*gate8_0 --hclk_sdmmc_ahb_arbi_gate_en, gate13_2 --clk_sdio1_src_gate_en*/
331 clocks = <&clk_sdio1>, <&clk_gates8 5>;
332 clock-names = "clk_mmc", "hclk_mmc";
334 fifo-depth = <0x100>;
340 compatible = "rockchip,rockchip-spi";
341 reg = <0xff110000 0x1000>;
342 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
343 #address-cells = <1>;
345 pinctrl-names = "default";
346 pinctrl-0 = <&spi0_txd &spi0_rxd &spi0_clk &spi0_cs0 &spi0_cs1>;
347 rockchip,spi-src-clk = <0>;
349 clocks =<&clk_spi0>, <&clk_gates6 4>;
350 clock-names = "spi","pclk_spi0";
351 //dmas = <&pdma1 11>, <&pdma1 12>;
353 //dma-names = "tx", "rx";
358 compatible = "rockchip,rockchip-spi";
359 reg = <0xff120000 0x1000>;
360 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
361 #address-cells = <1>;
363 pinctrl-names = "default";
364 pinctrl-0 = <&spi1_txd &spi1_rxd &spi1_clk &spi1_cs0>;
365 rockchip,spi-src-clk = <1>;
367 clocks = <&clk_spi1>, <&clk_gates6 5>;
368 clock-names = "spi","pclk_spi1";
369 //dmas = <&pdma1 13>, <&pdma1 14>;
371 //dma-names = "tx", "rx";
376 compatible = "rockchip,rockchip-spi";
377 reg = <0xff130000 0x1000>;
378 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
379 #address-cells = <1>;
381 pinctrl-names = "default";
382 pinctrl-0 = <&spi2_txd &spi2_rxd &spi2_clk &spi2_cs0 &spi2_cs1>;
383 rockchip,spi-src-clk = <2>;
385 clocks = <&clk_spi2>, <&clk_gates6 6>;
386 clock-names = "spi","pclk_spi2";
387 //dmas = <&pdma1 15>, <&pdma1 16>;
389 //dma-names = "tx", "rx";
393 uart_bt: serial@ff180000 {
394 compatible = "rockchip,serial";
395 reg = <0xff180000 0x100>;
396 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
397 clock-frequency = <24000000>;
398 clocks = <&clk_uart0>, <&clk_gates6 8>;
399 clock-names = "sclk_uart", "pclk_uart";
402 dmas = <&pdma1 1>, <&pdma1 2>;
404 pinctrl-names = "default";
405 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
409 uart_bb: serial@ff190000 {
410 compatible = "rockchip,serial";
411 reg = <0xff190000 0x100>;
412 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
413 clock-frequency = <24000000>;
414 clocks = <&clk_uart1>, <&clk_gates6 9>;
415 clock-names = "sclk_uart", "pclk_uart";
418 dmas = <&pdma1 3>, <&pdma1 4>;
420 pinctrl-names = "default";
421 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
425 uart_dbg: serial@ff690000 {
426 compatible = "rockchip,serial";
427 reg = <0xff690000 0x100>;
428 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
429 clock-frequency = <24000000>;
430 clocks = <&clk_uart2>, <&clk_gates11 9>;
431 clock-names = "sclk_uart", "pclk_uart";
434 dmas = <&pdma0 4>, <&pdma0 5>;
436 pinctrl-names = "default";
437 pinctrl-0 = <&uart2_xfer>;
441 uart_gps: serial@ff1b0000 {
442 compatible = "rockchip,serial";
443 reg = <0xff1b0000 0x100>;
444 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
445 clock-frequency = <24000000>;
446 clocks = <&clk_uart3>, <&clk_gates6 11>;
447 clock-names = "sclk_uart", "pclk_uart";
448 current-speed = <115200>;
451 dmas = <&pdma1 7>, <&pdma1 8>;
453 pinctrl-names = "default";
454 pinctrl-0 = <&uart3_xfer &uart3_cts &uart3_rts>;
458 uart_exp: serial@ff1c0000 {
459 compatible = "rockchip,serial";
460 reg = <0xff1c0000 0x100>;
461 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
462 clock-frequency = <24000000>;
463 clocks = <&clk_uart4>, <&clk_gates6 12>;
464 clock-names = "sclk_uart", "pclk_uart";
467 dmas = <&pdma1 9>, <&pdma1 10>;
469 pinctrl-names = "default";
470 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
475 compatible = "rockchip,fiq-debugger";
476 rockchip,serial-id = <2>;
477 rockchip,signal-irq = <106>;
478 rockchip,wake-irq = <0>;
482 rockchip_clocks_init: clocks-init{
483 compatible = "rockchip,clocks-init";
484 rockchip,clocks-init-parent =
485 <&clk_core &clk_apll>, <&aclk_bus_src &clk_gpll>,
486 <&aclk_peri &clk_gpll>, <&uart_pll_mux &clk_gpll>,
487 <&clk_i2s_pll &clk_gpll>, <&clk_spdif_pll &clk_gpll>,
488 <&usbphy_480m &otgphy2_480m>;
489 rockchip,clocks-init-rate =
490 <&clk_core 792000000>, <&clk_gpll 297000000>,
491 /*<&clk_cpll 47000000>,*/ <&clk_npll 1250000000>,
492 <&aclk_bus_src 300000000>, <&aclk_bus 300000000>,
493 <&hclk_bus 150000000>, <&pclk_bus 75000000>,
494 <&clk_crypto 150000000>, <&aclk_peri 300000000>,
495 <&hclk_peri 150000000>, <&pclk_peri 75000000>,
496 <&clk_gpu 200000000>, <&aclk_vio0 300000000>,
497 <&aclk_vio1 300000000>, <&hclk_vio 75000000>,
498 <&pclk_pd_alive 100000000>, <&pclk_pd_pmu 100000000>,
499 <&aclk_hevc 400000000>, <&hclk_hevc 200000000>,
500 <&clk_hevc_cabac 300000000>, <&clk_hevc_core 300000000>,
501 <&aclk_rga 300000000>, <&clk_rga 300000000>,
502 <&clk_vepu 300000000>, <&clk_vdpu 300000000>,
503 <&clk_edp 200000000>, <&clk_isp 200000000>,
504 <&clk_isp_jpe 400000000>, <&clk_tsp 80000000>,
505 <&clk_tspout 80000000>, <&clk_mac 125000000>;
506 rockchip,clocks-uboot-has-init =
511 compatible = "rockchip,clocks-enable";
514 <&clk_gates0 2>, <&clk_core0>,
515 <&clk_core1>, <&clk_core2>,
516 <&clk_core3>, <&clk_l2ram>,
517 <&aclk_core_m0>, <&aclk_core_mp>,
518 <&atclk_core>, <&pclk_dbg_src>,
519 <&clk_gates12 9>, <&clk_gates12 10>,
523 <&aclk_bus>, <&clk_gates0 3>,
524 <&hclk_bus>, <&pclk_bus>,
525 <&clk_gates13 8>, <&clk_crypto>,
529 <&clk_gates1 0>, <&clk_gates1 1>,
530 <&clk_gates1 2>, <&clk_gates1 3>,
531 <&clk_gates1 4>, <&clk_gates1 5>,
533 <&pclk_pd_alive>, <&pclk_pd_pmu>,
536 <&aclk_peri>, <&hclk_peri>,
540 /*<&clk_gates4 14>,*/
543 <&clk_gates10 5>,/*aclk_intmem0*/
544 <&clk_gates10 6>,/*aclk_intmem1*/
545 <&clk_gates10 7>,/*aclk_intmem2*/
546 <&clk_gates10 12>,/*aclk_dma1*/
547 <&clk_gates10 13>,/*aclk_strc_sys*/
548 <&clk_gates10 4>,/*aclk_intmem*/
549 <&clk_gates11 6>,/*aclk_crypto*/
550 <&clk_gates11 8>,/*aclk_ccp*/
553 <&clk_gates11 7>,/*hclk_crypto*/
554 <&clk_gates10 9>,/*hclk_rom*/
557 <&clk_gates10 1>,/*pclk_timer*/
558 <&clk_gates10 9>,/*rom*/
559 <&clk_gates10 13>,/*aclk strc*/
561 <&clk_gates12 8>,/*aclk strc*/
564 <&clk_gates6 2>,/*aclk_peri_axi_matrix*/
565 <&clk_gates6 3>,/*aclk_dmac2*/
566 <&clk_gates7 11>,/*aclk_peri_niu*/
567 <&clk_gates8 12>,/*aclk_peri_mmu*/
570 <&clk_gates6 0>,/*hclk_peri_matrix*/
571 <&clk_gates7 10>,/*hclk_peri_ahb_arbi*/
572 <&clk_gates7 12>,/*hclk_emem_peri*/
573 <&clk_gates7 13>,/*hclk_mem_peri*/
576 <&clk_gates6 1>,/*pclk_peri_axi_matrix*/
579 <&clk_gates14 11>,/*pclk_grf*/
580 <&clk_gates14 12>,/*pclk_alive_niu*/
583 <&clk_gates17 0>,/*pclk_pmu*/
584 <&clk_gates17 1>,/*pclk_intmem1*/
585 <&clk_gates17 2>,/*pclk_pmu_niu*/
586 <&clk_gates17 3>,/*pclk_sgrf*/
589 <&clk_gates15 9>,/*hclk_vio_ahb_arbi*/
590 <&clk_gates15 10>,/*hclk_vio_niu*/
591 <&clk_gates16 10>,/*hclk_vio2_h2p*/
592 <&clk_gates16 11>,/*pclk_vio2_h2p*/
595 <&clk_gates15 11>,/*aclk_vio0_niu*/
598 <&clk_gates15 12>,/*aclk_vio1_niu*/
601 //<&clk_gates5 12>,/*hdmi_hdcp_clk*/
604 <&clk_gates11 9>,/*pclk_uart2*/
611 compatible = "rockchip,rk30-i2c";
612 reg = <0xff650000 0x1000>;
613 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
614 #address-cells = <1>;
616 pinctrl-names = "default", "gpio";
617 pinctrl-0 = <&i2c0_sda &i2c0_scl>;
618 pinctrl-1 = <&i2c0_gpio>;
619 gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
620 clocks = <&clk_gates10 2>;
621 rockchip,check-idle = <1>;
626 compatible = "rockchip,rk30-i2c";
627 reg = <0xff140000 0x1000>;
628 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
629 #address-cells = <1>;
631 pinctrl-names = "default", "gpio";
632 pinctrl-0 = <&i2c1_sda &i2c1_scl>;
633 pinctrl-1 = <&i2c1_gpio>;
634 gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
635 clocks = <&clk_gates10 3>;
636 rockchip,check-idle = <1>;
641 compatible = "rockchip,rk30-i2c";
642 reg = <0xff660000 0x1000>;
643 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
644 #address-cells = <1>;
646 pinctrl-names = "default", "gpio";
647 pinctrl-0 = <&i2c2_sda &i2c2_scl>;
648 pinctrl-1 = <&i2c2_gpio>;
649 gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
650 clocks = <&clk_gates6 13>;
651 rockchip,check-idle = <1>;
656 compatible = "rockchip,rk30-i2c";
657 reg = <0xff150000 0x1000>;
658 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
659 #address-cells = <1>;
661 pinctrl-names = "default", "gpio";
662 pinctrl-0 = <&i2c3_sda &i2c3_scl>;
663 pinctrl-1 = <&i2c3_gpio>;
664 gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
665 clocks = <&clk_gates6 14>;
666 rockchip,check-idle = <1>;
671 compatible = "rockchip,rk30-i2c";
672 reg = <0xff160000 0x1000>;
673 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
674 #address-cells = <1>;
676 pinctrl-names = "default", "gpio";
677 pinctrl-0 = <&i2c4_sda &i2c4_scl>;
678 pinctrl-1 = <&i2c4_gpio>;
679 gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
680 clocks = <&clk_gates6 15>;
681 rockchip,check-idle = <1>;
686 compatible = "rockchip,rk30-i2c";
687 reg = <0xff170000 0x1000>;
688 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
689 #address-cells = <1>;
691 pinctrl-names = "default", "gpio";
692 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
693 pinctrl-1 = <&i2c5_gpio>;
694 gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
695 clocks = <&clk_gates7 0>;
696 rockchip,check-idle = <1>;
701 compatible = "rockchip,rk-fb";
702 rockchip,disp-mode = <DUAL>;
705 rk_screen: rk_screen{
706 compatible = "rockchip,screen";
709 dsihost0: mipi@ff960000{
710 compatible = "rockchip,rk32-dsi";
712 reg = <0xff960000 0x4000>;
713 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
714 clocks = <&clk_gates5 15>, <&clk_gates16 4> , <&pd_mipidsi>;
715 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
719 dsihost1: mipi@ff964000{
720 compatible = "rockchip,rk32-dsi";
722 reg = <0xff964000 0x4000>;
723 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
724 clocks = <&clk_gates5 15>, <&clk_gates16 5>, <&pd_mipidsi>;
725 clock-names = "clk_mipi_24m", "pclk_mipi_dsi", "pd_mipi_dsi";
729 lvds: lvds@ff96c000 {
730 compatible = "rockchip,rk32-lvds";
731 reg = <0xff96c000 0x4000>;
732 clocks = <&clk_gates16 7>;
733 clock-names = "pclk_lvds";
737 compatible = "rockchip,rk32-edp";
738 reg = <0xff970000 0x4000>;
739 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
740 clocks = <&clk_edp>, <&clk_edp_24m>, <&clk_gates16 8>;
741 clock-names = "clk_edp", "clk_edp_24m", "pclk_edp";
744 hdmi: hdmi@ff980000 {
745 compatible = "rockchip,rk3288-hdmi";
746 reg = <0xff980000 0x20000>;
747 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
748 pinctrl-names = "default", "sleep";
749 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
750 pinctrl-1 = <&i2c5_gpio>;
751 clocks = <&clk_gates16 9>, <&clk_gates5 12>;
752 clock-names = "pclk_hdmi", "hdcp_clk_hdmi";
756 lcdc0: lcdc@ff930000 {
757 compatible = "rockchip,rk3288-lcdc";
758 rockchip,prop = <PRMRY>;
759 rockchip,pwr18 = <0>;
760 rockchip,iommu-enabled = <0>;
761 reg = <0xff930000 0x10000>;
762 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
763 pinctrl-names = "default", "gpio";
764 pinctrl-0 = <&lcdc0_lcdc>;
765 pinctrl-1 = <&lcdc0_gpio>;
767 clocks = <&clk_gates15 5>, <&dclk_lcdc0>, <&clk_gates15 6>, <&pd_vop0>;
768 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
771 lcdc1: lcdc@ff940000 {
772 compatible = "rockchip,rk3288-lcdc";
773 rockchip,prop = <EXTEND>;
774 rockchip,pwr18 = <0>;
775 rockchip,iommu-enabled = <0>;
776 reg = <0xff940000 0x10000>;
777 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
779 clocks = <&clk_gates15 7>, <&dclk_lcdc1>, <&clk_gates15 8>, <&pd_vop1>;
780 clock-names = "aclk_lcdc", "dclk_lcdc", "hclk_lcdc", "pd_lcdc";
784 compatible = "rockchip,saradc";
785 reg = <0xff100000 0x100>;
786 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
787 #io-channel-cells = <1>;
789 rockchip,adc-vref = <1800>;
790 clock-frequency = <1000000>;
791 clocks = <&clk_saradc>, <&clk_gates7 1>;
792 clock-names = "saradc", "pclk_saradc";
797 compatible = "rockchip,rk3288-rga2";
798 reg = <0xff920000 0x1000>;
799 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
800 clocks = <&clk_gates15 1>, <&aclk_rga>, <&clk_rga>;
801 clock-names = "hclk_rga", "aclk_rga", "clk_rga";
804 i2s: rockchip-i2s@0xff890000 {
805 compatible = "rockchip-i2s";
806 reg = <0xff890000 0x10000>;
808 clocks = <&clk_i2s>, <&clk_i2s_out>, <&clk_gates10 8>;
809 clock-names = "i2s_clk","i2s_mclk", "i2s_hclk";
810 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
811 dmas = <&pdma0 0>, <&pdma0 1>;
813 dma-names = "tx", "rx";
814 pinctrl-names = "default", "sleep";
815 pinctrl-0 = <&i2s_mclk &i2s_sclk &i2s_lrckrx &i2s_lrcktx &i2s_sdi &i2s_sdo0 &i2s_sdo1 &i2s_sdo2 &i2s_sdo3>;
816 pinctrl-1 = <&i2s_gpio>;
819 spdif: rockchip-spdif@0xff8b0000 {
820 compatible = "rockchip-spdif";
821 reg = <0xff8b0000 0x10000>; //8channel
822 //reg = <ff880000 0x10000>;//2channel
823 clocks = <&clk_spdif>, <&clk_spdif_8ch>,<&clk_gates10 11>;
824 clock-names = "spdif_mclk","spdif_8ch_mclk","spdif_hclk";
825 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
827 //dmas = <&pdma0 2>; //2channel
830 pinctrl-names = "default";
831 pinctrl-0 = <&spdif_tx>;
834 vop1pwm: pwm@ff9401a0 {
835 compatible = "rockchip,vop-pwm";
836 reg = <0xff9401a0 0x10>;
838 pinctrl-names = "default";
839 pinctrl-0 = <&vop1_pwm_pin>;
840 clocks = <&clk_gates13 11>;
841 clock-names = "pclk_pwm";
845 vop0pwm: pwm@ff9301a0 {
846 compatible = "rockchip,vop-pwm";
847 reg = <0xff9301a0 0x10>;
849 pinctrl-names = "default";
850 pinctrl-0 = <&vop0_pwm_pin>;
851 clocks = <&clk_gates13 10>;
852 clock-names = "pclk_pwm";
857 compatible = "rockchip,rk-pwm";
858 reg = <0xff680000 0x10>;
860 pinctrl-names = "default";
861 pinctrl-0 = <&pwm0_pin>;
862 clocks = <&clk_gates11 11>;
863 clock-names = "pclk_pwm";
868 compatible = "rockchip,rk-pwm";
869 reg = <0xff680010 0x10>;
871 pinctrl-names = "default";
872 pinctrl-0 = <&pwm1_pin>;
873 clocks = <&clk_gates11 11>;
874 clock-names = "pclk_pwm";
879 compatible = "rockchip,rk-pwm";
880 reg = <0xff680020 0x10>;
882 pinctrl-names = "default";
883 pinctrl-0 = <&pwm2_pin>;
884 clocks = <&clk_gates11 11>;
885 clock-names = "pclk_pwm";
890 compatible = "rockchip,rk-pwm";
891 reg = <0xff680030 0x10>;
893 pinctrl-names = "default";
894 pinctrl-0 = <&pwm3_pin>;
895 clocks = <&clk_gates11 11>;
896 clock-names = "pclk_pwm";
901 temp-limit-enable = <1>;
905 regulator_name = "vdd_arm";
906 suspend_volt = <1000>; //mV
908 clk_core_dvfs_table: clk_core {
917 normal-temp-limit = <
918 /*delta-temp delta-freq*/
924 performance-temp-limit = <
940 regulator_name = "vdd_logic";
941 suspend_volt = <1000>; //mV
943 clk_ddr_dvfs_table: clk_ddr {
955 aclk_vio1_dvfs_table: aclk_vio1 {
967 regulator_name = "vdd_gpu";
968 suspend_volt = <1000>; //mV
970 clk_gpu_dvfs_table: clk_gpu {
990 compatible = "rockchip,ion";
991 #address-cells = <1>;
994 ion_cma: rockchip,ion-heap@1 { /* CMA HEAP */
995 compatible = "rockchip,ion-reserve";
996 rockchip,ion_heap = <1>;
997 reg = <0x00000000 0x20000000>; /* 512MB */
999 rockchip,ion-heap@3 { /* VMALLOC HEAP */
1000 rockchip,ion_heap = <3>;
1004 vpu: vpu_service@ff9a0000 {
1005 compatible = "vpu_service";
1006 iommu_enabled = <1>;
1007 reg = <0xff9a0000 0x800>;
1008 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1009 interrupt-names = "irq_enc", "irq_dec";
1010 clocks = <&clk_vdpu>, <&hclk_vdpu>;
1011 clock-names = "aclk_vcodec", "hclk_vcodec";
1012 name = "vpu_service";
1013 //status = "disabled";
1016 hevc: hevc_service@ff9c0000 {
1017 compatible = "rockchip,hevc_service";
1018 iommu_enabled = <1>;
1019 reg = <0xff9c0000 0x800>;
1020 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1021 interrupt-names = "irq_dec";
1022 clocks = <&aclk_hevc>, <&hclk_hevc>, <&clk_hevc_core>, <&clk_hevc_cabac>;
1023 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", "clk_cabac";
1024 name = "hevc_service";
1025 //status = "disabled";
1029 compatible = "rockchip,iep";
1030 iommu_enabled = <1>;
1031 reg = <0xff900000 0x800>;
1032 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1033 clocks = <&clk_gates15 2>, <&clk_gates15 3>;
1034 clock-names = "aclk_iep", "hclk_iep";
1038 dwc_control_usb: dwc-control-usb@ff770284 {
1039 compatible = "rockchip,rk3288-dwc-control-usb";
1040 reg = <0xff770284 0x04>, <0xff770288 0x04>,
1041 <0xff7702cc 0x04>, <0xff7702d4 0x04>,
1042 <0xff770320 0x14>, <0xff770334 0x14>,
1043 <0xff770348 0x10>, <0xff770358 0x08>,
1045 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
1046 "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
1047 "GRF_UOC0_BASE", "GRF_UOC1_BASE",
1048 "GRF_UOC2_BASE", "GRF_UOC3_BASE",
1050 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1051 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1052 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1053 interrupt-names = "otg_id", "otg_bvalid",
1054 "otg_linestate", "host0_linestate",
1056 clocks = <&clk_gates7 9>, <&usbphy_480m>,
1057 <&otgphy1_480m>, <&otgphy2_480m>;
1058 clock-names = "hclk_usb_peri", "usbphy_480m",
1059 "usbphy1_480m", "usbphy2_480m";
1062 compatible = "synopsys,phy";
1063 /* offset bit mask */
1064 rk_usb,bvalid = <0x288 14 1>;
1065 rk_usb,iddig = <0x288 17 1>;
1066 rk_usb,dcdenb = <0x328 14 1>;
1067 rk_usb,vdatsrcenb = <0x328 7 1>;
1068 rk_usb,vdatdetenb = <0x328 6 1>;
1069 rk_usb,chrgsel = <0x328 5 1>;
1070 rk_usb,chgdet = <0x2cc 23 1>;
1071 rk_usb,fsvminus = <0x2cc 25 1>;
1072 rk_usb,fsvplus = <0x2cc 24 1>;
1076 usb0: usb@ff580000 {
1077 compatible = "rockchip,rk3288_usb20_otg";
1078 reg = <0xff580000 0x40000>;
1079 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1080 clocks = <&clk_gates13 4>, <&clk_gates7 4>;
1081 clock-names = "clk_usbphy0", "hclk_usb0";
1082 resets = <&reset RK3288_SOFT_RST_USBOTG_H>, <&reset RK3288_SOFT_RST_USBOTGPHY>,
1083 <&reset RK3288_SOFT_RST_USBOTGC>;
1084 reset-names = "otg_ahb", "otg_phy", "otg_controller";
1085 /*0 - Normal, 1 - Force Host, 2 - Force Device*/
1086 rockchip,usb-mode = <0>;
1089 usb1: usb@ff540000 {
1090 compatible = "rockchip,rk3288_usb20_host";
1091 reg = <0xff540000 0x40000>;
1092 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1093 clocks = <&clk_gates13 6>, <&clk_gates7 7>,
1095 clock-names = "clk_usbphy1", "hclk_usb1",
1097 resets = <&reset RK3288_SOFT_RST_USBHOST1_H>, <&reset RK3288_SOFT_RST_USBHOST1PHY>,
1098 <&reset RK3288_SOFT_RST_USBHOST1C>;
1099 reset-names = "host1_ahb", "host1_phy", "host1_controller";
1102 usb2: usb@ff500000 {
1103 compatible = "rockchip,rk3288_rk_ehci_host";
1104 reg = <0xff500000 0x20000>;
1105 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1106 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1107 clock-names = "clk_usbphy2", "hclk_usb2";
1108 resets = <&reset RK3288_SOFT_RST_USBHOST0_H>, <&reset RK3288_SOFT_RST_USBHOST0PHY>,
1109 <&reset RK3288_SOFT_RST_USBHOST0C>, <&reset RK3288_SOFT_RST_USB_HOST0>;
1110 reset-names = "ehci_ahb", "ehci_phy", "ehci_controller", "ehci";
1113 usb3: usb@ff520000 {
1114 compatible = "rockchip,rk3288_rk_ohci_host";
1115 reg = <0xff520000 0x20000>;
1116 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1117 clocks = <&clk_gates13 5>, <&clk_gates7 6>;
1118 clock-names = "clk_usbphy3", "hclk_usb3";
1121 hsic: hsic@ff5c0000 {
1122 compatible = "rockchip,rk3288_rk_hsic_host";
1123 reg = <0xff5c0000 0x40000>;
1124 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1125 clocks = <&hsicphy_480m>, <&clk_gates7 8>,
1126 <&hsicphy_12m>, <&usbphy_480m>,
1127 <&otgphy1_480m>, <&otgphy2_480m>;
1128 clock-names = "hsicphy_480m", "hclk_hsic",
1129 "hsicphy_12m", "usbphy_480m",
1130 "hsic_usbphy1", "hsic_usbphy2";
1131 resets = <&reset RK3288_SOFT_RST_HSIC>, <&reset RK3288_SOFT_RST_HSIC_AUX>,
1132 <&reset RK3288_SOFT_RST_HSICPHY>;
1133 reset-names = "hsic_ahb", "hsic_aux", "hsic_phy";
1136 gmac: eth@ff290000 {
1137 compatible = "rockchip,rk3288-gmac";
1138 reg = <0xff290000 0x10000>;
1139 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; /*irq=59*/
1140 interrupt-names = "macirq";
1141 clocks = <&clk_mac>, <&clk_gates5 0>,
1142 <&clk_gates5 1>, <&clk_gates5 2>,
1143 <&clk_gates5 3>, <&clk_gates8 0>,
1145 clock-names = "clk_mac", "mac_clk_rx",
1146 "mac_clk_tx", "clk_mac_ref",
1147 "clk_mac_refout", "aclk_mac",
1150 pinctrl-names = "default";
1151 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
1155 compatible = "arm,malit764",
1159 reg = <0xffa30000 0x10000>;
1160 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1161 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1162 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1163 interrupt-names = "JOB", "MMU", "GPU";
1168 compatible = "rockchip,iep_mmu";
1169 reg = <0xff900800 0x100>;
1170 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1171 interrupt-names = "iep_mmu";
1176 compatible = "rockchip,vip_mmu";
1177 reg = <0xff950800 0x100>;
1178 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1179 interrupt-names = "vip_mmu";
1184 compatible = "rockchip,vopb_mmu";
1185 reg = <0xff930300 0x100>;
1186 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1187 interrupt-names = "vopb_mmu";
1192 compatible = "rockchip,vopl_mmu";
1193 reg = <0xff940300 0x100>;
1194 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1195 interrupt-names = "vopl_mmu";
1200 compatible = "rockchip,hevc_mmu";
1201 reg = <0xff9c0440 0x40>,
1203 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1204 interrupt-names = "hevc_mmu";
1209 compatible = "rockchip,vpu_mmu";
1210 reg = <0xff9a0800 0x100>;
1211 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1212 interrupt-names = "vpu_mmu";
1216 dbgname = "isp_mmu";
1217 compatible = "rockchip,isp_mmu";
1218 reg = <0xff914000 0x100>,
1220 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1221 interrupt-names = "isp_mmu";
1225 rockchip,ctrbits = <
1231 // |RKPM_CTR_SYSCLK_DIV
1232 // |RKPM_CTR_IDLEAUTO_MD
1233 // |RKPM_CTR_ARMOFF_LPMD
1234 |RKPM_CTR_ARMOFF_LOGDP_LPMD
1237 rockchip,pmic-suspend_gpios = <
1238 RKPM_PINGPIO_BITS_OUTPUT(GPIO7_A1,RKPM_GPIO_OUT_H)
1240 rockchip,pmic-resume_gpios = <
1241 RKPM_PINGPIO_BITS_FUN(PWM1,RKPM_GPIO_PULL_DN)
1247 compatible = "rockchip,isp";
1248 reg = <0xff910000 0x10000>;
1249 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1250 clocks = <&clk_gates16 2>, <&clk_gates16 1>, <&clk_isp>, <&clk_isp_jpe>, <&clkin_isp>, <&clk_cif_out>, <&clk_gates5 15>, <&clk_cif_pll>, <&pd_isp>, <&clk_gates16 6>;
1251 clock-names = "aclk_isp", "hclk_isp", "clk_isp", "clk_isp_jpe", "pclkin_isp", "clk_cif_out", "clk_mipi_24m", "clk_cif_pll", "pd_isp", "hclk_mipiphy1";
1252 pinctrl-names = "default", "isp_dvp8bit2", "isp_dvp10bit", "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl", "isp_mipi_fl_prefl","isp_flash_as_gpio","isp_flash_as_trigger_out";
1253 pinctrl-0 = <&isp_mipi>;
1254 pinctrl-1 = <&isp_mipi &isp_dvp_d2d9>;
1255 pinctrl-2 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1>;
1256 pinctrl-3 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1 &isp_dvp_d10d11>;
1257 pinctrl-4 = <&isp_mipi &isp_dvp_d0d7>;
1258 pinctrl-5 = <&isp_mipi>;
1259 pinctrl-6 = <&isp_mipi &isp_prelight>;
1260 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1261 pinctrl-8 = <&isp_flash_trigger>;
1262 rockchip,isp,mipiphy = <2>;
1263 rockchip,isp,cifphy = <1>;
1264 rockchip,isp,mipiphy1,reg = <0xff968000 0x4000>;
1265 rockchip,gpios = <&gpio7 GPIO_B5 GPIO_ACTIVE_HIGH>;
1266 rockchip,isp,iommu_enable = <0>;
1270 tsadc: tsadc@ff280000 {
1271 compatible = "rockchip,tsadc";
1272 reg = <0xff280000 0x100>;
1273 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1274 #io-channel-cells = <1>;
1276 clock-frequency = <10000>;
1277 clocks = <&clk_tsadc>, <&clk_gates7 2>;
1278 clock-names = "tsadc", "pclk_tsadc";
1279 pinctrl-names = "default", "tsadc_int";
1280 pinctrl-0 = <&tsadc_gpio>;
1281 pinctrl-1 = <&tsadc_int>;
1282 tsadc-ht-temp = <120>;
1283 tsadc-ht-reset-cru = <1>;
1284 tsadc-ht-pull-gpio = <0>;
1288 lcdc_vdd_domain: lcdc-vdd-domain {
1289 compatible = "rockchip,io_vol_domain";
1290 pinctrl-names = "default", "1.8V", "3.3V";
1291 pinctrl-0 = <&lcdc_vcc>;
1292 pinctrl-1 = <&lcdc_vcc_18>;
1293 pinctrl-2 = <&lcdc_vcc_33>;
1296 dpio_vdd_domain: dpio-vdd-domain {
1297 compatible = "rockchip,io_vol_domain";
1298 pinctrl-names = "default", "1.8V", "3.3V";
1299 pinctrl-0 = <&dvp_vcc>;
1300 pinctrl-1 = <&dvp_vcc_18>;
1301 pinctrl-2 = <&dvp_vcc_33>;
1304 flash0_vdd_domain: flash0-vdd-domain {
1305 compatible = "rockchip,io_vol_domain";
1306 pinctrl-names = "default", "1.8V", "3.3V";
1307 pinctrl-0 = <&flash0_vcc>;
1308 pinctrl-1 = <&flash0_vcc_18>;
1309 pinctrl-2 = <&flash0_vcc_33>;
1312 flash1_vdd_domain: flash1-vdd-domain {
1313 compatible = "rockchip,io_vol_domain";
1314 pinctrl-names = "default", "1.8V", "3.3V";
1315 pinctrl-0 = <&flash1_vcc>;
1316 pinctrl-1 = <&flash1_vcc_18>;
1317 pinctrl-2 = <&flash1_vcc_33>;
1320 apio3_vdd_domain: apio3-vdd-domain {
1321 compatible = "rockchip,io_vol_domain";
1322 pinctrl-names = "default", "1.8V", "3.3V";
1323 pinctrl-0 = <&wifi_vcc>;
1324 pinctrl-1 = <&wifi_vcc_18>;
1325 pinctrl-2 = <&wifi_vcc_33>;
1328 apio5_vdd_domain: apio5-vdd-domain {
1329 compatible = "rockchip,io_vol_domain";
1330 pinctrl-names = "default", "1.8V", "3.3V";
1331 pinctrl-0 = <&bb_vcc>;
1332 pinctrl-1 = <&bb_vcc_18>;
1333 pinctrl-2 = <&bb_vcc_33>;
1336 apio4_vdd_domain: apio4-vdd-domain {
1337 compatible = "rockchip,io_vol_domain";
1338 pinctrl-names = "default", "1.8V", "3.3V";
1339 pinctrl-0 = <&audio_vcc>;
1340 pinctrl-1 = <&audio_vcc_18>;
1341 pinctrl-2 = <&audio_vcc_33>;
1344 apio1_vdd_domain: apio0-vdd-domain {
1345 compatible = "rockchip,io_vol_domain";
1346 pinctrl-names = "default", "1.8V", "3.3V";
1347 pinctrl-0 = <&gpio30_vcc>;
1348 pinctrl-1 = <&gpio30_vcc_18>;
1349 pinctrl-2 = <&gpio30_vcc_33>;
1352 apio2_vdd_domain: apio2-vdd-domain {
1353 compatible = "rockchip,io_vol_domain";
1354 pinctrl-names = "default", "1.8V", "3.3V";
1355 pinctrl-0 = <&gpio1830_vcc>;
1356 pinctrl-1 = <&gpio1830_vcc_18>;
1357 pinctrl-2 = <&gpio1830_vcc_33>;
1360 sdmmc0_vdd_domain: sdmmc0-vdd-domain {
1361 compatible = "rockchip,io_vol_domain";
1362 pinctrl-names = "default", "1.8V", "3.3V";
1363 pinctrl-0 = <&sdcard_vcc>;
1364 pinctrl-1 = <&sdcard_vcc_18>;
1365 pinctrl-2 = <&sdcard_vcc_33>;
1369 bootargs = "vmalloc=496M";