arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49 #include <dt-bindings/suspend/rockchip-rk3288.h>
  50 #include <dt-bindings/display/drm_mipi_dsi.h>
  51 #include "skeleton64.dtsi"
  52
  53 / {
  54         compatible = "rockchip,rk3288";
  55
  56         interrupt-parent = <&gic>;
  57
  58         aliases {
  59                 ethernet0 = &gmac;
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 mshc0 = &emmc;
  67                 mshc1 = &sdmmc;
  68                 mshc2 = &sdio0;
  69                 mshc3 = &sdio1;
  70                 serial0 = &uart0;
  71                 serial1 = &uart1;
  72                 serial2 = &uart2;
  73                 serial3 = &uart3;
  74                 serial4 = &uart4;
  75                 spi0 = &spi0;
  76                 spi1 = &spi1;
  77                 spi2 = &spi2;
  78                 dsi0 = &dsi0;
  79                 dsi1 = &dsi1;
  80         };
  81
  82         arm-pmu {
  83                 compatible = "arm,cortex-a12-pmu";
  84                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  85                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  86                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  87                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  88                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  89         };
  90
  91         cpus {
  92                 #address-cells = <1>;
  93                 #size-cells = <0>;
  94                 enable-method = "rockchip,rk3066-smp";
  95                 rockchip,pmu = <&pmu>;
  96
  97                 cpu0: cpu@500 {
  98                         device_type = "cpu";
  99                         compatible = "arm,cortex-a12";
 100                         reg = <0x500>;
 101                         resets = <&cru SRST_CORE0>;
 102                         operating-points-v2 = <&cpu0_opp_table>;
 103                         #cooling-cells = <2>; /* min followed by max */
 104                         dynamic-power-coefficient = <322>;
 105                         clocks = <&cru ARMCLK>;
 106                 };
 107                 cpu1: cpu@501 {
 108                         device_type = "cpu";
 109                         compatible = "arm,cortex-a12";
 110                         reg = <0x501>;
 111                         resets = <&cru SRST_CORE1>;
 112                         operating-points-v2 = <&cpu0_opp_table>;
 113                 };
 114                 cpu2: cpu@502 {
 115                         device_type = "cpu";
 116                         compatible = "arm,cortex-a12";
 117                         reg = <0x502>;
 118                         resets = <&cru SRST_CORE2>;
 119                         operating-points-v2 = <&cpu0_opp_table>;
 120                 };
 121                 cpu3: cpu@503 {
 122                         device_type = "cpu";
 123                         compatible = "arm,cortex-a12";
 124                         reg = <0x503>;
 125                         resets = <&cru SRST_CORE3>;
 126                         operating-points-v2 = <&cpu0_opp_table>;
 127                 };
 128         };
 129
 130         cpu0_opp_table: opp_table0 {
 131                 compatible = "operating-points-v2";
 132                 opp-shared;
 133
 134                 nvmem-cells = <&cpu_leakage>;
 135                 nvmem-cell-names = "cpu_leakage";
 136
 137                 opp-126000000 {
 138                         opp-hz = /bits/ 64 <126000000>;
 139                         opp-microvolt = <900000>;
 140                         clock-latency-ns = <40000>;
 141                 };
 142                 opp-216000000 {
 143                         opp-hz = /bits/ 64 <216000000>;
 144                         opp-microvolt = <900000>;
 145                         clock-latency-ns = <40000>;
 146                 };
 147                 opp-408000000 {
 148                         opp-hz = /bits/ 64 <408000000>;
 149                         opp-microvolt = <900000>;
 150                         clock-latency-ns = <40000>;
 151                 };
 152                 opp-600000000 {
 153                         opp-hz = /bits/ 64 <600000000>;
 154                         opp-microvolt = <900000>;
 155                         clock-latency-ns = <40000>;
 156                 };
 157                 opp-696000000 {
 158                         opp-hz = /bits/ 64 <696000000>;
 159                         opp-microvolt = <950000>;
 160                         clock-latency-ns = <40000>;
 161                 };
 162                 opp-816000000 {
 163                         opp-hz = /bits/ 64 <816000000>;
 164                         opp-microvolt = <1000000>;
 165                         clock-latency-ns = <40000>;
 166                         opp-suspend;
 167                 };
 168                 opp-1008000000 {
 169                         opp-hz = /bits/ 64 <1008000000>;
 170                         opp-microvolt = <1050000>;
 171                         clock-latency-ns = <40000>;
 172                 };
 173                 opp-1200000000 {
 174                         opp-hz = /bits/ 64 <1200000000>;
 175                         opp-microvolt = <1100000>;
 176                         clock-latency-ns = <40000>;
 177                 };
 178                 opp-1416000000 {
 179                         opp-hz = /bits/ 64 <1416000000>;
 180                         opp-microvolt = <1200000>;
 181                         clock-latency-ns = <40000>;
 182                 };
 183                 opp-1512000000 {
 184                         opp-hz = /bits/ 64 <1512000000>;
 185                         opp-microvolt = <1300000>;
 186                         clock-latency-ns = <40000>;
 187                 };
 188                 opp-1608000000 {
 189                         opp-hz = /bits/ 64 <1608000000>;
 190                         opp-microvolt = <1350000>;
 191                         clock-latency-ns = <40000>;
 192                 };
 193         };
 194
 195         amba {
 196                 compatible = "arm,amba-bus";
 197                 #address-cells = <2>;
 198                 #size-cells = <2>;
 199                 ranges;
 200
 201                 dmac_peri: dma-controller@ff250000 {
 202                         compatible = "arm,pl330", "arm,primecell";
 203                         reg = <0x0 0xff250000 0x0 0x4000>;
 204                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 205                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 206                         #dma-cells = <1>;
 207                         arm,pl330-broken-no-flushp;
 208                         peripherals-req-type-burst;
 209                         clocks = <&cru ACLK_DMAC2>;
 210                         clock-names = "apb_pclk";
 211                 };
 212
 213                 dmac_bus_ns: dma-controller@ff600000 {
 214                         compatible = "arm,pl330", "arm,primecell";
 215                         reg = <0x0 0xff600000 0x0 0x4000>;
 216                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 217                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 218                         #dma-cells = <1>;
 219                         arm,pl330-broken-no-flushp;
 220                         peripherals-req-type-burst;
 221                         clocks = <&cru ACLK_DMAC1>;
 222                         clock-names = "apb_pclk";
 223                         status = "disabled";
 224                 };
 225
 226                 dmac_bus_s: dma-controller@ffb20000 {
 227                         compatible = "arm,pl330", "arm,primecell";
 228                         reg = <0x0 0xffb20000 0x0 0x4000>;
 229                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 230                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 231                         #dma-cells = <1>;
 232                         arm,pl330-broken-no-flushp;
 233                         peripherals-req-type-burst;
 234                         clocks = <&cru ACLK_DMAC1>;
 235                         clock-names = "apb_pclk";
 236                 };
 237         };
 238
 239         reserved-memory {
 240                 #address-cells = <2>;
 241                 #size-cells = <2>;
 242                 ranges;
 243
 244                 /*
 245                  * The rk3288 cannot use the memory area above 0xfe000000
 246                  * for dma operations for some reason. While there is
 247                  * probably a better solution available somewhere, we
 248                  * haven't found it yet and while devices with 2GB of ram
 249                  * are not affected, this issue prevents 4GB from booting.
 250                  * So to make these devices at least bootable, block
 251                  * this area for the time being until the real solution
 252                  * is found.
 253                  */
 254                 dma-unusable@fe000000 {
 255                         reg = <0x0 0xfe000000 0x0 0x1000000>;
 256                 };
 257         };
 258
 259         xin24m: oscillator {
 260                 compatible = "fixed-clock";
 261                 clock-frequency = <24000000>;
 262                 clock-output-names = "xin24m";
 263                 #clock-cells = <0>;
 264         };
 265
 266         timer {
 267                 compatible = "arm,armv7-timer";
 268                 arm,cpu-registers-not-fw-configured;
 269                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 270                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 271                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 272                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 273                 clock-frequency = <24000000>;
 274         };
 275
 276         display-subsystem {
 277                 compatible = "rockchip,display-subsystem";
 278                 ports = <&vopl_out>, <&vopb_out>;
 279         };
 280
 281         sdmmc: dwmmc@ff0c0000 {
 282                 compatible = "rockchip,rk3288-dw-mshc";
 283                 clock-freq-min-max = <400000 150000000>;
 284                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 285                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 286                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 287                 fifo-depth = <0x100>;
 288                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 289                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 290                 status = "disabled";
 291         };
 292
 293         sdio0: dwmmc@ff0d0000 {
 294                 compatible = "rockchip,rk3288-dw-mshc";
 295                 clock-freq-min-max = <400000 150000000>;
 296                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 297                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 298                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 299                 fifo-depth = <0x100>;
 300                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 301                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 302                 status = "disabled";
 303         };
 304
 305         sdio1: dwmmc@ff0e0000 {
 306                 compatible = "rockchip,rk3288-dw-mshc";
 307                 clock-freq-min-max = <400000 150000000>;
 308                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 309                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 310                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 311                 fifo-depth = <0x100>;
 312                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 313                 reg = <0x0 0xff0e0000 0x0 0x4000>;
 314                 status = "disabled";
 315         };
 316
 317         emmc: dwmmc@ff0f0000 {
 318                 compatible = "rockchip,rk3288-dw-mshc";
 319                 clock-freq-min-max = <400000 150000000>;
 320                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 321                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 322                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 323                 fifo-depth = <0x100>;
 324                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 325                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 326                 status = "disabled";
 327                 supports-emmc;
 328         };
 329
 330         saradc: saradc@ff100000 {
 331                 compatible = "rockchip,saradc";
 332                 reg = <0x0 0xff100000 0x0 0x100>;
 333                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 334                 #io-channel-cells = <1>;
 335                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 336                 clock-names = "saradc", "apb_pclk";
 337                 resets = <&cru SRST_SARADC>;
 338                 reset-names = "saradc-apb";
 339                 status = "disabled";
 340         };
 341
 342         spi0: spi@ff110000 {
 343                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 344                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 345                 clock-names = "spiclk", "apb_pclk";
 346                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 347                 dma-names = "tx", "rx";
 348                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 349                 pinctrl-names = "default";
 350                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 351                 reg = <0x0 0xff110000 0x0 0x1000>;
 352                 #address-cells = <1>;
 353                 #size-cells = <0>;
 354                 status = "disabled";
 355         };
 356
 357         spi1: spi@ff120000 {
 358                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 359                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 360                 clock-names = "spiclk", "apb_pclk";
 361                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 362                 dma-names = "tx", "rx";
 363                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 364                 pinctrl-names = "default";
 365                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 366                 reg = <0x0 0xff120000 0x0 0x1000>;
 367                 #address-cells = <1>;
 368                 #size-cells = <0>;
 369                 status = "disabled";
 370         };
 371
 372         spi2: spi@ff130000 {
 373                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 374                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 375                 clock-names = "spiclk", "apb_pclk";
 376                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 377                 dma-names = "tx", "rx";
 378                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 379                 pinctrl-names = "default";
 380                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 381                 reg = <0x0 0xff130000 0x0 0x1000>;
 382                 #address-cells = <1>;
 383                 #size-cells = <0>;
 384                 status = "disabled";
 385         };
 386
 387         i2c0: i2c@ff650000 {
 388                 compatible = "rockchip,rk3288-i2c";
 389                 reg = <0x0 0xff650000 0x0 0x1000>;
 390                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 391                 #address-cells = <1>;
 392                 #size-cells = <0>;
 393                 clock-names = "i2c";
 394                 clocks = <&cru PCLK_I2C0>;
 395                 pinctrl-names = "default";
 396                 pinctrl-0 = <&i2c0_xfer>;
 397                 status = "disabled";
 398         };
 399
 400         i2c1: i2c@ff140000 {
 401                 compatible = "rockchip,rk3288-i2c";
 402                 reg = <0x0 0xff140000 0x0 0x1000>;
 403                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 404                 #address-cells = <1>;
 405                 #size-cells = <0>;
 406                 clock-names = "i2c";
 407                 clocks = <&cru PCLK_I2C1>;
 408                 pinctrl-names = "default";
 409                 pinctrl-0 = <&i2c1_xfer>;
 410                 status = "disabled";
 411         };
 412
 413         i2c3: i2c@ff150000 {
 414                 compatible = "rockchip,rk3288-i2c";
 415                 reg = <0x0 0xff150000 0x0 0x1000>;
 416                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 417                 #address-cells = <1>;
 418                 #size-cells = <0>;
 419                 clock-names = "i2c";
 420                 clocks = <&cru PCLK_I2C3>;
 421                 pinctrl-names = "default";
 422                 pinctrl-0 = <&i2c3_xfer>;
 423                 status = "disabled";
 424         };
 425
 426         i2c4: i2c@ff160000 {
 427                 compatible = "rockchip,rk3288-i2c";
 428                 reg = <0x0 0xff160000 0x0 0x1000>;
 429                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 430                 #address-cells = <1>;
 431                 #size-cells = <0>;
 432                 clock-names = "i2c";
 433                 clocks = <&cru PCLK_I2C4>;
 434                 pinctrl-names = "default";
 435                 pinctrl-0 = <&i2c4_xfer>;
 436                 status = "disabled";
 437         };
 438
 439         i2c5: i2c@ff170000 {
 440                 compatible = "rockchip,rk3288-i2c";
 441                 reg = <0x0 0xff170000 0x0 0x1000>;
 442                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 443                 #address-cells = <1>;
 444                 #size-cells = <0>;
 445                 clock-names = "i2c";
 446                 clocks = <&cru PCLK_I2C5>;
 447                 pinctrl-names = "default";
 448                 pinctrl-0 = <&i2c5_xfer>;
 449                 status = "disabled";
 450         };
 451
 452         uart0: serial@ff180000 {
 453                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 454                 reg = <0x0 0xff180000 0x0 0x100>;
 455                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 456                 reg-shift = <2>;
 457                 reg-io-width = <4>;
 458                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 459                 clock-names = "baudclk", "apb_pclk";
 460                 pinctrl-names = "default";
 461                 pinctrl-0 = <&uart0_xfer>;
 462                 status = "disabled";
 463         };
 464
 465         uart1: serial@ff190000 {
 466                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 467                 reg = <0x0 0xff190000 0x0 0x100>;
 468                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 469                 reg-shift = <2>;
 470                 reg-io-width = <4>;
 471                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 472                 clock-names = "baudclk", "apb_pclk";
 473                 pinctrl-names = "default";
 474                 pinctrl-0 = <&uart1_xfer>;
 475                 status = "disabled";
 476         };
 477
 478         uart2: serial@ff690000 {
 479                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 480                 reg = <0x0 0xff690000 0x0 0x100>;
 481                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 482                 reg-shift = <2>;
 483                 reg-io-width = <4>;
 484                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 485                 clock-names = "baudclk", "apb_pclk";
 486                 pinctrl-names = "default";
 487                 pinctrl-0 = <&uart2_xfer>;
 488                 status = "disabled";
 489         };
 490
 491         uart3: serial@ff1b0000 {
 492                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 493                 reg = <0x0 0xff1b0000 0x0 0x100>;
 494                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 495                 reg-shift = <2>;
 496                 reg-io-width = <4>;
 497                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 498                 clock-names = "baudclk", "apb_pclk";
 499                 pinctrl-names = "default";
 500                 pinctrl-0 = <&uart3_xfer>;
 501                 status = "disabled";
 502         };
 503
 504         uart4: serial@ff1c0000 {
 505                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 506                 reg = <0x0 0xff1c0000 0x0 0x100>;
 507                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 508                 reg-shift = <2>;
 509                 reg-io-width = <4>;
 510                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 511                 clock-names = "baudclk", "apb_pclk";
 512                 pinctrl-names = "default";
 513                 pinctrl-0 = <&uart4_xfer>;
 514                 status = "disabled";
 515         };
 516
 517         thermal_zones: thermal-zones {
 518                 soc_thermal: soc-thermal {
 519                         polling-delay-passive = <200>; /* milliseconds */
 520                         polling-delay = <1000>; /* milliseconds */
 521                         sustainable-power = <1200>; /* milliwatts */
 522
 523                         thermal-sensors = <&tsadc 1>;
 524                         trips {
 525                                 threshold: trip-point@0 {
 526                                         temperature = <75000>; /* millicelsius */
 527                                         hysteresis = <2000>; /* millicelsius */
 528                                         type = "passive";
 529                                 };
 530                                 target: trip-point@1 {
 531                                         temperature = <85000>; /* millicelsius */
 532                                         hysteresis = <2000>; /* millicelsius */
 533                                         type = "passive";
 534                                 };
 535                                 soc_crit: soc-crit {
 536                                         temperature = <90000>; /* millicelsius */
 537                                         hysteresis = <2000>; /* millicelsius */
 538                                         type = "critical";
 539                                 };
 540                         };
 541
 542                         cooling-maps {
 543                                 map0 {
 544                                         trip = <&target>;
 545                                         cooling-device =
 546                                         <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 547                                         contribution = <1024>;
 548                                 };
 549                                 map1 {
 550                                         trip = <&target>;
 551                                         cooling-device =
 552                                         <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 553                                         contribution = <1024>;
 554                                 };
 555                         };
 556                 };
 557
 558                 gpu_thermal: gpu-thermal {
 559                         polling-delay-passive = <200>; /* milliseconds */
 560                         polling-delay = <1000>; /* milliseconds */
 561                         thermal-sensors = <&tsadc 2>;
 562                 };
 563         };
 564
 565         tsadc: tsadc@ff280000 {
 566                 compatible = "rockchip,rk3288-tsadc";
 567                 reg = <0x0 0xff280000 0x0 0x100>;
 568                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 569                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 570                 clock-names = "tsadc", "apb_pclk";
 571                 assigned-clocks = <&cru SCLK_TSADC>;
 572                 assigned-clock-rates = <5000>;
 573                 resets = <&cru SRST_TSADC>;
 574                 reset-names = "tsadc-apb";
 575                 pinctrl-names = "init", "default", "sleep";
 576                 pinctrl-0 = <&otp_gpio>;
 577                 pinctrl-1 = <&otp_out>;
 578                 pinctrl-2 = <&otp_gpio>;
 579                 #thermal-sensor-cells = <1>;
 580                 rockchip,hw-tshut-temp = <95000>;
 581                 status = "disabled";
 582         };
 583
 584         gmac: ethernet@ff290000 {
 585                 compatible = "rockchip,rk3288-gmac";
 586                 reg = <0x0 0xff290000 0x0 0x10000>;
 587                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 588                                 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 589                 interrupt-names = "macirq", "eth_wake_irq";
 590                 rockchip,grf = <&grf>;
 591                 clocks = <&cru SCLK_MAC>,
 592                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 593                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 594                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 595                 clock-names = "stmmaceth",
 596                         "mac_clk_rx", "mac_clk_tx",
 597                         "clk_mac_ref", "clk_mac_refout",
 598                         "aclk_mac", "pclk_mac";
 599                 resets = <&cru SRST_MAC>;
 600                 reset-names = "stmmaceth";
 601                 status = "disabled";
 602         };
 603
 604         usb_host0_ehci: usb@ff500000 {
 605                 compatible = "generic-ehci";
 606                 reg = <0x0 0xff500000 0x0 0x100>;
 607                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 608                 clocks = <&cru HCLK_USBHOST0>;
 609                 clock-names = "usbhost";
 610                 phys = <&usbphy1>;
 611                 phy-names = "usb";
 612                 status = "disabled";
 613         };
 614
 615         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 616
 617         usb_host1: usb@ff540000 {
 618                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 619                                 "snps,dwc2";
 620                 reg = <0x0 0xff540000 0x0 0x40000>;
 621                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 622                 clocks = <&cru HCLK_USBHOST1>;
 623                 clock-names = "otg";
 624                 dr_mode = "host";
 625                 phys = <&usbphy2>;
 626                 phy-names = "usb2-phy";
 627                 status = "disabled";
 628         };
 629
 630         usb_otg: usb@ff580000 {
 631                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 632                                 "snps,dwc2";
 633                 reg = <0x0 0xff580000 0x0 0x40000>;
 634                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 635                 clocks = <&cru HCLK_OTG0>;
 636                 clock-names = "otg";
 637                 dr_mode = "otg";
 638                 g-np-tx-fifo-size = <16>;
 639                 g-rx-fifo-size = <275>;
 640                 g-tx-fifo-size = <256 128 128 64 64 32>;
 641                 g-use-dma;
 642                 phys = <&usbphy0>;
 643                 phy-names = "usb2-phy";
 644                 status = "disabled";
 645         };
 646
 647         usb_hsic: usb@ff5c0000 {
 648                 compatible = "generic-ehci";
 649                 reg = <0x0 0xff5c0000 0x0 0x100>;
 650                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 651                 clocks = <&cru HCLK_HSIC>;
 652                 clock-names = "usbhost";
 653                 status = "disabled";
 654         };
 655
 656         dmc: dmc@ff610000 {
 657                 compatible = "rockchip,rk3288-dmc", "syscon";
 658                 rockchip,cru = <&cru>;
 659                 rockchip,grf = <&grf>;
 660                 rockchip,pmu = <&pmu>;
 661                 rockchip,sgrf = <&sgrf>;
 662                 rockchip,noc = <&noc>;
 663                 reg = <0x0 0xff610000 0x0 0x3fc
 664                        0x0 0xff620000 0x0 0x294
 665                        0x0 0xff630000 0x0 0x3fc
 666                        0x0 0xff640000 0x0 0x294>;
 667                 rockchip,sram = <&ddr_sram>;
 668                 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
 669                          <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
 670                          <&cru ARMCLK>, <&cru ACLK_DMAC1>;
 671                 clock-names = "pclk_ddrupctl0", "pclk_publ0",
 672                               "pclk_ddrupctl1", "pclk_publ1",
 673                               "arm_clk", "aclk_dmac1";
 674         };
 675
 676         i2c2: i2c@ff660000 {
 677                 compatible = "rockchip,rk3288-i2c";
 678                 reg = <0x0 0xff660000 0x0 0x1000>;
 679                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 680                 #address-cells = <1>;
 681                 #size-cells = <0>;
 682                 clock-names = "i2c";
 683                 clocks = <&cru PCLK_I2C2>;
 684                 pinctrl-names = "default";
 685                 pinctrl-0 = <&i2c2_xfer>;
 686                 status = "disabled";
 687         };
 688
 689         pwm0: pwm@ff680000 {
 690                 compatible = "rockchip,rk3288-pwm";
 691                 reg = <0x0 0xff680000 0x0 0x10>;
 692                 #pwm-cells = <3>;
 693                 pinctrl-names = "default";
 694                 pinctrl-0 = <&pwm0_pin>;
 695                 clocks = <&cru PCLK_PWM>;
 696                 clock-names = "pwm";
 697                 status = "disabled";
 698         };
 699
 700         pwm1: pwm@ff680010 {
 701                 compatible = "rockchip,rk3288-pwm";
 702                 reg = <0x0 0xff680010 0x0 0x10>;
 703                 #pwm-cells = <3>;
 704                 pinctrl-names = "default";
 705                 pinctrl-0 = <&pwm1_pin>;
 706                 clocks = <&cru PCLK_PWM>;
 707                 clock-names = "pwm";
 708                 status = "disabled";
 709         };
 710
 711         pwm2: pwm@ff680020 {
 712                 compatible = "rockchip,rk3288-pwm";
 713                 reg = <0x0 0xff680020 0x0 0x10>;
 714                 #pwm-cells = <3>;
 715                 pinctrl-names = "default";
 716                 pinctrl-0 = <&pwm2_pin>;
 717                 clocks = <&cru PCLK_PWM>;
 718                 clock-names = "pwm";
 719                 status = "disabled";
 720         };
 721
 722         pwm3: pwm@ff680030 {
 723                 compatible = "rockchip,rk3288-pwm";
 724                 reg = <0x0 0xff680030 0x0 0x10>;
 725                 #pwm-cells = <2>;
 726                 pinctrl-names = "default";
 727                 pinctrl-0 = <&pwm3_pin>;
 728                 clocks = <&cru PCLK_PWM>;
 729                 clock-names = "pwm";
 730                 status = "disabled";
 731         };
 732
 733         timer: timer@ff6b0000 {
 734                 compatible = "rockchip,rk3288-timer";
 735                 reg = <0x0 0xff6b0000 0x0 0x20>;
 736                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 737                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 738                 clock-names = "timer", "pclk";
 739         };
 740
 741         bus_intmem@ff700000 {
 742                 compatible = "mmio-sram";
 743                 reg = <0x0 0xff700000 0x0 0x18000>;
 744                 #address-cells = <1>;
 745                 #size-cells = <1>;
 746                 ranges = <0 0x0 0xff700000 0x18000>;
 747                 smp-sram@0 {
 748                         compatible = "rockchip,rk3066-smp-sram";
 749                         reg = <0x00 0x10>;
 750                 };
 751                 ddr_sram: ddr-sram@1000 {
 752                         compatible = "rockchip,rk3288-ddr-sram";
 753                         reg = <0x1000 0x4000>;
 754                 };
 755         };
 756
 757         sram@ff720000 {
 758                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 759                 reg = <0x0 0xff720000 0x0 0x1000>;
 760         };
 761
 762         qos_gpu_r: qos@ffaa0000 {
 763                 compatible = "syscon";
 764                 reg = <0x0 0xffaa0000 0x0 0x20>;
 765         };
 766
 767         qos_gpu_w: qos@ffaa0080 {
 768                 compatible = "syscon";
 769                 reg = <0x0 0xffaa0080 0x0 0x20>;
 770         };
 771
 772         qos_vio1_vop: qos@ffad0000 {
 773                 compatible = "syscon";
 774                 reg = <0x0 0xffad0000 0x0 0x20>;
 775         };
 776
 777         qos_vio1_isp_w0: qos@ffad0100 {
 778                 compatible = "syscon";
 779                 reg = <0x0 0xffad0100 0x0 0x20>;
 780         };
 781
 782         qos_vio1_isp_w1: qos@ffad0180 {
 783                 compatible = "syscon";
 784                 reg = <0x0 0xffad0180 0x0 0x20>;
 785         };
 786
 787         qos_vio0_vop: qos@ffad0400 {
 788                 compatible = "syscon";
 789                 reg = <0x0 0xffad0400 0x0 0x20>;
 790         };
 791
 792         qos_vio0_vip: qos@ffad0480 {
 793                 compatible = "syscon";
 794                 reg = <0x0 0xffad0480 0x0 0x20>;
 795         };
 796
 797         qos_vio0_iep: qos@ffad0500 {
 798                 compatible = "syscon";
 799                 reg = <0x0 0xffad0500 0x0 0x20>;
 800         };
 801
 802         qos_vio2_rga_r: qos@ffad0800 {
 803                 compatible = "syscon";
 804                 reg = <0x0 0xffad0800 0x0 0x20>;
 805         };
 806
 807         qos_vio2_rga_w: qos@ffad0880 {
 808                 compatible = "syscon";
 809                 reg = <0x0 0xffad0880 0x0 0x20>;
 810         };
 811
 812         qos_vio1_isp_r: qos@ffad0900 {
 813                 compatible = "syscon";
 814                 reg = <0x0 0xffad0900 0x0 0x20>;
 815         };
 816
 817         qos_video: qos@ffae0000 {
 818                 compatible = "syscon";
 819                 reg = <0x0 0xffae0000 0x0 0x20>;
 820         };
 821
 822         qos_hevc_r: qos@ffaf0000 {
 823                 compatible = "syscon";
 824                 reg = <0x0 0xffaf0000 0x0 0x20>;
 825         };
 826
 827         qos_hevc_w: qos@ffaf0080 {
 828                 compatible = "syscon";
 829                 reg = <0x0 0xffaf0080 0x0 0x20>;
 830         };
 831
 832         pmu: power-management@ff730000 {
 833                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 834                 reg = <0x0 0xff730000 0x0 0x100>;
 835
 836                 power: power-controller {
 837                         compatible = "rockchip,rk3288-power-controller";
 838                         #power-domain-cells = <1>;
 839                         #address-cells = <1>;
 840                         #size-cells = <0>;
 841
 842                         /*
 843                          * Note: Although SCLK_* are the working clocks
 844                          * of device without including on the NOC, needed for
 845                          * synchronous reset.
 846                          *
 847                          * The clocks on the which NOC:
 848                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 849                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 850                          * ACLK_RGA is on ACLK_RGA_NIU.
 851                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 852                          *
 853                          * Which clock are device clocks:
 854                          *      clocks          devices
 855                          *      *_IEP           IEP:Image Enhancement Processor
 856                          *      *_ISP           ISP:Image Signal Processing
 857                          *      *_VIP           VIP:Video Input Processor
 858                          *      *_VOP*          VOP:Visual Output Processor
 859                          *      *_RGA           RGA
 860                          *      *_EDP*          EDP
 861                          *      *_LVDS_*        LVDS
 862                          *      *_HDMI          HDMI
 863                          *      *_MIPI_*        MIPI
 864                          */
 865                         pd_vio@RK3288_PD_VIO {
 866                                 reg = <RK3288_PD_VIO>;
 867                                 clocks = <&cru ACLK_IEP>,
 868                                          <&cru ACLK_ISP>,
 869                                          <&cru ACLK_RGA>,
 870                                          <&cru ACLK_VIP>,
 871                                          <&cru ACLK_VOP0>,
 872                                          <&cru ACLK_VOP1>,
 873                                          <&cru DCLK_VOP0>,
 874                                          <&cru DCLK_VOP1>,
 875                                          <&cru HCLK_IEP>,
 876                                          <&cru HCLK_ISP>,
 877                                          <&cru HCLK_RGA>,
 878                                          <&cru HCLK_VIP>,
 879                                          <&cru HCLK_VOP0>,
 880                                          <&cru HCLK_VOP1>,
 881                                          <&cru PCLK_EDP_CTRL>,
 882                                          <&cru PCLK_HDMI_CTRL>,
 883                                          <&cru PCLK_LVDS_PHY>,
 884                                          <&cru PCLK_MIPI_CSI>,
 885                                          <&cru PCLK_MIPI_DSI0>,
 886                                          <&cru PCLK_MIPI_DSI1>,
 887                                          <&cru SCLK_EDP_24M>,
 888                                          <&cru SCLK_EDP>,
 889                                          <&cru SCLK_ISP_JPE>,
 890                                          <&cru SCLK_ISP>,
 891                                          <&cru SCLK_RGA>;
 892                                 pm_qos = <&qos_vio0_iep>,
 893                                          <&qos_vio1_vop>,
 894                                          <&qos_vio1_isp_w0>,
 895                                          <&qos_vio1_isp_w1>,
 896                                          <&qos_vio0_vop>,
 897                                          <&qos_vio0_vip>,
 898                                          <&qos_vio2_rga_r>,
 899                                          <&qos_vio2_rga_w>,
 900                                          <&qos_vio1_isp_r>;
 901                         };
 902
 903                         /*
 904                          * Note: The following 3 are HEVC(H.265) clocks,
 905                          * and on the ACLK_HEVC_NIU (NOC).
 906                          */
 907                         pd_hevc@RK3288_PD_HEVC {
 908                                 reg = <RK3288_PD_HEVC>;
 909                                 clocks = <&cru ACLK_HEVC>,
 910                                          <&cru SCLK_HEVC_CABAC>,
 911                                          <&cru SCLK_HEVC_CORE>;
 912                                 pm_qos = <&qos_hevc_r>,
 913                                          <&qos_hevc_w>;
 914                         };
 915
 916                         /*
 917                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 918                          * (video endecoder & decoder) clocks that on the
 919                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 920                          */
 921                         pd_video@RK3288_PD_VIDEO {
 922                                 reg = <RK3288_PD_VIDEO>;
 923                                 clocks = <&cru ACLK_VCODEC>,
 924                                          <&cru HCLK_VCODEC>;
 925                                 pm_qos = <&qos_video>;
 926                         };
 927
 928                         /*
 929                          * Note: ACLK_GPU is the GPU clock,
 930                          * and on the ACLK_GPU_NIU (NOC).
 931                          */
 932                         pd_gpu@RK3288_PD_GPU {
 933                                 reg = <RK3288_PD_GPU>;
 934                                 clocks = <&cru ACLK_GPU>;
 935                                 pm_qos = <&qos_gpu_r>,
 936                                          <&qos_gpu_w>;
 937                         };
 938                 };
 939
 940                 reboot-mode {
 941                         compatible = "syscon-reboot-mode";
 942                         offset = <0x94>;
 943                         mode-normal = <BOOT_NORMAL>;
 944                         mode-recovery = <BOOT_RECOVERY>;
 945                         mode-bootloader = <BOOT_FASTBOOT>;
 946                         mode-loader = <BOOT_BL_DOWNLOAD>;
 947                         mode-ums = <BOOT_UMS>;
 948                 };
 949         };
 950
 951         sgrf: syscon@ff740000 {
 952                 compatible = "rockchip,rk3288-sgrf", "syscon";
 953                 reg = <0x0 0xff740000 0x0 0x1000>;
 954         };
 955
 956         cru: clock-controller@ff760000 {
 957                 compatible = "rockchip,rk3288-cru";
 958                 reg = <0x0 0xff760000 0x0 0x1000>;
 959                 rockchip,grf = <&grf>;
 960                 #clock-cells = <1>;
 961                 #reset-cells = <1>;
 962                 assigned-clocks = <&cru PLL_GPLL>,
 963                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 964                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 965                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 966                                   <&cru PCLK_PERI>;
 967                 assigned-clock-rates = <594000000>,
 968                                        <500000000>, <300000000>,
 969                                        <150000000>, <75000000>,
 970                                        <300000000>, <150000000>,
 971                                        <75000000>;
 972         };
 973
 974         grf: syscon@ff770000 {
 975                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 976                 reg = <0x0 0xff770000 0x0 0x1000>;
 977
 978                 edp_phy: edp-phy {
 979                         compatible = "rockchip,rk3288-dp-phy";
 980                         clocks = <&cru SCLK_EDP_24M>;
 981                         clock-names = "24m";
 982                         #phy-cells = <0>;
 983                         status = "disabled";
 984                 };
 985
 986                 io_domains: io-domains {
 987                         compatible = "rockchip,rk3288-io-voltage-domain";
 988                         status = "disabled";
 989                 };
 990
 991                 usbphy: usbphy {
 992                         compatible = "rockchip,rk3288-usb-phy";
 993                         #address-cells = <1>;
 994                         #size-cells = <0>;
 995                         status = "disabled";
 996
 997                         usbphy0: usb-phy@320 {
 998                                 #phy-cells = <0>;
 999                                 reg = <0x320>;
1000                                 clocks = <&cru SCLK_OTGPHY0>;
1001                                 clock-names = "phyclk";
1002                                 #clock-cells = <0>;
1003                                 resets = <&cru SRST_USBOTG_PHY>;
1004                                 reset-names = "phy-reset";
1005                         };
1006
1007                         usbphy1: usb-phy@334 {
1008                                 #phy-cells = <0>;
1009                                 reg = <0x334>;
1010                                 clocks = <&cru SCLK_OTGPHY1>;
1011                                 clock-names = "phyclk";
1012                                 #clock-cells = <0>;
1013                         };
1014
1015                         usbphy2: usb-phy@348 {
1016                                 #phy-cells = <0>;
1017                                 reg = <0x348>;
1018                                 clocks = <&cru SCLK_OTGPHY2>;
1019                                 clock-names = "phyclk";
1020                                 #clock-cells = <0>;
1021                                 resets = <&cru SRST_USBHOST1_PHY>;
1022                                 reset-names = "phy-reset";
1023                         };
1024                 };
1025         };
1026
1027         wdt: watchdog@ff800000 {
1028                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
1029                 reg = <0x0 0xff800000 0x0 0x100>;
1030                 clocks = <&cru PCLK_WDT>;
1031                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1032                 status = "disabled";
1033         };
1034
1035         spdif: sound@ff8b0000 {
1036                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
1037                 reg = <0x0 0xff8b0000 0x0 0x10000>;
1038                 #sound-dai-cells = <0>;
1039                 clock-names = "hclk", "mclk";
1040                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
1041                 dmas = <&dmac_bus_s 3>;
1042                 dma-names = "tx";
1043                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1044                 pinctrl-names = "default";
1045                 pinctrl-0 = <&spdif_tx>;
1046                 rockchip,grf = <&grf>;
1047                 status = "disabled";
1048         };
1049
1050         i2s: i2s@ff890000 {
1051                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
1052                 reg = <0x0 0xff890000 0x0 0x10000>;
1053                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1054                 #address-cells = <1>;
1055                 #size-cells = <0>;
1056                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
1057                 dma-names = "tx", "rx";
1058                 clock-names = "i2s_hclk", "i2s_clk";
1059                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
1060                 pinctrl-names = "default";
1061                 pinctrl-0 = <&i2s0_bus>;
1062                 rockchip,playback-channels = <8>;
1063                 rockchip,capture-channels = <2>;
1064                 status = "disabled";
1065         };
1066
1067         iep: iep@ff90000 {
1068                 compatible = "rockchip,iep";
1069                 iommu_enabled = <1>;
1070                 iommus = <&iep_mmu>;
1071                 reg = <0x0 0xff900000 0x0 0x800>;
1072                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1073                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1074                 clock-names = "aclk_iep", "hclk_iep";
1075                 power-domains = <&power RK3288_PD_VIO>;
1076                 allocator = <1>;
1077                 version = <1>;
1078                 status = "disabled";
1079         };
1080
1081         iep_mmu: iommu@ff900800 {
1082                 compatible = "rockchip,iommu";
1083                 reg = <0x0 0xff900800 0x0 0x40>;
1084                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1085                 interrupt-names = "iep_mmu";
1086                 #iommu-cells = <0>;
1087                 status = "disabled";
1088         };
1089
1090         cif_isp0: cif_isp@ff910000 {
1091                 compatible = "rockchip,rk3288-cif-isp";
1092                 rockchip,grf = <&grf>;
1093                 reg = <0x0 0xff910000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
1094                 reg-names = "register", "csihost-register";
1095                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1096                         <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
1097                         <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
1098                         <&cru SCLK_MIPIDSI_24M>;
1099                 clock-names = "aclk_isp", "hclk_isp",
1100                         "sclk_isp", "sclk_isp_jpe",
1101                         "pclk_mipi_csi", "pclk_isp_in",
1102                         "sclk_mipidsi_24m";
1103                 resets = <&cru SRST_ISP>;
1104                 reset-names = "rst_isp";
1105                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1106                 interrupt-names = "cif_isp10_irq";
1107                 power-domains = <&power RK3288_PD_VIO>;
1108                 rockchip,isp,iommu-enable = <1>;
1109                 iommus = <&isp_mmu>;
1110                 status = "disabled";
1111         };
1112
1113         isp: isp@ff910000 {
1114                 compatible = "rockchip,rk3288-isp", "rockchip,isp";
1115                 reg = <0x0 0xff910000 0x0 0x4000>;
1116                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1117                 power-domains = <&power RK3288_PD_VIO>;
1118                 clocks =
1119                         <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
1120                         <&cru SCLK_ISP_JPE>, <&cru PCLK_ISP_IN>,
1121                         <&cru SCLK_VIP_OUT>, <&cru SCLK_MIPIDSI_24M>,
1122                         <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>;
1123                 clock-names =
1124                         "aclk_isp", "hclk_isp", "clk_isp",
1125                         "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
1126                         "clk_mipi_24m", "clk_cif_pll", "hclk_mipiphy1";
1127                 pinctrl-names =
1128                         "default", "isp_dvp8bit2", "isp_dvp10bit",
1129                         "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl",
1130                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
1131                         "isp_flash_as_trigger_out";
1132                 pinctrl-0 = <&isp_mipi>;
1133                 pinctrl-1 = <&isp_mipi &isp_dvp_d2d9>;
1134                 pinctrl-2 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1>;
1135                 pinctrl-3 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1
1136                                         &isp_dvp_d10d11>;
1137                 pinctrl-4 = <&isp_mipi &isp_dvp_d0d7>;
1138                 pinctrl-5 = <&isp_mipi>;
1139                 pinctrl-6 = <&isp_mipi &isp_prelight>;
1140                 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1141                 pinctrl-8 = <&isp_flash_trigger>;
1142                 rockchip,isp,mipiphy = <2>;
1143                 rockchip,isp,cifphy = <1>;
1144                 rockchip,isp,mipiphy1,reg = <0xff968000 0x4000>;
1145                 rockchip,grf = <&grf>;
1146                 rockchip,cru = <&cru>;
1147                 rockchip,gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>;
1148                 rockchip,isp,iommu_enable = <1>;
1149                 iommus = <&isp_mmu>;
1150                 status = "disabled";
1151         };
1152
1153         isp_mmu: iommu@ff914000 {
1154                 compatible = "rockchip,iommu";
1155                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1156                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1157                 interrupt-names = "isp_mmu";
1158                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1159                 clock-names = "aclk", "hclk";
1160                 rk_iommu,disable_reset_quirk;
1161                 #iommu-cells = <0>;
1162                 power-domains = <&power RK3288_PD_VIO>;
1163                 status = "disabled";
1164         };
1165
1166         rga: rga@ff920000 {
1167                 compatible = "rockchip,rk3288-rga";
1168                 reg = <0x0 0xff920000 0x0 0x180>;
1169                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1170                 interrupt-names = "rga";
1171                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1172                 clock-names = "aclk", "hclk", "sclk";
1173                 power-domains = <&power RK3288_PD_VIO>;
1174                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1175                 reset-names = "core", "axi", "ahb";
1176                 dma-coherent;
1177                 status = "disabled";
1178         };
1179
1180         vopb: vop@ff930000 {
1181                 compatible = "rockchip,rk3288-vop";
1182                 reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
1183                 reg-names = "regs", "gamma_lut";
1184                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1185                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1186                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1187                 power-domains = <&power RK3288_PD_VIO>;
1188                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1189                 reset-names = "axi", "ahb", "dclk";
1190                 iommus = <&vopb_mmu>;
1191                 status = "disabled";
1192
1193                 vopb_out: port {
1194                         #address-cells = <1>;
1195                         #size-cells = <0>;
1196
1197                         vopb_out_hdmi: endpoint@0 {
1198                                 reg = <0>;
1199                                 remote-endpoint = <&hdmi_in_vopb>;
1200                         };
1201
1202                         vopb_out_edp: endpoint@1 {
1203                                 reg = <1>;
1204                                 remote-endpoint = <&edp_in_vopb>;
1205                         };
1206
1207                         vopb_out_dsi0: endpoint@2 {
1208                                 reg = <2>;
1209                                 remote-endpoint = <&dsi0_in_vopb>;
1210                         };
1211
1212                         vopb_out_lvds: endpoint@3 {
1213                                 reg = <3>;
1214                                 remote-endpoint = <&lvds_in_vopb>;
1215                         };
1216
1217                         vopb_out_dsi1: endpoint@4 {
1218                                 reg = <4>;
1219                                 remote-endpoint = <&dsi1_in_vopb>;
1220                         };
1221                 };
1222         };
1223
1224         vopb_mmu: iommu@ff930300 {
1225                 compatible = "rockchip,iommu";
1226                 reg = <0x0 0xff930300 0x0 0x100>;
1227                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1228                 interrupt-names = "vopb_mmu";
1229                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1230                 clock-names = "aclk", "hclk";
1231                 power-domains = <&power RK3288_PD_VIO>;
1232                 #iommu-cells = <0>;
1233                 status = "disabled";
1234         };
1235
1236         vopl: vop@ff940000 {
1237                 compatible = "rockchip,rk3288-vop";
1238                 reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>;
1239                 reg-names = "regs", "gamma_lut";
1240                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1241                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1242                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1243                 power-domains = <&power RK3288_PD_VIO>;
1244                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1245                 reset-names = "axi", "ahb", "dclk";
1246                 iommus = <&vopl_mmu>;
1247                 status = "disabled";
1248
1249                 vopl_out: port {
1250                         #address-cells = <1>;
1251                         #size-cells = <0>;
1252
1253                         vopl_out_hdmi: endpoint@0 {
1254                                 reg = <0>;
1255                                 remote-endpoint = <&hdmi_in_vopl>;
1256                         };
1257
1258                         vopl_out_edp: endpoint@1 {
1259                                 reg = <1>;
1260                                 remote-endpoint = <&edp_in_vopl>;
1261                         };
1262
1263                         vopl_out_dsi0: endpoint@2 {
1264                                 reg = <2>;
1265                                 remote-endpoint = <&dsi0_in_vopl>;
1266                         };
1267
1268                         vopl_out_lvds: endpoint@3 {
1269                                 reg = <3>;
1270                                 remote-endpoint = <&lvds_in_vopl>;
1271                         };
1272
1273                         vopl_out_dsi1: endpoint@4 {
1274                                 reg = <4>;
1275                                 remote-endpoint = <&dsi1_in_vopl>;
1276                         };
1277                 };
1278         };
1279
1280         vopl_mmu: iommu@ff940300 {
1281                 compatible = "rockchip,iommu";
1282                 reg = <0x0 0xff940300 0x0 0x100>;
1283                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1284                 interrupt-names = "vopl_mmu";
1285                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1286                 clock-names = "aclk", "hclk";
1287                 power-domains = <&power RK3288_PD_VIO>;
1288                 #iommu-cells = <0>;
1289                 status = "disabled";
1290         };
1291
1292         dsi0: dsi@ff960000 {
1293                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1294                 reg = <0x0 0xff960000 0x0 0x4000>;
1295                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1296                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1297                 clock-names = "ref", "pclk";
1298                 power-domains = <&power RK3288_PD_VIO>;
1299                 rockchip,grf = <&grf>;
1300                 #address-cells = <1>;
1301                 #size-cells = <0>;
1302                 status = "disabled";
1303
1304                 ports {
1305                         #address-cells = <1>;
1306                         #size-cells = <0>;
1307
1308                         dsi0_in: port {
1309                                 #address-cells = <1>;
1310                                 #size-cells = <0>;
1311
1312                                 dsi0_in_vopb: endpoint@0 {
1313                                         reg = <0>;
1314                                         remote-endpoint = <&vopb_out_dsi0>;
1315                                 };
1316                                 dsi0_in_vopl: endpoint@1 {
1317                                         reg = <1>;
1318                                         remote-endpoint = <&vopl_out_dsi0>;
1319                                 };
1320                         };
1321                 };
1322         };
1323
1324         dsi1: dsi@ff964000 {
1325                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1326                 reg = <0x0 0xff964000 0x0 0x4000>;
1327                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1328                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI1>;
1329                 clock-names = "ref", "pclk";
1330                 power-domains = <&power RK3288_PD_VIO>;
1331                 rockchip,grf = <&grf>;
1332                 #address-cells = <1>;
1333                 #size-cells = <0>;
1334                 status = "disabled";
1335
1336                 ports {
1337                         #address-cells = <1>;
1338                         #size-cells = <0>;
1339
1340                         dsi1_in: port {
1341                                 #address-cells = <1>;
1342                                 #size-cells = <0>;
1343
1344                                 dsi1_in_vopb: endpoint@0 {
1345                                         reg = <0>;
1346                                         remote-endpoint = <&vopb_out_dsi1>;
1347                                 };
1348                                 dsi1_in_vopl: endpoint@1 {
1349                                         reg = <1>;
1350                                         remote-endpoint = <&vopl_out_dsi1>;
1351                                 };
1352                         };
1353                 };
1354         };
1355
1356         edp: dp@ff970000 {
1357                 compatible = "rockchip,rk3288-dp";
1358                 reg = <0x0 0xff970000 0x0 0x4000>;
1359                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1360                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1361                 clock-names = "dp", "pclk";
1362                 power-domains = <&power RK3288_PD_VIO>;
1363                 phys = <&edp_phy>;
1364                 phy-names = "dp";
1365                 resets = <&cru SRST_EDP>;
1366                 reset-names = "dp";
1367                 rockchip,grf = <&grf>;
1368                 status = "disabled";
1369
1370                 ports {
1371                         #address-cells = <1>;
1372                         #size-cells = <0>;
1373                         edp_in: port@0 {
1374                                 reg = <0>;
1375                                 #address-cells = <1>;
1376                                 #size-cells = <0>;
1377                                 edp_in_vopb: endpoint@0 {
1378                                         reg = <0>;
1379                                         remote-endpoint = <&vopb_out_edp>;
1380                                 };
1381                                 edp_in_vopl: endpoint@1 {
1382                                         reg = <1>;
1383                                         remote-endpoint = <&vopl_out_edp>;
1384                                 };
1385                         };
1386                 };
1387         };
1388
1389         lvds: lvds@ff96c000 {
1390                 compatible = "rockchip,rk3288-lvds";
1391                 reg = <0x0 0xff96c000 0x0 0x4000>;
1392                 clocks = <&cru PCLK_LVDS_PHY>;
1393                 clock-names = "pclk_lvds";
1394                 pinctrl-names = "default";
1395                 pinctrl-0 = <&lcdc0_ctl>;
1396                 power-domains = <&power RK3288_PD_VIO>;
1397                 rockchip,grf = <&grf>;
1398                 status = "disabled";
1399
1400                 ports {
1401                         #address-cells = <1>;
1402                         #size-cells = <0>;
1403
1404                         lvds_in: port@0 {
1405                                 reg = <0>;
1406
1407                                 #address-cells = <1>;
1408                                 #size-cells = <0>;
1409
1410                                 lvds_in_vopb: endpoint@0 {
1411                                         reg = <0>;
1412                                         remote-endpoint = <&vopb_out_lvds>;
1413                                 };
1414                                 lvds_in_vopl: endpoint@1 {
1415                                         reg = <1>;
1416                                         remote-endpoint = <&vopl_out_lvds>;
1417                                 };
1418                         };
1419                 };
1420         };
1421
1422         hdmi: hdmi@ff980000 {
1423                 compatible = "rockchip,rk3288-dw-hdmi";
1424                 reg = <0x0 0xff980000 0x0 0x20000>;
1425                 reg-io-width = <4>;
1426                 rockchip,grf = <&grf>;
1427                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1428                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1429                 clock-names = "iahb", "isfr";
1430                 pinctrl-names = "default";
1431                 pinctrl-0 = <&hdmi_ddc>;
1432                 power-domains = <&power RK3288_PD_VIO>;
1433                 status = "disabled";
1434
1435                 ports {
1436                         hdmi_in: port {
1437                                 #address-cells = <1>;
1438                                 #size-cells = <0>;
1439                                 hdmi_in_vopb: endpoint@0 {
1440                                         reg = <0>;
1441                                         remote-endpoint = <&vopb_out_hdmi>;
1442                                 };
1443                                 hdmi_in_vopl: endpoint@1 {
1444                                         reg = <1>;
1445                                         remote-endpoint = <&vopl_out_hdmi>;
1446                                 };
1447                         };
1448                 };
1449         };
1450
1451         vpu: video-codec@ff9a0000 {
1452                 compatible = "rockchip,rk3288-vpu";
1453                 reg = <0x0 0xff9a0000 0x0 0x800>;
1454                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1455                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1456                 interrupt-names = "vepu", "vdpu";
1457                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1458                 clock-names = "aclk", "hclk";
1459                 power-domains = <&power RK3288_PD_VIDEO>;
1460                 iommus = <&vpu_mmu>;
1461                 assigned-clocks = <&cru ACLK_VCODEC>;
1462                 assigned-clock-rates = <400000000>;
1463                 status = "disabled";
1464         };
1465
1466         vpu_service: vpu-service@ff9a0000 {
1467                 compatible = "rockchip,vpu_service";
1468                 reg = <0x0 0xff9a0000 0x0 0x800>;
1469                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1470                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1471                 interrupt-names = "irq_enc", "irq_dec";
1472                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1473                 clock-names = "aclk_vcodec", "hclk_vcodec";
1474                 power-domains = <&power RK3288_PD_VIDEO>;
1475                 rockchip,grf = <&grf>;
1476                 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
1477                 reset-names = "video_a", "video_h";
1478                 iommus = <&vpu_mmu>;
1479                 iommu_enabled = <1>;
1480                 status = "disabled";
1481                 /* 0 means ion, 1 means drm */
1482                 allocator = <1>;
1483         };
1484
1485         vpu_mmu: iommu@ff9a0800 {
1486                 compatible = "rockchip,iommu";
1487                 reg = <0x0 0xff9a0800 0x0 0x100>;
1488                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1489                 interrupt-names = "vpu_mmu";
1490                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1491                 clock-names = "aclk", "hclk";
1492                 power-domains = <&power RK3288_PD_VIDEO>;
1493                 #iommu-cells = <0>;
1494         };
1495
1496         hevc_service: hevc-service@ff9c0000 {
1497                 compatible = "rockchip,hevc_service";
1498                 reg = <0x0 0xff9c0000 0x0 0x400>;
1499                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1500                 interrupt-names = "irq_dec";
1501                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1502                         <&cru SCLK_HEVC_CORE>,
1503                         <&cru SCLK_HEVC_CABAC>;
1504                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
1505                         "clk_cabac";
1506                 /*
1507                  * The 4K hevc would also work well with 500/125/300/300,
1508                  * no more err irq and reset request.
1509                  */
1510                 assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1511                                   <&cru SCLK_HEVC_CORE>,
1512                                   <&cru SCLK_HEVC_CABAC>;
1513                 assigned-clock-rates = <400000000>, <100000000>,
1514                                        <300000000>, <300000000>;
1515
1516                 resets = <&cru SRST_HEVC>;
1517                 reset-names = "video";
1518                 power-domains = <&power RK3288_PD_HEVC>;
1519                 rockchip,grf = <&grf>;
1520                 iommus = <&hevc_mmu>;
1521                 iommu_enabled = <1>;
1522                 status = "disabled";
1523                 /* 0 means ion, 1 means drm */
1524                 allocator = <1>;
1525         };
1526
1527         hevc_mmu: iommu@ff9c0440 {
1528                 compatible = "rockchip,iommu";
1529                 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
1530                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1531                 interrupt-names = "hevc_mmu";
1532                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1533                         <&cru SCLK_HEVC_CORE>,
1534                         <&cru SCLK_HEVC_CABAC>;
1535                 clock-names = "aclk", "hclk", "clk_core",
1536                         "clk_cabac";
1537                 power-domains = <&power RK3288_PD_HEVC>;
1538                 #iommu-cells = <0>;
1539         };
1540
1541         gpu: gpu@ffa30000 {
1542                 compatible = "arm,malit764",
1543                              "arm,malit76x",
1544                              "arm,malit7xx",
1545                              "arm,mali-midgard";
1546                 reg = <0x0 0xffa30000 0x0 0x10000>;
1547                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1548                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1549                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1550                 interrupt-names = "JOB", "MMU", "GPU";
1551                 clocks = <&cru ACLK_GPU>;
1552                 clock-names = "clk_mali";
1553                 operating-points-v2 = <&gpu_opp_table>;
1554                 #cooling-cells = <2>; /* min followed by max */
1555                 power-domains = <&power RK3288_PD_GPU>;
1556                 status = "disabled";
1557
1558                 upthreshold = <75>;
1559                 downdifferential = <10>;
1560
1561                 gpu_power_model: power_model {
1562                         compatible = "arm,mali-simple-power-model";
1563                         voltage = <950>;
1564                         frequency = <500>;
1565                         static-power = <300>;
1566                         dynamic-power = <396>;
1567                         ts = <32000 4700 (-80) 2>;
1568                         thermal-zone = "gpu-thermal";
1569                 };
1570         };
1571
1572         gpu_opp_table: opp-table1 {
1573                 compatible = "operating-points-v2";
1574
1575                 opp-100000000 {
1576                         opp-hz = /bits/ 64 <100000000>;
1577                         opp-microvolt = <950000>;
1578                 };
1579                 opp-200000000 {
1580                         opp-hz = /bits/ 64 <200000000>;
1581                         opp-microvolt = <950000>;
1582                 };
1583                 opp-300000000 {
1584                         opp-hz = /bits/ 64 <300000000>;
1585                         opp-microvolt = <1000000>;
1586                 };
1587                 opp-400000000 {
1588                         opp-hz = /bits/ 64 <400000000>;
1589                         opp-microvolt = <1100000>;
1590                 };
1591                 opp-600000000 {
1592                         opp-hz = /bits/ 64 <600000000>;
1593                         opp-microvolt = <1250000>;
1594                 };
1595         };
1596
1597         noc: syscon@ffac0000 {
1598                 compatible = "rockchip,rk3288-noc", "syscon";
1599                 reg = <0x0 0xffac0000 0x0 0x2000>;
1600         };
1601
1602         efuse: efuse@ffb40000 {
1603                 compatible = "rockchip,rockchip-efuse";
1604                 reg = <0x0 0xffb40000 0x0 0x20>;
1605                 #address-cells = <1>;
1606                 #size-cells = <1>;
1607                 clocks = <&cru PCLK_EFUSE256>;
1608                 clock-names = "pclk_efuse";
1609
1610                 cpu_leakage: cpu_leakage@17 {
1611                         reg = <0x17 0x1>;
1612                 };
1613         };
1614
1615         gic: interrupt-controller@ffc01000 {
1616                 compatible = "arm,gic-400";
1617                 interrupt-controller;
1618                 #interrupt-cells = <3>;
1619                 #address-cells = <0>;
1620
1621                 reg = <0x0 0xffc01000 0x0 0x1000>,
1622                       <0x0 0xffc02000 0x0 0x2000>,
1623                       <0x0 0xffc04000 0x0 0x2000>,
1624                       <0x0 0xffc06000 0x0 0x2000>;
1625                 interrupts = <GIC_PPI 9 0xf04>;
1626         };
1627
1628         pinctrl: pinctrl {
1629                 compatible = "rockchip,rk3288-pinctrl";
1630                 rockchip,grf = <&grf>;
1631                 rockchip,pmu = <&pmu>;
1632                 #address-cells = <2>;
1633                 #size-cells = <2>;
1634                 ranges;
1635
1636                 gpio0: gpio0@ff750000 {
1637                         compatible = "rockchip,gpio-bank";
1638                         reg = <0x0 0xff750000 0x0 0x100>;
1639                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1640                         clocks = <&cru PCLK_GPIO0>;
1641
1642                         gpio-controller;
1643                         #gpio-cells = <2>;
1644
1645                         interrupt-controller;
1646                         #interrupt-cells = <2>;
1647                 };
1648
1649                 gpio1: gpio1@ff780000 {
1650                         compatible = "rockchip,gpio-bank";
1651                         reg = <0x0 0xff780000 0x0 0x100>;
1652                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1653                         clocks = <&cru PCLK_GPIO1>;
1654
1655                         gpio-controller;
1656                         #gpio-cells = <2>;
1657
1658                         interrupt-controller;
1659                         #interrupt-cells = <2>;
1660                 };
1661
1662                 gpio2: gpio2@ff790000 {
1663                         compatible = "rockchip,gpio-bank";
1664                         reg = <0x0 0xff790000 0x0 0x100>;
1665                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1666                         clocks = <&cru PCLK_GPIO2>;
1667
1668                         gpio-controller;
1669                         #gpio-cells = <2>;
1670
1671                         interrupt-controller;
1672                         #interrupt-cells = <2>;
1673                 };
1674
1675                 gpio3: gpio3@ff7a0000 {
1676                         compatible = "rockchip,gpio-bank";
1677                         reg = <0x0 0xff7a0000 0x0 0x100>;
1678                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1679                         clocks = <&cru PCLK_GPIO3>;
1680
1681                         gpio-controller;
1682                         #gpio-cells = <2>;
1683
1684                         interrupt-controller;
1685                         #interrupt-cells = <2>;
1686                 };
1687
1688                 gpio4: gpio4@ff7b0000 {
1689                         compatible = "rockchip,gpio-bank";
1690                         reg = <0x0 0xff7b0000 0x0 0x100>;
1691                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1692                         clocks = <&cru PCLK_GPIO4>;
1693
1694                         gpio-controller;
1695                         #gpio-cells = <2>;
1696
1697                         interrupt-controller;
1698                         #interrupt-cells = <2>;
1699                 };
1700
1701                 gpio5: gpio5@ff7c0000 {
1702                         compatible = "rockchip,gpio-bank";
1703                         reg = <0x0 0xff7c0000 0x0 0x100>;
1704                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1705                         clocks = <&cru PCLK_GPIO5>;
1706
1707                         gpio-controller;
1708                         #gpio-cells = <2>;
1709
1710                         interrupt-controller;
1711                         #interrupt-cells = <2>;
1712                 };
1713
1714                 gpio6: gpio6@ff7d0000 {
1715                         compatible = "rockchip,gpio-bank";
1716                         reg = <0x0 0xff7d0000 0x0 0x100>;
1717                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1718                         clocks = <&cru PCLK_GPIO6>;
1719
1720                         gpio-controller;
1721                         #gpio-cells = <2>;
1722
1723                         interrupt-controller;
1724                         #interrupt-cells = <2>;
1725                 };
1726
1727                 gpio7: gpio7@ff7e0000 {
1728                         compatible = "rockchip,gpio-bank";
1729                         reg = <0x0 0xff7e0000 0x0 0x100>;
1730                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1731                         clocks = <&cru PCLK_GPIO7>;
1732
1733                         gpio-controller;
1734                         #gpio-cells = <2>;
1735
1736                         interrupt-controller;
1737                         #interrupt-cells = <2>;
1738                 };
1739
1740                 gpio8: gpio8@ff7f0000 {
1741                         compatible = "rockchip,gpio-bank";
1742                         reg = <0x0 0xff7f0000 0x0 0x100>;
1743                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1744                         clocks = <&cru PCLK_GPIO8>;
1745
1746                         gpio-controller;
1747                         #gpio-cells = <2>;
1748
1749                         interrupt-controller;
1750                         #interrupt-cells = <2>;
1751                 };
1752
1753                 hdmi {
1754                         hdmi_ddc: hdmi-ddc {
1755                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1756                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1757                         };
1758                 };
1759
1760                 pcfg_pull_up: pcfg-pull-up {
1761                         bias-pull-up;
1762                 };
1763
1764                 pcfg_pull_down: pcfg-pull-down {
1765                         bias-pull-down;
1766                 };
1767
1768                 pcfg_pull_none: pcfg-pull-none {
1769                         bias-disable;
1770                 };
1771
1772                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1773                         bias-disable;
1774                         drive-strength = <12>;
1775                 };
1776
1777                 sleep {
1778                         global_pwroff: global-pwroff {
1779                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1780                         };
1781
1782                         ddrio_pwroff: ddrio-pwroff {
1783                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1784                         };
1785
1786                         ddr0_retention: ddr0-retention {
1787                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1788                         };
1789
1790                         ddr1_retention: ddr1-retention {
1791                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1792                         };
1793                 };
1794
1795                 edp {
1796                         edp_hpd: edp-hpd {
1797                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1798                         };
1799                 };
1800
1801                 i2c0 {
1802                         i2c0_xfer: i2c0-xfer {
1803                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1804                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1805                         };
1806                 };
1807
1808                 i2c1 {
1809                         i2c1_xfer: i2c1-xfer {
1810                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1811                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1812                         };
1813                 };
1814
1815                 i2c2 {
1816                         i2c2_xfer: i2c2-xfer {
1817                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1818                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1819                         };
1820                 };
1821
1822                 i2c3 {
1823                         i2c3_xfer: i2c3-xfer {
1824                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1825                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1826                         };
1827                 };
1828
1829                 i2c4 {
1830                         i2c4_xfer: i2c4-xfer {
1831                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1832                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1833                         };
1834                 };
1835
1836                 i2c5 {
1837                         i2c5_xfer: i2c5-xfer {
1838                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1839                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1840                         };
1841                 };
1842
1843                 i2s0 {
1844                         i2s0_bus: i2s0-bus {
1845                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1846                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1847                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1848                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1849                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1850                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1851                         };
1852                 };
1853
1854                 lcdc0 {
1855                         lcdc0_ctl: lcdc0-ctl {
1856                                 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1857                                                 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1858                                                 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1859                                                 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1860                         };
1861                 };
1862
1863                 sdmmc {
1864                         sdmmc_clk: sdmmc-clk {
1865                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1866                         };
1867
1868                         sdmmc_cmd: sdmmc-cmd {
1869                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1870                         };
1871
1872                         sdmmc_cd: sdmmc-cd {
1873                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1874                         };
1875
1876                         sdmmc_bus1: sdmmc-bus1 {
1877                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1878                         };
1879
1880                         sdmmc_bus4: sdmmc-bus4 {
1881                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1882                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1883                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1884                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1885                         };
1886                 };
1887
1888                 sdio0 {
1889                         sdio0_bus1: sdio0-bus1 {
1890                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1891                         };
1892
1893                         sdio0_bus4: sdio0-bus4 {
1894                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1895                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1896                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1897                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1898                         };
1899
1900                         sdio0_cmd: sdio0-cmd {
1901                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1902                         };
1903
1904                         sdio0_clk: sdio0-clk {
1905                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1906                         };
1907
1908                         sdio0_cd: sdio0-cd {
1909                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1910                         };
1911
1912                         sdio0_wp: sdio0-wp {
1913                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1914                         };
1915
1916                         sdio0_pwr: sdio0-pwr {
1917                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1918                         };
1919
1920                         sdio0_bkpwr: sdio0-bkpwr {
1921                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1922                         };
1923
1924                         sdio0_int: sdio0-int {
1925                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1926                         };
1927                 };
1928
1929                 sdio1 {
1930                         sdio1_bus1: sdio1-bus1 {
1931                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1932                         };
1933
1934                         sdio1_bus4: sdio1-bus4 {
1935                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1936                                                 <3 25 4 &pcfg_pull_up>,
1937                                                 <3 26 4 &pcfg_pull_up>,
1938                                                 <3 27 4 &pcfg_pull_up>;
1939                         };
1940
1941                         sdio1_cd: sdio1-cd {
1942                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1943                         };
1944
1945                         sdio1_wp: sdio1-wp {
1946                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1947                         };
1948
1949                         sdio1_bkpwr: sdio1-bkpwr {
1950                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1951                         };
1952
1953                         sdio1_int: sdio1-int {
1954                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1955                         };
1956
1957                         sdio1_cmd: sdio1-cmd {
1958                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1959                         };
1960
1961                         sdio1_clk: sdio1-clk {
1962                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1963                         };
1964
1965                         sdio1_pwr: sdio1-pwr {
1966                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1967                         };
1968                 };
1969
1970                 emmc {
1971                         emmc_clk: emmc-clk {
1972                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1973                         };
1974
1975                         emmc_cmd: emmc-cmd {
1976                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1977                         };
1978
1979                         emmc_pwr: emmc-pwr {
1980                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1981                         };
1982
1983                         emmc_bus1: emmc-bus1 {
1984                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1985                         };
1986
1987                         emmc_bus4: emmc-bus4 {
1988                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1989                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1990                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1991                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1992                         };
1993
1994                         emmc_bus8: emmc-bus8 {
1995                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1996                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1997                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1998                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1999                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
2000                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
2001                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
2002                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
2003                         };
2004                 };
2005
2006                 spi0 {
2007                         spi0_clk: spi0-clk {
2008                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
2009                         };
2010                         spi0_cs0: spi0-cs0 {
2011                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
2012                         };
2013                         spi0_tx: spi0-tx {
2014                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
2015                         };
2016                         spi0_rx: spi0-rx {
2017                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
2018                         };
2019                         spi0_cs1: spi0-cs1 {
2020                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
2021                         };
2022                 };
2023                 spi1 {
2024                         spi1_clk: spi1-clk {
2025                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
2026                         };
2027                         spi1_cs0: spi1-cs0 {
2028                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
2029                         };
2030                         spi1_rx: spi1-rx {
2031                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
2032                         };
2033                         spi1_tx: spi1-tx {
2034                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
2035                         };
2036                 };
2037
2038                 spi2 {
2039                         spi2_cs1: spi2-cs1 {
2040                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
2041                         };
2042                         spi2_clk: spi2-clk {
2043                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
2044                         };
2045                         spi2_cs0: spi2-cs0 {
2046                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
2047                         };
2048                         spi2_rx: spi2-rx {
2049                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
2050                         };
2051                         spi2_tx: spi2-tx {
2052                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
2053                         };
2054                 };
2055
2056                 uart0 {
2057                         uart0_xfer: uart0-xfer {
2058                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
2059                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
2060                         };
2061
2062                         uart0_cts: uart0-cts {
2063                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
2064                         };
2065
2066                         uart0_rts: uart0-rts {
2067                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
2068                         };
2069                 };
2070
2071                 uart1 {
2072                         uart1_xfer: uart1-xfer {
2073                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
2074                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
2075                         };
2076
2077                         uart1_cts: uart1-cts {
2078                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
2079                         };
2080
2081                         uart1_rts: uart1-rts {
2082                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
2083                         };
2084                 };
2085
2086                 uart2 {
2087                         uart2_xfer: uart2-xfer {
2088                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
2089                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
2090                         };
2091                         /* no rts / cts for uart2 */
2092                 };
2093
2094                 uart3 {
2095                         uart3_xfer: uart3-xfer {
2096                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
2097                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
2098                         };
2099
2100                         uart3_cts: uart3-cts {
2101                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
2102                         };
2103
2104                         uart3_rts: uart3-rts {
2105                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
2106                         };
2107                 };
2108
2109                 uart4 {
2110                         uart4_xfer: uart4-xfer {
2111                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
2112                                                 <5 13 3 &pcfg_pull_none>;
2113                         };
2114
2115                         uart4_cts: uart4-cts {
2116                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
2117                         };
2118
2119                         uart4_rts: uart4-rts {
2120                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
2121                         };
2122                 };
2123
2124                 tsadc {
2125                         otp_gpio: otp-gpio {
2126                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
2127                         };
2128
2129                         otp_out: otp-out {
2130                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
2131                         };
2132                 };
2133
2134                 pwm0 {
2135                         pwm0_pin: pwm0-pin {
2136                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
2137                         };
2138                 };
2139
2140                 pwm1 {
2141                         pwm1_pin: pwm1-pin {
2142                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
2143                         };
2144                 };
2145
2146                 pwm2 {
2147                         pwm2_pin: pwm2-pin {
2148                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
2149                         };
2150                 };
2151
2152                 pwm3 {
2153                         pwm3_pin: pwm3-pin {
2154                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
2155                         };
2156                 };
2157
2158                 gmac {
2159                         rgmii_pins: rgmii-pins {
2160                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
2161                                                 <3 31 3 &pcfg_pull_none>,
2162                                                 <3 26 3 &pcfg_pull_none>,
2163                                                 <3 27 3 &pcfg_pull_none>,
2164                                                 <3 28 3 &pcfg_pull_none_12ma>,
2165                                                 <3 29 3 &pcfg_pull_none_12ma>,
2166                                                 <3 24 3 &pcfg_pull_none_12ma>,
2167                                                 <3 25 3 &pcfg_pull_none_12ma>,
2168                                                 <4 0 3 &pcfg_pull_none>,
2169                                                 <4 5 3 &pcfg_pull_none>,
2170                                                 <4 6 3 &pcfg_pull_none>,
2171                                                 <4 9 3 &pcfg_pull_none_12ma>,
2172                                                 <4 4 3 &pcfg_pull_none_12ma>,
2173                                                 <4 1 3 &pcfg_pull_none>,
2174                                                 <4 3 3 &pcfg_pull_none>;
2175                         };
2176
2177                         rmii_pins: rmii-pins {
2178                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
2179                                                 <3 31 3 &pcfg_pull_none>,
2180                                                 <3 28 3 &pcfg_pull_none>,
2181                                                 <3 29 3 &pcfg_pull_none>,
2182                                                 <4 0 3 &pcfg_pull_none>,
2183                                                 <4 5 3 &pcfg_pull_none>,
2184                                                 <4 4 3 &pcfg_pull_none>,
2185                                                 <4 1 3 &pcfg_pull_none>,
2186                                                 <4 2 3 &pcfg_pull_none>,
2187                                                 <4 3 3 &pcfg_pull_none>;
2188                         };
2189                 };
2190
2191                 spdif {
2192                         spdif_tx: spdif-tx {
2193                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
2194                         };
2195                 };
2196
2197                 cif {
2198                         cif_dvp_d2d9: cif-dvp-d2d9 {
2199                                 rockchip,pins = <2 0 RK_FUNC_1 &pcfg_pull_none>,
2200                                                 <2 1 RK_FUNC_1 &pcfg_pull_none>,
2201                                                 <2 2 RK_FUNC_1 &pcfg_pull_none>,
2202                                                 <2 3 RK_FUNC_1 &pcfg_pull_none>,
2203                                                 <2 4 RK_FUNC_1 &pcfg_pull_none>,
2204                                                 <2 5 RK_FUNC_1 &pcfg_pull_none>,
2205                                                 <2 6 RK_FUNC_1 &pcfg_pull_none>,
2206                                                 <2 7 RK_FUNC_1 &pcfg_pull_none>,
2207                                                 <2 8 RK_FUNC_1 &pcfg_pull_none>,
2208                                                 <2 9 RK_FUNC_1 &pcfg_pull_none>,
2209                                                 <2 11 RK_FUNC_1 &pcfg_pull_none>;
2210                         };
2211                 };
2212
2213                 isp_pin {
2214                         isp_mipi: isp-mipi {
2215                                 rockchip,pins =
2216                                         /* cif_clkout */
2217                                         <2 11 RK_FUNC_1 &pcfg_pull_none>;
2218                         };
2219
2220                         isp_dvp_d2d9: isp-d2d9 {
2221                                 rockchip,pins =
2222                                         /* cif_data2 ... cif_data9 */
2223                                         <2 0 RK_FUNC_1 &pcfg_pull_none>,
2224                                         <2 1 RK_FUNC_1 &pcfg_pull_none>,
2225                                         <2 2 RK_FUNC_1 &pcfg_pull_none>,
2226                                         <2 3 RK_FUNC_1 &pcfg_pull_none>,
2227                                         <2 4 RK_FUNC_1 &pcfg_pull_none>,
2228                                         <2 5 RK_FUNC_1 &pcfg_pull_none>,
2229                                         <2 6 RK_FUNC_1 &pcfg_pull_none>,
2230                                         <2 7 RK_FUNC_1 &pcfg_pull_none>,
2231                                         /* cif_sync, cif_href */
2232                                         <2 8 RK_FUNC_1 &pcfg_pull_none>,
2233                                         <2 9 RK_FUNC_1 &pcfg_pull_none>,
2234                                         /* cif_clkin, cif_clkout */
2235                                         <2 10 RK_FUNC_1 &pcfg_pull_none>,
2236                                         <2 11 RK_FUNC_1 &pcfg_pull_none>;
2237                         };
2238
2239                         isp_dvp_d0d1: isp-d0d1 {
2240                                 rockchip,pins =
2241                                         /* cif_data0, cif_data1 */
2242                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
2243                                         <2 13 RK_FUNC_1 &pcfg_pull_none>;
2244                         };
2245
2246                         isp_dvp_d10d11: isp-d10d11 {
2247                                 rockchip,pins =
2248                                         /* cif_data10, cif_data11 */
2249                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
2250                                         <2 15 RK_FUNC_1 &pcfg_pull_none>;
2251                         };
2252
2253                         isp_dvp_d0d7: isp-d0d7 {
2254                                 rockchip,pins =
2255                                         /* cif_data0 ... cif_data7 */
2256                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
2257                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
2258                                         <2 0 RK_FUNC_1 &pcfg_pull_none>,
2259                                         <2 1 RK_FUNC_1 &pcfg_pull_none>,
2260                                         <2 2 RK_FUNC_1 &pcfg_pull_none>,
2261                                         <2 3 RK_FUNC_1 &pcfg_pull_none>,
2262                                         <2 4 RK_FUNC_1 &pcfg_pull_none>,
2263                                         <2 5 RK_FUNC_1 &pcfg_pull_none>;
2264                         };
2265
2266                         isp_shutter: isp-shutter {
2267                                 rockchip,pins =
2268                                         /* SHUTTEREN, SHUTTERTRIG */
2269                                         <7 12 RK_FUNC_2 &pcfg_pull_none>,
2270                                         <7 15 RK_FUNC_2 &pcfg_pull_none>;
2271                         };
2272
2273                         isp_flash_trigger: isp-flash-trigger {
2274                                 rockchip,pins =
2275                                         /* ISP_FLASHTRIGOU */
2276                                         <7 13 RK_FUNC_2 &pcfg_pull_none>;
2277                         };
2278
2279                         isp_prelight: isp-prelight {
2280                                 rockchip,pins =
2281                                         /* ISP_PRELIGHTTRIG */
2282                                         <7 14 RK_FUNC_2 &pcfg_pull_none>;
2283                         };
2284
2285                         isp_flash_trigger_as_gpio: isp-flash-trigger-as-gpio {
2286                                 rockchip,pins =
2287                                         /* ISP_FLASHTRIGOU */
2288                                         <7 13 RK_FUNC_2 &pcfg_pull_none>;
2289                         };
2290                 };
2291
2292         };
2293         rockchip_suspend: rockchip-suspend {
2294                 compatible = "rockchip,pm-rk3288";
2295                 status = "disabled";
2296                 rockchip,sleep-mode-config = <
2297                         (0
2298                         |RKPM_CTR_PWR_DMNS
2299                         |RKPM_CTR_GTCLKS
2300                         |RKPM_CTR_PLLS
2301                         |RKPM_CTR_ARMOFF_LPMD
2302                         )
2303                 >;
2304                 rockchip,wakeup-config = <
2305                         (0
2306                         | RKPM_GPIO_WKUP_EN
2307                         )
2308                 >;
2309                 rockchip,pwm-regulator-config = <
2310                         (0
2311                         | PWM2_REGULATOR_EN
2312                         )
2313                 >;
2314         };
2315 };