arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include <dt-bindings/soc/rockchip_boot-mode.h>
  49 #include "skeleton.dtsi"
  50
  51 / {
  52         compatible = "rockchip,rk3288";
  53
  54         interrupt-parent = <&gic>;
  55
  56         aliases {
  57                 i2c0 = &i2c0;
  58                 i2c1 = &i2c1;
  59                 i2c2 = &i2c2;
  60                 i2c3 = &i2c3;
  61                 i2c4 = &i2c4;
  62                 i2c5 = &i2c5;
  63                 mshc0 = &emmc;
  64                 mshc1 = &sdmmc;
  65                 mshc2 = &sdio0;
  66                 mshc3 = &sdio1;
  67                 serial0 = &uart0;
  68                 serial1 = &uart1;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71                 serial4 = &uart4;
  72                 spi0 = &spi0;
  73                 spi1 = &spi1;
  74                 spi2 = &spi2;
  75         };
  76
  77         arm-pmu {
  78                 compatible = "arm,cortex-a12-pmu";
  79                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  80                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  82                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  83                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  84         };
  85
  86         cpus {
  87                 #address-cells = <1>;
  88                 #size-cells = <0>;
  89                 enable-method = "rockchip,rk3066-smp";
  90                 rockchip,pmu = <&pmu>;
  91
  92                 cpu0: cpu@500 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a12";
  95                         reg = <0x500>;
  96                         resets = <&cru SRST_CORE0>;
  97                         operating-points = <
  98                                 /* KHz    uV */
  99                                 1608000 1350000
 100                                 1512000 1300000
 101                                 1416000 1200000
 102                                 1200000 1100000
 103                                 1008000 1050000
 104                                  816000 1000000
 105                                  696000  950000
 106                                  600000  900000
 107                                  408000  900000
 108                                  312000  900000
 109                                  216000  900000
 110                                  126000  900000
 111                         >;
 112                         #cooling-cells = <2>; /* min followed by max */
 113                         clock-latency = <40000>;
 114                         clocks = <&cru ARMCLK>;
 115                 };
 116                 cpu1: cpu@501 {
 117                         device_type = "cpu";
 118                         compatible = "arm,cortex-a12";
 119                         reg = <0x501>;
 120                         resets = <&cru SRST_CORE1>;
 121                 };
 122                 cpu2: cpu@502 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a12";
 125                         reg = <0x502>;
 126                         resets = <&cru SRST_CORE2>;
 127                 };
 128                 cpu3: cpu@503 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a12";
 131                         reg = <0x503>;
 132                         resets = <&cru SRST_CORE3>;
 133                 };
 134         };
 135
 136         amba {
 137                 compatible = "arm,amba-bus";
 138                 #address-cells = <1>;
 139                 #size-cells = <1>;
 140                 ranges;
 141
 142                 dmac_peri: dma-controller@ff250000 {
 143                         compatible = "arm,pl330", "arm,primecell";
 144                         reg = <0xff250000 0x4000>;
 145                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 146                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 147                         #dma-cells = <1>;
 148                         arm,pl330-broken-no-flushp;
 149                         peripherals-req-type-burst;
 150                         clocks = <&cru ACLK_DMAC2>;
 151                         clock-names = "apb_pclk";
 152                 };
 153
 154                 dmac_bus_ns: dma-controller@ff600000 {
 155                         compatible = "arm,pl330", "arm,primecell";
 156                         reg = <0xff600000 0x4000>;
 157                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 158                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 159                         #dma-cells = <1>;
 160                         arm,pl330-broken-no-flushp;
 161                         peripherals-req-type-burst;
 162                         clocks = <&cru ACLK_DMAC1>;
 163                         clock-names = "apb_pclk";
 164                         status = "disabled";
 165                 };
 166
 167                 dmac_bus_s: dma-controller@ffb20000 {
 168                         compatible = "arm,pl330", "arm,primecell";
 169                         reg = <0xffb20000 0x4000>;
 170                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 171                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 172                         #dma-cells = <1>;
 173                         arm,pl330-broken-no-flushp;
 174                         peripherals-req-type-burst;
 175                         clocks = <&cru ACLK_DMAC1>;
 176                         clock-names = "apb_pclk";
 177                 };
 178         };
 179
 180         reserved-memory {
 181                 #address-cells = <1>;
 182                 #size-cells = <1>;
 183                 ranges;
 184
 185                 /*
 186                  * The rk3288 cannot use the memory area above 0xfe000000
 187                  * for dma operations for some reason. While there is
 188                  * probably a better solution available somewhere, we
 189                  * haven't found it yet and while devices with 2GB of ram
 190                  * are not affected, this issue prevents 4GB from booting.
 191                  * So to make these devices at least bootable, block
 192                  * this area for the time being until the real solution
 193                  * is found.
 194                  */
 195                 dma-unusable@fe000000 {
 196                         reg = <0xfe000000 0x1000000>;
 197                 };
 198         };
 199
 200         xin24m: oscillator {
 201                 compatible = "fixed-clock";
 202                 clock-frequency = <24000000>;
 203                 clock-output-names = "xin24m";
 204                 #clock-cells = <0>;
 205         };
 206
 207         timer {
 208                 compatible = "arm,armv7-timer";
 209                 arm,cpu-registers-not-fw-configured;
 210                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 211                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 212                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 213                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 214                 clock-frequency = <24000000>;
 215         };
 216
 217         timer: timer@ff810000 {
 218                 compatible = "rockchip,rk3288-timer";
 219                 reg = <0xff810000 0x20>;
 220                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 221                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 222                 clock-names = "timer", "pclk";
 223         };
 224
 225         display-subsystem {
 226                 compatible = "rockchip,display-subsystem";
 227                 ports = <&vopl_out>, <&vopb_out>;
 228         };
 229
 230         sdmmc: dwmmc@ff0c0000 {
 231                 compatible = "rockchip,rk3288-dw-mshc";
 232                 clock-freq-min-max = <400000 150000000>;
 233                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 234                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 235                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 236                 fifo-depth = <0x100>;
 237                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 238                 reg = <0xff0c0000 0x4000>;
 239                 status = "disabled";
 240         };
 241
 242         sdio0: dwmmc@ff0d0000 {
 243                 compatible = "rockchip,rk3288-dw-mshc";
 244                 clock-freq-min-max = <400000 150000000>;
 245                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 246                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 247                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 248                 fifo-depth = <0x100>;
 249                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 250                 reg = <0xff0d0000 0x4000>;
 251                 status = "disabled";
 252         };
 253
 254         sdio1: dwmmc@ff0e0000 {
 255                 compatible = "rockchip,rk3288-dw-mshc";
 256                 clock-freq-min-max = <400000 150000000>;
 257                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 258                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 259                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 260                 fifo-depth = <0x100>;
 261                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 262                 reg = <0xff0e0000 0x4000>;
 263                 status = "disabled";
 264         };
 265
 266         emmc: dwmmc@ff0f0000 {
 267                 compatible = "rockchip,rk3288-dw-mshc";
 268                 clock-freq-min-max = <400000 150000000>;
 269                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 270                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 271                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 272                 fifo-depth = <0x100>;
 273                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 274                 reg = <0xff0f0000 0x4000>;
 275                 status = "disabled";
 276                 supports-emmc;
 277         };
 278
 279         saradc: saradc@ff100000 {
 280                 compatible = "rockchip,saradc";
 281                 reg = <0xff100000 0x100>;
 282                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 283                 #io-channel-cells = <1>;
 284                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 285                 clock-names = "saradc", "apb_pclk";
 286                 status = "disabled";
 287         };
 288
 289         spi0: spi@ff110000 {
 290                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 291                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 292                 clock-names = "spiclk", "apb_pclk";
 293                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 294                 dma-names = "tx", "rx";
 295                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 296                 pinctrl-names = "default";
 297                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 298                 reg = <0xff110000 0x1000>;
 299                 #address-cells = <1>;
 300                 #size-cells = <0>;
 301                 status = "disabled";
 302         };
 303
 304         spi1: spi@ff120000 {
 305                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 306                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 307                 clock-names = "spiclk", "apb_pclk";
 308                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 309                 dma-names = "tx", "rx";
 310                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 311                 pinctrl-names = "default";
 312                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 313                 reg = <0xff120000 0x1000>;
 314                 #address-cells = <1>;
 315                 #size-cells = <0>;
 316                 status = "disabled";
 317         };
 318
 319         spi2: spi@ff130000 {
 320                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 321                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 322                 clock-names = "spiclk", "apb_pclk";
 323                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 324                 dma-names = "tx", "rx";
 325                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 326                 pinctrl-names = "default";
 327                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 328                 reg = <0xff130000 0x1000>;
 329                 #address-cells = <1>;
 330                 #size-cells = <0>;
 331                 status = "disabled";
 332         };
 333
 334         i2c1: i2c@ff140000 {
 335                 compatible = "rockchip,rk3288-i2c";
 336                 reg = <0xff140000 0x1000>;
 337                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 338                 #address-cells = <1>;
 339                 #size-cells = <0>;
 340                 clock-names = "i2c";
 341                 clocks = <&cru PCLK_I2C1>;
 342                 pinctrl-names = "default";
 343                 pinctrl-0 = <&i2c1_xfer>;
 344                 status = "disabled";
 345         };
 346
 347         i2c3: i2c@ff150000 {
 348                 compatible = "rockchip,rk3288-i2c";
 349                 reg = <0xff150000 0x1000>;
 350                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 351                 #address-cells = <1>;
 352                 #size-cells = <0>;
 353                 clock-names = "i2c";
 354                 clocks = <&cru PCLK_I2C3>;
 355                 pinctrl-names = "default";
 356                 pinctrl-0 = <&i2c3_xfer>;
 357                 status = "disabled";
 358         };
 359
 360         i2c4: i2c@ff160000 {
 361                 compatible = "rockchip,rk3288-i2c";
 362                 reg = <0xff160000 0x1000>;
 363                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 364                 #address-cells = <1>;
 365                 #size-cells = <0>;
 366                 clock-names = "i2c";
 367                 clocks = <&cru PCLK_I2C4>;
 368                 pinctrl-names = "default";
 369                 pinctrl-0 = <&i2c4_xfer>;
 370                 status = "disabled";
 371         };
 372
 373         i2c5: i2c@ff170000 {
 374                 compatible = "rockchip,rk3288-i2c";
 375                 reg = <0xff170000 0x1000>;
 376                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 377                 #address-cells = <1>;
 378                 #size-cells = <0>;
 379                 clock-names = "i2c";
 380                 clocks = <&cru PCLK_I2C5>;
 381                 pinctrl-names = "default";
 382                 pinctrl-0 = <&i2c5_xfer>;
 383                 status = "disabled";
 384         };
 385
 386         uart0: serial@ff180000 {
 387                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 388                 reg = <0xff180000 0x100>;
 389                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 390                 reg-shift = <2>;
 391                 reg-io-width = <4>;
 392                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 393                 clock-names = "baudclk", "apb_pclk";
 394                 pinctrl-names = "default";
 395                 pinctrl-0 = <&uart0_xfer>;
 396                 status = "disabled";
 397         };
 398
 399         uart1: serial@ff190000 {
 400                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 401                 reg = <0xff190000 0x100>;
 402                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 403                 reg-shift = <2>;
 404                 reg-io-width = <4>;
 405                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 406                 clock-names = "baudclk", "apb_pclk";
 407                 pinctrl-names = "default";
 408                 pinctrl-0 = <&uart1_xfer>;
 409                 status = "disabled";
 410         };
 411
 412         uart2: serial@ff690000 {
 413                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 414                 reg = <0xff690000 0x100>;
 415                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 416                 reg-shift = <2>;
 417                 reg-io-width = <4>;
 418                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 419                 clock-names = "baudclk", "apb_pclk";
 420                 pinctrl-names = "default";
 421                 pinctrl-0 = <&uart2_xfer>;
 422                 status = "disabled";
 423         };
 424
 425         uart3: serial@ff1b0000 {
 426                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 427                 reg = <0xff1b0000 0x100>;
 428                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 429                 reg-shift = <2>;
 430                 reg-io-width = <4>;
 431                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 432                 clock-names = "baudclk", "apb_pclk";
 433                 pinctrl-names = "default";
 434                 pinctrl-0 = <&uart3_xfer>;
 435                 status = "disabled";
 436         };
 437
 438         uart4: serial@ff1c0000 {
 439                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 440                 reg = <0xff1c0000 0x100>;
 441                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 442                 reg-shift = <2>;
 443                 reg-io-width = <4>;
 444                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 445                 clock-names = "baudclk", "apb_pclk";
 446                 pinctrl-names = "default";
 447                 pinctrl-0 = <&uart4_xfer>;
 448                 status = "disabled";
 449         };
 450
 451         thermal-zones {
 452                 #include "rk3288-thermal.dtsi"
 453         };
 454
 455         tsadc: tsadc@ff280000 {
 456                 compatible = "rockchip,rk3288-tsadc";
 457                 reg = <0xff280000 0x100>;
 458                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 459                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 460                 clock-names = "tsadc", "apb_pclk";
 461                 resets = <&cru SRST_TSADC>;
 462                 reset-names = "tsadc-apb";
 463                 pinctrl-names = "init", "default", "sleep";
 464                 pinctrl-0 = <&otp_gpio>;
 465                 pinctrl-1 = <&otp_out>;
 466                 pinctrl-2 = <&otp_gpio>;
 467                 #thermal-sensor-cells = <1>;
 468                 rockchip,hw-tshut-temp = <95000>;
 469                 status = "disabled";
 470         };
 471
 472         gmac: ethernet@ff290000 {
 473                 compatible = "rockchip,rk3288-gmac";
 474                 reg = <0xff290000 0x10000>;
 475                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 476                 interrupt-names = "macirq";
 477                 rockchip,grf = <&grf>;
 478                 clocks = <&cru SCLK_MAC>,
 479                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 480                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 481                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 482                 clock-names = "stmmaceth",
 483                         "mac_clk_rx", "mac_clk_tx",
 484                         "clk_mac_ref", "clk_mac_refout",
 485                         "aclk_mac", "pclk_mac";
 486                 resets = <&cru SRST_MAC>;
 487                 reset-names = "stmmaceth";
 488                 max-speed = <100>;
 489                 status = "disabled";
 490         };
 491
 492         usb_host0_ehci: usb@ff500000 {
 493                 compatible = "generic-ehci";
 494                 reg = <0xff500000 0x100>;
 495                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 496                 clocks = <&cru HCLK_USBHOST0>;
 497                 clock-names = "usbhost";
 498                 phys = <&usbphy1>;
 499                 phy-names = "usb";
 500                 status = "disabled";
 501         };
 502
 503         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 504
 505         usb_host1: usb@ff540000 {
 506                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 507                                 "snps,dwc2";
 508                 reg = <0xff540000 0x40000>;
 509                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 510                 clocks = <&cru HCLK_USBHOST1>;
 511                 clock-names = "otg";
 512                 dr_mode = "host";
 513                 phys = <&usbphy2>;
 514                 phy-names = "usb2-phy";
 515                 status = "disabled";
 516         };
 517
 518         usb_otg: usb@ff580000 {
 519                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 520                                 "snps,dwc2";
 521                 reg = <0xff580000 0x40000>;
 522                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 523                 clocks = <&cru HCLK_OTG0>;
 524                 clock-names = "otg";
 525                 dr_mode = "otg";
 526                 g-np-tx-fifo-size = <16>;
 527                 g-rx-fifo-size = <275>;
 528                 g-tx-fifo-size = <256 128 128 64 64 32>;
 529                 g-use-dma;
 530                 phys = <&usbphy0>;
 531                 phy-names = "usb2-phy";
 532                 status = "disabled";
 533         };
 534
 535         usb_hsic: usb@ff5c0000 {
 536                 compatible = "generic-ehci";
 537                 reg = <0xff5c0000 0x100>;
 538                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 539                 clocks = <&cru HCLK_HSIC>;
 540                 clock-names = "usbhost";
 541                 status = "disabled";
 542         };
 543
 544         i2c0: i2c@ff650000 {
 545                 compatible = "rockchip,rk3288-i2c";
 546                 reg = <0xff650000 0x1000>;
 547                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 548                 #address-cells = <1>;
 549                 #size-cells = <0>;
 550                 clock-names = "i2c";
 551                 clocks = <&cru PCLK_I2C0>;
 552                 pinctrl-names = "default";
 553                 pinctrl-0 = <&i2c0_xfer>;
 554                 status = "disabled";
 555         };
 556
 557         i2c2: i2c@ff660000 {
 558                 compatible = "rockchip,rk3288-i2c";
 559                 reg = <0xff660000 0x1000>;
 560                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 561                 #address-cells = <1>;
 562                 #size-cells = <0>;
 563                 clock-names = "i2c";
 564                 clocks = <&cru PCLK_I2C2>;
 565                 pinctrl-names = "default";
 566                 pinctrl-0 = <&i2c2_xfer>;
 567                 status = "disabled";
 568         };
 569
 570         pwm0: pwm@ff680000 {
 571                 compatible = "rockchip,rk3288-pwm";
 572                 reg = <0xff680000 0x10>;
 573                 #pwm-cells = <3>;
 574                 pinctrl-names = "default";
 575                 pinctrl-0 = <&pwm0_pin>;
 576                 clocks = <&cru PCLK_PWM>;
 577                 clock-names = "pwm";
 578                 status = "disabled";
 579         };
 580
 581         pwm1: pwm@ff680010 {
 582                 compatible = "rockchip,rk3288-pwm";
 583                 reg = <0xff680010 0x10>;
 584                 #pwm-cells = <3>;
 585                 pinctrl-names = "default";
 586                 pinctrl-0 = <&pwm1_pin>;
 587                 clocks = <&cru PCLK_PWM>;
 588                 clock-names = "pwm";
 589                 status = "disabled";
 590         };
 591
 592         pwm2: pwm@ff680020 {
 593                 compatible = "rockchip,rk3288-pwm";
 594                 reg = <0xff680020 0x10>;
 595                 #pwm-cells = <3>;
 596                 pinctrl-names = "default";
 597                 pinctrl-0 = <&pwm2_pin>;
 598                 clocks = <&cru PCLK_PWM>;
 599                 clock-names = "pwm";
 600                 status = "disabled";
 601         };
 602
 603         pwm3: pwm@ff680030 {
 604                 compatible = "rockchip,rk3288-pwm";
 605                 reg = <0xff680030 0x10>;
 606                 #pwm-cells = <2>;
 607                 pinctrl-names = "default";
 608                 pinctrl-0 = <&pwm3_pin>;
 609                 clocks = <&cru PCLK_PWM>;
 610                 clock-names = "pwm";
 611                 status = "disabled";
 612         };
 613
 614         bus_intmem@ff700000 {
 615                 compatible = "mmio-sram";
 616                 reg = <0xff700000 0x18000>;
 617                 #address-cells = <1>;
 618                 #size-cells = <1>;
 619                 ranges = <0 0xff700000 0x18000>;
 620                 smp-sram@0 {
 621                         compatible = "rockchip,rk3066-smp-sram";
 622                         reg = <0x00 0x10>;
 623                 };
 624         };
 625
 626         sram@ff720000 {
 627                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 628                 reg = <0xff720000 0x1000>;
 629         };
 630
 631         qos_gpu_r: qos@ffaa0000 {
 632                 compatible = "syscon";
 633                 reg = <0xffaa0000 0x20>;
 634         };
 635
 636         qos_gpu_w: qos@ffaa0080 {
 637                 compatible = "syscon";
 638                 reg = <0xffaa0080 0x20>;
 639         };
 640
 641         qos_vio1_vop: qos@ffad0000 {
 642                 compatible = "syscon";
 643                 reg = <0xffad0000 0x20>;
 644         };
 645
 646         qos_vio1_isp_w0: qos@ffad0100 {
 647                 compatible = "syscon";
 648                 reg = <0xffad0100 0x20>;
 649         };
 650
 651         qos_vio1_isp_w1: qos@ffad0180 {
 652                 compatible = "syscon";
 653                 reg = <0xffad0180 0x20>;
 654         };
 655
 656         qos_vio0_vop: qos@ffad0400 {
 657                 compatible = "syscon";
 658                 reg = <0xffad0400 0x20>;
 659         };
 660
 661         qos_vio0_vip: qos@ffad0480 {
 662                 compatible = "syscon";
 663                 reg = <0xffad0480 0x20>;
 664         };
 665
 666         qos_vio0_iep: qos@ffad0500 {
 667                 compatible = "syscon";
 668                 reg = <0xffad0500 0x20>;
 669         };
 670
 671         qos_vio2_rga_r: qos@ffad0800 {
 672                 compatible = "syscon";
 673                 reg = <0xffad0800 0x20>;
 674         };
 675
 676         qos_vio2_rga_w: qos@ffad0880 {
 677                 compatible = "syscon";
 678                 reg = <0xffad0880 0x20>;
 679         };
 680
 681         qos_vio1_isp_r: qos@ffad0900 {
 682                 compatible = "syscon";
 683                 reg = <0xffad0900 0x20>;
 684         };
 685
 686         qos_video: qos@ffae0000 {
 687                 compatible = "syscon";
 688                 reg = <0xffae0000 0x20>;
 689         };
 690
 691         qos_hevc_r: qos@ffaf0000 {
 692                 compatible = "syscon";
 693                 reg = <0xffaf0000 0x20>;
 694         };
 695
 696         qos_hevc_w: qos@ffaf0080 {
 697                 compatible = "syscon";
 698                 reg = <0xffaf0080 0x20>;
 699         };
 700
 701         pmu: power-management@ff730000 {
 702                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 703                 reg = <0xff730000 0x100>;
 704
 705                 power: power-controller {
 706                         compatible = "rockchip,rk3288-power-controller";
 707                         #power-domain-cells = <1>;
 708                         #address-cells = <1>;
 709                         #size-cells = <0>;
 710
 711                         /*
 712                          * Note: Although SCLK_* are the working clocks
 713                          * of device without including on the NOC, needed for
 714                          * synchronous reset.
 715                          *
 716                          * The clocks on the which NOC:
 717                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 718                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 719                          * ACLK_RGA is on ACLK_RGA_NIU.
 720                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 721                          *
 722                          * Which clock are device clocks:
 723                          *      clocks          devices
 724                          *      *_IEP           IEP:Image Enhancement Processor
 725                          *      *_ISP           ISP:Image Signal Processing
 726                          *      *_VIP           VIP:Video Input Processor
 727                          *      *_VOP*          VOP:Visual Output Processor
 728                          *      *_RGA           RGA
 729                          *      *_EDP*          EDP
 730                          *      *_LVDS_*        LVDS
 731                          *      *_HDMI          HDMI
 732                          *      *_MIPI_*        MIPI
 733                          */
 734                         pd_vio {
 735                                 reg = <RK3288_PD_VIO>;
 736                                 clocks = <&cru ACLK_IEP>,
 737                                          <&cru ACLK_ISP>,
 738                                          <&cru ACLK_RGA>,
 739                                          <&cru ACLK_VIP>,
 740                                          <&cru ACLK_VOP0>,
 741                                          <&cru ACLK_VOP1>,
 742                                          <&cru DCLK_VOP0>,
 743                                          <&cru DCLK_VOP1>,
 744                                          <&cru HCLK_IEP>,
 745                                          <&cru HCLK_ISP>,
 746                                          <&cru HCLK_RGA>,
 747                                          <&cru HCLK_VIP>,
 748                                          <&cru HCLK_VOP0>,
 749                                          <&cru HCLK_VOP1>,
 750                                          <&cru PCLK_EDP_CTRL>,
 751                                          <&cru PCLK_HDMI_CTRL>,
 752                                          <&cru PCLK_LVDS_PHY>,
 753                                          <&cru PCLK_MIPI_CSI>,
 754                                          <&cru PCLK_MIPI_DSI0>,
 755                                          <&cru PCLK_MIPI_DSI1>,
 756                                          <&cru SCLK_EDP_24M>,
 757                                          <&cru SCLK_EDP>,
 758                                          <&cru SCLK_ISP_JPE>,
 759                                          <&cru SCLK_ISP>,
 760                                          <&cru SCLK_RGA>;
 761                                 pm_qos = <&qos_vio0_iep>,
 762                                          <&qos_vio1_vop>,
 763                                          <&qos_vio1_isp_w0>,
 764                                          <&qos_vio1_isp_w1>,
 765                                          <&qos_vio0_vop>,
 766                                          <&qos_vio0_vip>,
 767                                          <&qos_vio2_rga_r>,
 768                                          <&qos_vio2_rga_w>,
 769                                          <&qos_vio1_isp_r>;
 770                         };
 771
 772                         /*
 773                          * Note: The following 3 are HEVC(H.265) clocks,
 774                          * and on the ACLK_HEVC_NIU (NOC).
 775                          */
 776                         pd_hevc {
 777                                 reg = <RK3288_PD_HEVC>;
 778                                 clocks = <&cru ACLK_HEVC>,
 779                                          <&cru SCLK_HEVC_CABAC>,
 780                                          <&cru SCLK_HEVC_CORE>;
 781                                 pm_qos = <&qos_hevc_r>,
 782                                          <&qos_hevc_w>;
 783                         };
 784
 785                         /*
 786                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 787                          * (video endecoder & decoder) clocks that on the
 788                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 789                          */
 790                         pd_video {
 791                                 reg = <RK3288_PD_VIDEO>;
 792                                 clocks = <&cru ACLK_VCODEC>,
 793                                          <&cru HCLK_VCODEC>;
 794                                 pm_qos = <&qos_video>;
 795                         };
 796
 797                         /*
 798                          * Note: ACLK_GPU is the GPU clock,
 799                          * and on the ACLK_GPU_NIU (NOC).
 800                          */
 801                         pd_gpu {
 802                                 reg = <RK3288_PD_GPU>;
 803                                 clocks = <&cru ACLK_GPU>;
 804                                 pm_qos = <&qos_gpu_r>,
 805                                          <&qos_gpu_w>;
 806                         };
 807                 };
 808
 809                 reboot-mode {
 810                         compatible = "syscon-reboot-mode";
 811                         offset = <0x94>;
 812                         mode-normal = <BOOT_NORMAL>;
 813                         mode-recovery = <BOOT_RECOVERY>;
 814                         mode-bootloader = <BOOT_FASTBOOT>;
 815                         mode-loader = <BOOT_LOADER>;
 816                         mode-ums = <BOOT_UMS>;
 817                 };
 818         };
 819
 820         sgrf: syscon@ff740000 {
 821                 compatible = "rockchip,rk3288-sgrf", "syscon";
 822                 reg = <0xff740000 0x1000>;
 823         };
 824
 825         cru: clock-controller@ff760000 {
 826                 compatible = "rockchip,rk3288-cru";
 827                 reg = <0xff760000 0x1000>;
 828                 rockchip,grf = <&grf>;
 829                 #clock-cells = <1>;
 830                 #reset-cells = <1>;
 831                 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
 832                                   <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 833                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 834                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 835                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 836                                   <&cru PCLK_PERI>;
 837                 assigned-clock-rates = <0>, <0>,
 838                                        <594000000>, <400000000>,
 839                                        <500000000>, <300000000>,
 840                                        <150000000>, <75000000>,
 841                                        <300000000>, <150000000>,
 842                                        <75000000>;
 843                 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
 844         };
 845
 846         grf: syscon@ff770000 {
 847                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 848                 reg = <0xff770000 0x1000>;
 849
 850                 edp_phy: edp-phy {
 851                         compatible = "rockchip,rk3288-dp-phy";
 852                         clocks = <&cru SCLK_EDP_24M>;
 853                         clock-names = "24m";
 854                         #phy-cells = <0>;
 855                         status = "disabled";
 856                 };
 857         };
 858
 859         wdt: watchdog@ff800000 {
 860                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 861                 reg = <0xff800000 0x100>;
 862                 clocks = <&cru PCLK_WDT>;
 863                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 864                 status = "disabled";
 865         };
 866
 867         spdif: sound@ff88b0000 {
 868                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 869                 reg = <0xff8b0000 0x10000>;
 870                 #sound-dai-cells = <0>;
 871                 clock-names = "hclk", "mclk";
 872                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 873                 dmas = <&dmac_bus_s 3>;
 874                 dma-names = "tx";
 875                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 876                 pinctrl-names = "default";
 877                 pinctrl-0 = <&spdif_tx>;
 878                 rockchip,grf = <&grf>;
 879                 status = "disabled";
 880         };
 881
 882         i2s: i2s@ff890000 {
 883                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 884                 reg = <0xff890000 0x10000>;
 885                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 886                 #address-cells = <1>;
 887                 #size-cells = <0>;
 888                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 889                 dma-names = "tx", "rx";
 890                 clock-names = "i2s_hclk", "i2s_clk";
 891                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 892                 pinctrl-names = "default";
 893                 pinctrl-0 = <&i2s0_bus>;
 894                 status = "disabled";
 895         };
 896
 897         vopb: vop@ff930000 {
 898                 compatible = "rockchip,rk3288-vop";
 899                 reg = <0xff930000 0x19c>;
 900                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 901                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 902                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 903                 power-domains = <&power RK3288_PD_VIO>;
 904                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 905                 reset-names = "axi", "ahb", "dclk";
 906                 iommus = <&vopb_mmu>;
 907                 status = "disabled";
 908
 909                 vopb_out: port {
 910                         #address-cells = <1>;
 911                         #size-cells = <0>;
 912
 913                         vopb_out_hdmi: endpoint@0 {
 914                                 reg = <0>;
 915                                 remote-endpoint = <&hdmi_in_vopb>;
 916                         };
 917
 918                         vopb_out_edp: endpoint@1 {
 919                                 reg = <1>;
 920                                 remote-endpoint = <&edp_in_vopb>;
 921                         };
 922
 923                         vopb_out_mipi: endpoint@2 {
 924                                 reg = <2>;
 925                                 remote-endpoint = <&mipi_in_vopb>;
 926                         };
 927
 928                         vopb_out_lvds: endpoint@3 {
 929                                 reg = <3>;
 930                                 remote-endpoint = <&lvds_in_vopb>;
 931                         };
 932                 };
 933         };
 934
 935         vopb_mmu: iommu@ff930300 {
 936                 compatible = "rockchip,iommu";
 937                 reg = <0xff930300 0x100>;
 938                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 939                 interrupt-names = "vopb_mmu";
 940                 power-domains = <&power RK3288_PD_VIO>;
 941                 #iommu-cells = <0>;
 942                 status = "disabled";
 943         };
 944
 945         vopl: vop@ff940000 {
 946                 compatible = "rockchip,rk3288-vop";
 947                 reg = <0xff940000 0x19c>;
 948                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 949                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 950                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 951                 power-domains = <&power RK3288_PD_VIO>;
 952                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 953                 reset-names = "axi", "ahb", "dclk";
 954                 iommus = <&vopl_mmu>;
 955                 status = "disabled";
 956
 957                 vopl_out: port {
 958                         #address-cells = <1>;
 959                         #size-cells = <0>;
 960
 961                         vopl_out_hdmi: endpoint@0 {
 962                                 reg = <0>;
 963                                 remote-endpoint = <&hdmi_in_vopl>;
 964                         };
 965
 966                         vopl_out_edp: endpoint@1 {
 967                                 reg = <1>;
 968                                 remote-endpoint = <&edp_in_vopl>;
 969                         };
 970
 971                         vopl_out_mipi: endpoint@2 {
 972                                 reg = <2>;
 973                                 remote-endpoint = <&mipi_in_vopl>;
 974                         };
 975
 976                         vopl_out_lvds: endpoint@3 {
 977                                 reg = <3>;
 978                                 remote-endpoint = <&lvds_in_vopl>;
 979                         };
 980
 981                 };
 982         };
 983
 984         vopl_mmu: iommu@ff940300 {
 985                 compatible = "rockchip,iommu";
 986                 reg = <0xff940300 0x100>;
 987                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 988                 interrupt-names = "vopl_mmu";
 989                 power-domains = <&power RK3288_PD_VIO>;
 990                 #iommu-cells = <0>;
 991                 status = "disabled";
 992         };
 993
 994         mipi_dsi: mipi@ff960000 {
 995                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
 996                 reg = <0xff960000 0x4000>;
 997                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 998                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
 999                 clock-names = "ref", "pclk";
1000                 rockchip,grf = <&grf>;
1001                 #address-cells = <1>;
1002                 #size-cells = <0>;
1003                 status = "disabled";
1004
1005                 ports {
1006                         #address-cells = <1>;
1007                         #size-cells = <0>;
1008                         reg = <1>;
1009
1010                         mipi_in: port {
1011                                 #address-cells = <1>;
1012                                 #size-cells = <0>;
1013                                 mipi_in_vopb: endpoint@0 {
1014                                         reg = <0>;
1015                                         remote-endpoint = <&vopb_out_mipi>;
1016                                 };
1017                                 mipi_in_vopl: endpoint@1 {
1018                                         reg = <1>;
1019                                         remote-endpoint = <&vopl_out_mipi>;
1020                                 };
1021                         };
1022                 };
1023         };
1024
1025         edp: dp@ff970000 {
1026                 compatible = "rockchip,rk3288-dp";
1027                 reg = <0xff970000 0x4000>;
1028                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1029                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1030                 clock-names = "dp", "pclk";
1031                 phys = <&edp_phy>;
1032                 phy-names = "dp";
1033                 resets = <&cru SRST_EDP>;
1034                 reset-names = "dp";
1035                 rockchip,grf = <&grf>;
1036                 status = "disabled";
1037
1038                 ports {
1039                         #address-cells = <1>;
1040                         #size-cells = <0>;
1041                         edp_in: port@0 {
1042                                 reg = <0>;
1043                                 #address-cells = <1>;
1044                                 #size-cells = <0>;
1045                                 edp_in_vopb: endpoint@0 {
1046                                         reg = <0>;
1047                                         remote-endpoint = <&vopb_out_edp>;
1048                                 };
1049                                 edp_in_vopl: endpoint@1 {
1050                                         reg = <1>;
1051                                         remote-endpoint = <&vopl_out_edp>;
1052                                 };
1053                         };
1054                 };
1055         };
1056
1057         lvds: lvds@ff96c000 {
1058                 compatible = "rockchip,rk3288-lvds";
1059                 reg = <0xff96c000 0x4000>;
1060                 clocks = <&cru PCLK_LVDS_PHY>;
1061                 clock-names = "pclk_lvds";
1062                 pinctrl-names = "default";
1063                 pinctrl-0 = <&lcdc0_ctl>;
1064                 power-domains = <&power RK3288_PD_VIO>;
1065                 rockchip,grf = <&grf>;
1066                 status = "disabled";
1067
1068                 ports {
1069                         #address-cells = <1>;
1070                         #size-cells = <0>;
1071
1072                         lvds_in: port@0 {
1073                                 reg = <0>;
1074
1075                                 #address-cells = <1>;
1076                                 #size-cells = <0>;
1077
1078                                 lvds_in_vopb: endpoint@0 {
1079                                         reg = <0>;
1080                                         remote-endpoint = <&vopb_out_lvds>;
1081                                 };
1082                                 lvds_in_vopl: endpoint@1 {
1083                                         reg = <1>;
1084                                         remote-endpoint = <&vopl_out_lvds>;
1085                                 };
1086                         };
1087                 };
1088         };
1089
1090         hdmi: hdmi@ff980000 {
1091                 compatible = "rockchip,rk3288-dw-hdmi";
1092                 reg = <0xff980000 0x20000>;
1093                 reg-io-width = <4>;
1094                 rockchip,grf = <&grf>;
1095                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1096                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1097                 clock-names = "iahb", "isfr";
1098                 power-domains = <&power RK3288_PD_VIO>;
1099                 status = "disabled";
1100
1101                 ports {
1102                         hdmi_in: port {
1103                                 #address-cells = <1>;
1104                                 #size-cells = <0>;
1105                                 hdmi_in_vopb: endpoint@0 {
1106                                         reg = <0>;
1107                                         remote-endpoint = <&vopb_out_hdmi>;
1108                                 };
1109                                 hdmi_in_vopl: endpoint@1 {
1110                                         reg = <1>;
1111                                         remote-endpoint = <&vopl_out_hdmi>;
1112                                 };
1113                         };
1114                 };
1115         };
1116
1117         gpu: gpu@ffa30000 {
1118                 compatible = "arm,malit764",
1119                              "arm,malit76x",
1120                              "arm,malit7xx",
1121                              "arm,mali-midgard";
1122                 reg = <0xffa30000 0x10000>;
1123                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1124                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1125                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1126                 interrupt-names = "JOB", "MMU", "GPU";
1127                 clocks = <&cru ACLK_GPU>;
1128                 clock-names = "clk_mali";
1129                 operating-points = <
1130                         /* KHz uV */
1131                         600000 1250000
1132                         /* 500000 1200000 - See crosbug.com/p/33857 */
1133                         400000 1100000
1134                         300000 1000000
1135                         200000 950000
1136                         100000 950000
1137                 >;
1138                 #cooling-cells = <2>; /* min followed by max */
1139                 power-domains = <&power RK3288_PD_GPU>;
1140                 status = "disabled";
1141         };
1142
1143         vpu: video-codec@ff9a0000 {
1144                 compatible = "rockchip,rk3288-vpu";
1145                 reg = <0xff9a0000 0x800>;
1146                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1147                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1148                 interrupt-names = "vepu", "vdpu";
1149                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1150                 clock-names = "aclk", "hclk";
1151                 power-domains = <&power RK3288_PD_VIDEO>;
1152                 iommus = <&vpu_mmu>;
1153                 assigned-clocks = <&cru ACLK_VCODEC>;
1154                 assigned-clock-rates = <400000000>;
1155                 status = "disabled";
1156         };
1157
1158         vpu_service: vpu-service@ff9a0000 {
1159                 compatible = "rockchip,vpu_service";
1160                 reg = <0xff9a0000 0x800>;
1161                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1162                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1163                 interrupt-names = "irq_enc", "irq_dec";
1164                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1165                 clock-names = "aclk_vcodec", "hclk_vcodec";
1166                 power-domains = <&power RK3288_PD_VIDEO>;
1167                 rockchip,grf = <&grf>;
1168                 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
1169                 reset-names = "video_a", "video_h";
1170                 iommus = <&vpu_mmu>;
1171                 iommu_enabled = <1>;
1172                 dev_mode = <0>;
1173                 status = "disabled";
1174         };
1175
1176         vpu_mmu: iommu@ff9a0800 {
1177                 compatible = "rockchip,iommu";
1178                 reg = <0xff9a0800 0x100>;
1179                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1180                 interrupt-names = "vpu_mmu";
1181                 power-domains = <&power RK3288_PD_VIDEO>;
1182                 #iommu-cells = <0>;
1183         };
1184
1185         hevc_service: hevc-service@ff9c0000 {
1186                 compatible = "rockchip,hevc_service";
1187                 reg = <0xff9c0000 0x400>;
1188                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1189                 interrupt-names = "irq_dec";
1190                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1191                         <&cru SCLK_HEVC_CORE>,
1192                         <&cru SCLK_HEVC_CABAC>;
1193                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
1194                         "clk_cabac";
1195                 /*
1196                  * The 4K hevc would also work well with 500/125/300/300,
1197                  * no more err irq and reset request.
1198                  */
1199                 assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1200                                   <&cru SCLK_HEVC_CORE>,
1201                                   <&cru SCLK_HEVC_CABAC>;
1202                 assigned-clock-rates = <400000000>, <100000000>,
1203                                        <300000000>, <300000000>;
1204
1205                 resets = <&cru SRST_HEVC>;
1206                 reset-names = "video";
1207                 power-domains = <&power RK3288_PD_HEVC>;
1208                 rockchip,grf = <&grf>;
1209                 dev_mode = <1>;
1210                 iommus = <&hevc_mmu>;
1211                 iommu_enabled = <1>;
1212                 status = "disabled";
1213         };
1214
1215         hevc_mmu: iommu@ff9c0440 {
1216                 compatible = "rockchip,iommu";
1217                 reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
1218                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1219                 interrupt-names = "hevc_mmu";
1220                 power-domains = <&power RK3288_PD_HEVC>;
1221                 #iommu-cells = <0>;
1222         };
1223
1224         gic: interrupt-controller@ffc01000 {
1225                 compatible = "arm,gic-400";
1226                 interrupt-controller;
1227                 #interrupt-cells = <3>;
1228                 #address-cells = <0>;
1229
1230                 reg = <0xffc01000 0x1000>,
1231                       <0xffc02000 0x1000>,
1232                       <0xffc04000 0x2000>,
1233                       <0xffc06000 0x2000>;
1234                 interrupts = <GIC_PPI 9 0xf04>;
1235         };
1236
1237         efuse: efuse@ffb40000 {
1238                 compatible = "rockchip,rockchip-efuse";
1239                 reg = <0xffb40000 0x20>;
1240                 #address-cells = <1>;
1241                 #size-cells = <1>;
1242                 clocks = <&cru PCLK_EFUSE256>;
1243                 clock-names = "pclk_efuse";
1244
1245                 cpu_leakage: cpu_leakage@17 {
1246                         reg = <0x17 0x1>;
1247                 };
1248         };
1249
1250         usbphy: phy {
1251                 compatible = "rockchip,rk3288-usb-phy";
1252                 rockchip,grf = <&grf>;
1253                 #address-cells = <1>;
1254                 #size-cells = <0>;
1255                 status = "disabled";
1256
1257                 usbphy0: usb-phy0 {
1258                         #phy-cells = <0>;
1259                         reg = <0x320>;
1260                         clocks = <&cru SCLK_OTGPHY0>;
1261                         clock-names = "phyclk";
1262                         resets = <&cru SRST_USBOTG_PHY>;
1263                         reset-names = "phy-reset";
1264                 };
1265
1266                 usbphy1: usb-phy1 {
1267                         #phy-cells = <0>;
1268                         reg = <0x334>;
1269                         clocks = <&cru SCLK_OTGPHY1>;
1270                         clock-names = "phyclk";
1271                 };
1272
1273                 usbphy2: usb-phy2 {
1274                         #phy-cells = <0>;
1275                         reg = <0x348>;
1276                         clocks = <&cru SCLK_OTGPHY2>;
1277                         clock-names = "phyclk";
1278                         resets = <&cru SRST_USBHOST1_PHY>;
1279                         reset-names = "phy-reset";
1280                 };
1281         };
1282
1283         cif_isp0: cif_isp@ff910000 {
1284                 compatible = "rockchip,rk3288-cif-isp";
1285                 rockchip,grf = <&grf>;
1286                 reg = <0xff910000 0x10000>, <0xff968000 0x4000>;
1287                 reg-names = "register", "csihost-register";
1288                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1289                         <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
1290                         <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
1291                         <&cru SCLK_MIPIDSI_24M>;
1292                 clock-names = "aclk_isp", "hclk_isp",
1293                         "sclk_isp", "sclk_isp_jpe",
1294                         "pclk_mipi_csi", "pclk_isp_in",
1295                         "sclk_mipidsi_24m";
1296                 resets = <&cru SRST_ISP>;
1297                 reset-names = "rst_isp";
1298                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1299                 interrupt-names = "cif_isp10_irq";
1300                 status = "disabled";
1301         };
1302
1303         pinctrl: pinctrl {
1304                 compatible = "rockchip,rk3288-pinctrl";
1305                 rockchip,grf = <&grf>;
1306                 rockchip,pmu = <&pmu>;
1307                 #address-cells = <1>;
1308                 #size-cells = <1>;
1309                 ranges;
1310
1311                 gpio0: gpio0@ff750000 {
1312                         compatible = "rockchip,gpio-bank";
1313                         reg =   <0xff750000 0x100>;
1314                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1315                         clocks = <&cru PCLK_GPIO0>;
1316
1317                         gpio-controller;
1318                         #gpio-cells = <2>;
1319
1320                         interrupt-controller;
1321                         #interrupt-cells = <2>;
1322                 };
1323
1324                 gpio1: gpio1@ff780000 {
1325                         compatible = "rockchip,gpio-bank";
1326                         reg = <0xff780000 0x100>;
1327                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1328                         clocks = <&cru PCLK_GPIO1>;
1329
1330                         gpio-controller;
1331                         #gpio-cells = <2>;
1332
1333                         interrupt-controller;
1334                         #interrupt-cells = <2>;
1335                 };
1336
1337                 gpio2: gpio2@ff790000 {
1338                         compatible = "rockchip,gpio-bank";
1339                         reg = <0xff790000 0x100>;
1340                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1341                         clocks = <&cru PCLK_GPIO2>;
1342
1343                         gpio-controller;
1344                         #gpio-cells = <2>;
1345
1346                         interrupt-controller;
1347                         #interrupt-cells = <2>;
1348                 };
1349
1350                 gpio3: gpio3@ff7a0000 {
1351                         compatible = "rockchip,gpio-bank";
1352                         reg = <0xff7a0000 0x100>;
1353                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1354                         clocks = <&cru PCLK_GPIO3>;
1355
1356                         gpio-controller;
1357                         #gpio-cells = <2>;
1358
1359                         interrupt-controller;
1360                         #interrupt-cells = <2>;
1361                 };
1362
1363                 gpio4: gpio4@ff7b0000 {
1364                         compatible = "rockchip,gpio-bank";
1365                         reg = <0xff7b0000 0x100>;
1366                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1367                         clocks = <&cru PCLK_GPIO4>;
1368
1369                         gpio-controller;
1370                         #gpio-cells = <2>;
1371
1372                         interrupt-controller;
1373                         #interrupt-cells = <2>;
1374                 };
1375
1376                 gpio5: gpio5@ff7c0000 {
1377                         compatible = "rockchip,gpio-bank";
1378                         reg = <0xff7c0000 0x100>;
1379                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1380                         clocks = <&cru PCLK_GPIO5>;
1381
1382                         gpio-controller;
1383                         #gpio-cells = <2>;
1384
1385                         interrupt-controller;
1386                         #interrupt-cells = <2>;
1387                 };
1388
1389                 gpio6: gpio6@ff7d0000 {
1390                         compatible = "rockchip,gpio-bank";
1391                         reg = <0xff7d0000 0x100>;
1392                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1393                         clocks = <&cru PCLK_GPIO6>;
1394
1395                         gpio-controller;
1396                         #gpio-cells = <2>;
1397
1398                         interrupt-controller;
1399                         #interrupt-cells = <2>;
1400                 };
1401
1402                 gpio7: gpio7@ff7e0000 {
1403                         compatible = "rockchip,gpio-bank";
1404                         reg = <0xff7e0000 0x100>;
1405                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1406                         clocks = <&cru PCLK_GPIO7>;
1407
1408                         gpio-controller;
1409                         #gpio-cells = <2>;
1410
1411                         interrupt-controller;
1412                         #interrupt-cells = <2>;
1413                 };
1414
1415                 gpio8: gpio8@ff7f0000 {
1416                         compatible = "rockchip,gpio-bank";
1417                         reg = <0xff7f0000 0x100>;
1418                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1419                         clocks = <&cru PCLK_GPIO8>;
1420
1421                         gpio-controller;
1422                         #gpio-cells = <2>;
1423
1424                         interrupt-controller;
1425                         #interrupt-cells = <2>;
1426                 };
1427
1428                 hdmi {
1429                         hdmi_ddc: hdmi-ddc {
1430                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1431                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1432                         };
1433                 };
1434
1435                 pcfg_pull_up: pcfg-pull-up {
1436                         bias-pull-up;
1437                 };
1438
1439                 pcfg_pull_down: pcfg-pull-down {
1440                         bias-pull-down;
1441                 };
1442
1443                 pcfg_pull_none: pcfg-pull-none {
1444                         bias-disable;
1445                 };
1446
1447                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1448                         bias-disable;
1449                         drive-strength = <12>;
1450                 };
1451
1452                 sleep {
1453                         global_pwroff: global-pwroff {
1454                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1455                         };
1456
1457                         ddrio_pwroff: ddrio-pwroff {
1458                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1459                         };
1460
1461                         ddr0_retention: ddr0-retention {
1462                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1463                         };
1464
1465                         ddr1_retention: ddr1-retention {
1466                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1467                         };
1468                 };
1469
1470                 edp {
1471                         edp_hpd: edp-hpd {
1472                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1473                         };
1474                 };
1475
1476                 i2c0 {
1477                         i2c0_xfer: i2c0-xfer {
1478                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1479                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1480                         };
1481                 };
1482
1483                 i2c1 {
1484                         i2c1_xfer: i2c1-xfer {
1485                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1486                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1487                         };
1488                 };
1489
1490                 i2c2 {
1491                         i2c2_xfer: i2c2-xfer {
1492                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1493                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1494                         };
1495                 };
1496
1497                 i2c3 {
1498                         i2c3_xfer: i2c3-xfer {
1499                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1500                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1501                         };
1502                 };
1503
1504                 i2c4 {
1505                         i2c4_xfer: i2c4-xfer {
1506                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1507                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1508                         };
1509                 };
1510
1511                 i2c5 {
1512                         i2c5_xfer: i2c5-xfer {
1513                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1514                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1515                         };
1516                 };
1517
1518                 i2s0 {
1519                         i2s0_bus: i2s0-bus {
1520                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1521                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1522                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1523                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1524                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1525                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1526                         };
1527                 };
1528
1529                 lcdc0 {
1530                         lcdc0_ctl: lcdc0-ctl {
1531                                 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1532                                                 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1533                                                 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1534                                                 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1535                         };
1536                 };
1537
1538                 sdmmc {
1539                         sdmmc_clk: sdmmc-clk {
1540                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1541                         };
1542
1543                         sdmmc_cmd: sdmmc-cmd {
1544                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1545                         };
1546
1547                         sdmmc_cd: sdmcc-cd {
1548                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1549                         };
1550
1551                         sdmmc_bus1: sdmmc-bus1 {
1552                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1553                         };
1554
1555                         sdmmc_bus4: sdmmc-bus4 {
1556                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1557                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1558                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1559                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1560                         };
1561                 };
1562
1563                 sdio0 {
1564                         sdio0_bus1: sdio0-bus1 {
1565                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1566                         };
1567
1568                         sdio0_bus4: sdio0-bus4 {
1569                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1570                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1571                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1572                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1573                         };
1574
1575                         sdio0_cmd: sdio0-cmd {
1576                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1577                         };
1578
1579                         sdio0_clk: sdio0-clk {
1580                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1581                         };
1582
1583                         sdio0_cd: sdio0-cd {
1584                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1585                         };
1586
1587                         sdio0_wp: sdio0-wp {
1588                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1589                         };
1590
1591                         sdio0_pwr: sdio0-pwr {
1592                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1593                         };
1594
1595                         sdio0_bkpwr: sdio0-bkpwr {
1596                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1597                         };
1598
1599                         sdio0_int: sdio0-int {
1600                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1601                         };
1602                 };
1603
1604                 sdio1 {
1605                         sdio1_bus1: sdio1-bus1 {
1606                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1607                         };
1608
1609                         sdio1_bus4: sdio1-bus4 {
1610                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1611                                                 <3 25 4 &pcfg_pull_up>,
1612                                                 <3 26 4 &pcfg_pull_up>,
1613                                                 <3 27 4 &pcfg_pull_up>;
1614                         };
1615
1616                         sdio1_cd: sdio1-cd {
1617                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1618                         };
1619
1620                         sdio1_wp: sdio1-wp {
1621                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1622                         };
1623
1624                         sdio1_bkpwr: sdio1-bkpwr {
1625                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1626                         };
1627
1628                         sdio1_int: sdio1-int {
1629                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1630                         };
1631
1632                         sdio1_cmd: sdio1-cmd {
1633                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1634                         };
1635
1636                         sdio1_clk: sdio1-clk {
1637                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1638                         };
1639
1640                         sdio1_pwr: sdio1-pwr {
1641                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1642                         };
1643                 };
1644
1645                 emmc {
1646                         emmc_clk: emmc-clk {
1647                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1648                         };
1649
1650                         emmc_cmd: emmc-cmd {
1651                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1652                         };
1653
1654                         emmc_pwr: emmc-pwr {
1655                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1656                         };
1657
1658                         emmc_bus1: emmc-bus1 {
1659                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1660                         };
1661
1662                         emmc_bus4: emmc-bus4 {
1663                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1664                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1665                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1666                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1667                         };
1668
1669                         emmc_bus8: emmc-bus8 {
1670                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1671                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1672                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1673                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1674                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1675                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1676                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1677                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1678                         };
1679                 };
1680
1681                 spi0 {
1682                         spi0_clk: spi0-clk {
1683                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1684                         };
1685                         spi0_cs0: spi0-cs0 {
1686                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1687                         };
1688                         spi0_tx: spi0-tx {
1689                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1690                         };
1691                         spi0_rx: spi0-rx {
1692                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1693                         };
1694                         spi0_cs1: spi0-cs1 {
1695                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1696                         };
1697                 };
1698                 spi1 {
1699                         spi1_clk: spi1-clk {
1700                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1701                         };
1702                         spi1_cs0: spi1-cs0 {
1703                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1704                         };
1705                         spi1_rx: spi1-rx {
1706                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1707                         };
1708                         spi1_tx: spi1-tx {
1709                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1710                         };
1711                 };
1712
1713                 spi2 {
1714                         spi2_cs1: spi2-cs1 {
1715                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1716                         };
1717                         spi2_clk: spi2-clk {
1718                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1719                         };
1720                         spi2_cs0: spi2-cs0 {
1721                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1722                         };
1723                         spi2_rx: spi2-rx {
1724                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1725                         };
1726                         spi2_tx: spi2-tx {
1727                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1728                         };
1729                 };
1730
1731                 uart0 {
1732                         uart0_xfer: uart0-xfer {
1733                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1734                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1735                         };
1736
1737                         uart0_cts: uart0-cts {
1738                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1739                         };
1740
1741                         uart0_rts: uart0-rts {
1742                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1743                         };
1744                 };
1745
1746                 uart1 {
1747                         uart1_xfer: uart1-xfer {
1748                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1749                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1750                         };
1751
1752                         uart1_cts: uart1-cts {
1753                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1754                         };
1755
1756                         uart1_rts: uart1-rts {
1757                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1758                         };
1759                 };
1760
1761                 uart2 {
1762                         uart2_xfer: uart2-xfer {
1763                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1764                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1765                         };
1766                         /* no rts / cts for uart2 */
1767                 };
1768
1769                 uart3 {
1770                         uart3_xfer: uart3-xfer {
1771                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1772                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1773                         };
1774
1775                         uart3_cts: uart3-cts {
1776                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1777                         };
1778
1779                         uart3_rts: uart3-rts {
1780                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1781                         };
1782                 };
1783
1784                 uart4 {
1785                         uart4_xfer: uart4-xfer {
1786                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1787                                                 <5 13 3 &pcfg_pull_none>;
1788                         };
1789
1790                         uart4_cts: uart4-cts {
1791                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1792                         };
1793
1794                         uart4_rts: uart4-rts {
1795                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1796                         };
1797                 };
1798
1799                 tsadc {
1800                         otp_gpio: otp-gpio {
1801                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1802                         };
1803
1804                         otp_out: otp-out {
1805                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1806                         };
1807                 };
1808
1809                 pwm0 {
1810                         pwm0_pin: pwm0-pin {
1811                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1812                         };
1813                 };
1814
1815                 pwm1 {
1816                         pwm1_pin: pwm1-pin {
1817                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1818                         };
1819                 };
1820
1821                 pwm2 {
1822                         pwm2_pin: pwm2-pin {
1823                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1824                         };
1825                 };
1826
1827                 pwm3 {
1828                         pwm3_pin: pwm3-pin {
1829                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1830                         };
1831                 };
1832
1833                 gmac {
1834                         rgmii_pins: rgmii-pins {
1835                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1836                                                 <3 31 3 &pcfg_pull_none>,
1837                                                 <3 26 3 &pcfg_pull_none>,
1838                                                 <3 27 3 &pcfg_pull_none>,
1839                                                 <3 28 3 &pcfg_pull_none_12ma>,
1840                                                 <3 29 3 &pcfg_pull_none_12ma>,
1841                                                 <3 24 3 &pcfg_pull_none_12ma>,
1842                                                 <3 25 3 &pcfg_pull_none_12ma>,
1843                                                 <4 0 3 &pcfg_pull_none>,
1844                                                 <4 5 3 &pcfg_pull_none>,
1845                                                 <4 6 3 &pcfg_pull_none>,
1846                                                 <4 9 3 &pcfg_pull_none_12ma>,
1847                                                 <4 4 3 &pcfg_pull_none_12ma>,
1848                                                 <4 1 3 &pcfg_pull_none>,
1849                                                 <4 3 3 &pcfg_pull_none>;
1850                         };
1851
1852                         rmii_pins: rmii-pins {
1853                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1854                                                 <3 31 3 &pcfg_pull_none>,
1855                                                 <3 28 3 &pcfg_pull_none>,
1856                                                 <3 29 3 &pcfg_pull_none>,
1857                                                 <4 0 3 &pcfg_pull_none>,
1858                                                 <4 5 3 &pcfg_pull_none>,
1859                                                 <4 4 3 &pcfg_pull_none>,
1860                                                 <4 1 3 &pcfg_pull_none>,
1861                                                 <4 2 3 &pcfg_pull_none>,
1862                                                 <4 3 3 &pcfg_pull_none>;
1863                         };
1864                 };
1865
1866                 spdif {
1867                         spdif_tx: spdif-tx {
1868                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1869                         };
1870                 };
1871
1872                 cif {
1873                         cif_dvp_d2d9: cif-dvp-d2d9 {
1874                                 rockchip,pins = <2 0 RK_FUNC_1 &pcfg_pull_none>,
1875                                                 <2 1 RK_FUNC_1 &pcfg_pull_none>,
1876                                                 <2 2 RK_FUNC_1 &pcfg_pull_none>,
1877                                                 <2 3 RK_FUNC_1 &pcfg_pull_none>,
1878                                                 <2 4 RK_FUNC_1 &pcfg_pull_none>,
1879                                                 <2 5 RK_FUNC_1 &pcfg_pull_none>,
1880                                                 <2 6 RK_FUNC_1 &pcfg_pull_none>,
1881                                                 <2 7 RK_FUNC_1 &pcfg_pull_none>,
1882                                                 <2 8 RK_FUNC_1 &pcfg_pull_none>,
1883                                                 <2 9 RK_FUNC_1 &pcfg_pull_none>,
1884                                                 <2 11 RK_FUNC_1 &pcfg_pull_none>;
1885                         };
1886                 };
1887         };
1888 };