arch/arm/boot/dts/rk3288.dtsi

   1 #include <dt-bindings/clock/ddr.h>
   2 #include <dt-bindings/interrupt-controller/arm-gic.h>
   3 #include <dt-bindings/rkfb/rk_fb.h>
   4 #include <dt-bindings/suspend/rockchip-pm.h>
   5 #include <dt-bindings/sensor-dev.h>
   6
   7 #include "skeleton.dtsi"
   8 #include "rk3288-pinctrl.dtsi"
   9 #include "rk3288-clocks.dtsi"
  10
  11 / {
  12         compatible = "rockchip,rk3288";
  13         interrupt-parent = <&gic>;
  14
  15         aliases {
  16                 serial2 = &uart_dbg;
  17                 i2c0 = &i2c0;
  18                 i2c1 = &i2c1;
  19                 i2c2 = &i2c2;
  20                 i2c3 = &i2c3;
  21                 i2c4 = &i2c4;
  22                 i2c5 = &i2c5;
  23                 lcdc0 = &lcdc0;
  24                 lcdc1 = &lcdc1;
  25         };
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 cpu@0 {
  32                         device_type = "cpu";
  33                         compatible = "arm,cortex-a15";
  34                         reg = <0x500>;
  35                 };
  36                 cpu@1 {
  37                         device_type = "cpu";
  38                         compatible = "arm,cortex-a15";
  39                         reg = <0x501>;
  40                 };
  41                 cpu@2 {
  42                         device_type = "cpu";
  43                         compatible = "arm,cortex-a15";
  44                         reg = <0x502>;
  45                 };
  46                 cpu@3 {
  47                         device_type = "cpu";
  48                         compatible = "arm,cortex-a15";
  49                         reg = <0x503>;
  50                 };
  51         };
  52
  53         gic: interrupt-controller@ffc01000 {
  54                 compatible = "arm,cortex-a15-gic";
  55                 interrupt-controller;
  56                 #interrupt-cells = <3>;
  57                 #address-cells = <0>;
  58                 reg = <0xffc01000 0x1000>,
  59                       <0xffc02000 0x1000>;
  60         };
  61
  62         sram: sram@ff710000 {
  63                 compatible = "mmio-sram";
  64                 reg = <0xff710000 0x8000>; /* 32k */
  65                 map-exec;
  66         };
  67
  68         timer {
  69                 compatible = "arm,armv7-timer";
  70                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  71                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  72                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
  73                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  74                 clock-frequency = <24000000>;
  75         };
  76
  77         timer@ff810000 {
  78                 compatible = "rockchip,timer";
  79                 reg = <0xff810000 0x20>;
  80                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
  81                 rockchip,broadcast = <1>;
  82         };
  83
  84         timer@ff810020 {
  85                 compatible = "rockchip,timer";
  86                 reg = <0xff810020 0x20>;
  87                 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
  88                 rockchip,clocksource = <1>;
  89                 rockchip,count-up = <1>;
  90         };
  91
  92         uart_dbg: serial@ff690000 {
  93                 compatible = "rockchip,serial";
  94                 reg = <0xff690000 0x100>;
  95                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
  96                 clock-frequency = <24000000>;
  97                 reg-shift = <2>;
  98                 reg-io-width = <4>;
  99                 status = "disabled";
 100         };
 101
 102         fiq-debugger {
 103                 compatible = "rockchip,fiq-debugger";
 104                 rockchip,serial-id = <2>;
 105                 rockchip,signal-irq = <106>;
 106                 rockchip,wake-irq = <0>;
 107                 status = "disabled";
 108         };
 109
 110         i2c0: i2c@ff650000 {
 111                 compatible = "rockchip,rk30-i2c";
 112                 reg = <0xff650000 0x1000>;
 113                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 114                 #address-cells = <1>;
 115                 #size-cells = <0>;
 116                 //pinctrl-names = "default", "gpio";
 117                 //pinctrl-0 = <&i2c0_sda &i2c0_scl>;
 118                 //pinctrl-1 = <&i2c0_gpio>;
 119                 //gpios = <&gpio0 GPIO_B7 GPIO_ACTIVE_LOW>, <&gpio0 GPIO_C0 GPIO_ACTIVE_LOW>;
 120                 //clocks = <&clk_gates8 4>;
 121                 rockchip,check-idle = <1>;
 122                 status = "disabled";
 123         };
 124
 125         i2c1: i2c@ff140000 {
 126                 compatible = "rockchip,rk30-i2c";
 127                 reg = <0xff140000 0x1000>;
 128                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 129                 #address-cells = <1>;
 130                 #size-cells = <0>;
 131                 //pinctrl-names = "default", "gpio";
 132                 //pinctrl-0 = <&i2c1_sda &i2c1_scl>;
 133                 //pinctrl-1 = <&i2c1_gpio>;
 134                 //gpios = <&gpio8 GPIO_A4 GPIO_ACTIVE_LOW>, <&gpio8 GPIO_A5 GPIO_ACTIVE_LOW>;
 135                 //clocks = <&clk_gates8 5>;
 136                 rockchip,check-idle = <1>;
 137                 status = "disabled";
 138         };
 139
 140         i2c2: i2c@ff660000 {
 141                 compatible = "rockchip,rk30-i2c";
 142                 reg = <0xff660000 0x1000>;
 143                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 144                 #address-cells = <1>;
 145                 #size-cells = <0>;
 146                 //pinctrl-names = "default", "gpio";
 147                 //pinctrl-0 = <&i2c2_sda &i2c2_scl>;
 148                 //pinctrl-1 = <&i2c2_gpio>;
 149                 //gpios = <&gpio6 GPIO_B1 GPIO_ACTIVE_LOW>, <&gpio6 GPIO_B2 GPIO_ACTIVE_LOW>;
 150                 //clocks = <&clk_gates8 6>;
 151                 rockchip,check-idle = <1>;
 152                 status = "disabled";
 153         };
 154
 155         i2c3: i2c@ff150000 {
 156                 compatible = "rockchip,rk30-i2c";
 157                 reg = <0xff150000 0x1000>;
 158                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 159                 #address-cells = <1>;
 160                 #size-cells = <0>;
 161                 //pinctrl-names = "default", "gpio";
 162                 //pinctrl-0 = <&i2c3_sda &i2c3_scl>;
 163                 //pinctrl-1 = <&i2c3_gpio>;
 164                 //gpios = <&gpio2 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio2 GPIO_C0 GPIO_ACTIVE_LOW>;
 165                 //clocks = <&clk_gates8 7>;
 166                 rockchip,check-idle = <1>;
 167                 status = "disabled";
 168         };
 169
 170         i2c4: i2c@ff160000 {
 171                 compatible = "rockchip,rk30-i2c";
 172                 reg = <0xff160000 0x1000>;
 173                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 174                 #address-cells = <1>;
 175                 #size-cells = <0>;
 176                 //pinctrl-names = "default", "gpio";
 177                 //pinctrl-0 = <&i2c4_sda &i2c4_scl>;
 178                 //pinctrl-1 = <&i2c4_gpio>;
 179                 //gpios = <&gpio7 GPIO_C1 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C2 GPIO_ACTIVE_LOW>;
 180                 //clocks = <&clk_gates8 8>;
 181                 rockchip,check-idle = <1>;
 182                 status = "disabled";
 183         };
 184
 185         i2c5: i2c@ff170000 {
 186                 compatible = "rockchip,rk30-i2c";
 187                 reg = <0xff170000 0x1000>;
 188                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 189                 #address-cells = <1>;
 190                 #size-cells = <0>;
 191                 //pinctrl-names = "default", "gpio";
 192                 //pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 193                 //pinctrl-1 = <&i2c5_gpio>;
 194                 //gpios = <&gpio7 GPIO_C3 GPIO_ACTIVE_LOW>, <&gpio7 GPIO_C4 GPIO_ACTIVE_LOW>;
 195                 //clocks = <&clk_gates8 8>;
 196                 rockchip,check-idle = <1>;
 197                 status = "disabled";
 198         };
 199
 200
 201         fb: fb{
 202                 compatible = "rockchip,rk-fb";
 203                 rockchip,disp-mode = <DUAL>;
 204         };
 205
 206         rk_screen: rk_screen{
 207                         compatible = "rockchip,screen";
 208         };
 209
 210         lvds: lvds@ff96c000 {
 211                 compatible = "rockchip, rk32-lvds";
 212                 reg = <0xff960000 0x20000>;
 213         };
 214
 215         edp: edp@ff970000 {
 216                 compatible = "rockchip,rk32-edp";
 217                 reg = <0xff970000 0x4000>;
 218                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 219         };
 220
 221         hdmi: hdmi@ff980000 {
 222                 compatible = "rockchip,rk3288-hdmi";
 223                 reg = <0xff980000 0x20000>;
 224                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 225                 rockchip,hdmi_lcdc_source = <1>;
 226                 pinctrl-names = "default", "gpio";
 227                 pinctrl-0 = <&i2c5_sda &i2c5_scl>;
 228                 pinctrl-1 = <&i2c5_gpio>;
 229                 status = "disabled";
 230         };
 231
 232         lcdc0: lcdc@ff940000 {
 233                 compatible = "rockchip,rk3288-lcdc";
 234                 rockchip,prop = <PRMRY>;
 235                 rochchip,pwr18 = <0>;
 236                 reg = <0xff940000 0x10000>;
 237                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 238                 //pinctrl-names = "default", "gpio";
 239                 //pinctrl-0 = <&lcdc0_lcdc>;
 240                 //pinctrl-1 = <&lcdc0_gpio>;
 241                 status = "disabled";
 242         };
 243
 244         lcdc1: lcdc@ff930000 {
 245                 compatible = "rockchip,rk3288-lcdc";
 246                 rockchip,prop = <EXTEND>;
 247                 rockchip,pwr18 = <0>;
 248                 reg = <0xff930000 0x10000>;
 249                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 250                 pinctrl-names = "default", "gpio";
 251                 pinctrl-0 = <&lcdc0_lcdc>;
 252                 pinctrl-1 = <&lcdc0_gpio>;
 253                 status = "disabled";
 254         };
 255
 256         adc: adc@ff100000 {
 257                 compatible = "rockchip,saradc";
 258                 reg = <0xff100000 0x100>;
 259                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 260                 #io-channel-cells = <1>;
 261                 io-channel-ranges;
 262                 rockchip,adc-vref = <1800>;
 263                 clock-frequency = <1000000>;
 264                 clock-names = "saradc", "pclk_saradc";
 265                 status = "disabled";
 266         };
 267
 268         rga@ff920000 {
 269                 compatible = "rockchip,rga";
 270                 reg = <0xff920000 0x1000>;
 271                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
 272                 clock-names = "hclk_rga", "aclk_rga";
 273         };
 274
 275         i2s: rockchip-i2s@0xff890000 {
 276                 compatible = "rockchip-i2s";
 277                 reg = <0xff890000 0x10000>;
 278                 i2s-id = <0>;
 279         //      clocks = <&clk_i2s>;
 280         //      clock-names = "i2s_clk","i2s_mclk";
 281                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 282         //      dmas = <&pdma0 0>,
 283         //              <&pdma0 1>;
 284                 //#dma-cells = <2>;
 285         //      dma-names = "tx", "rx";
 286         //      pinctrl-names = "default", "sleep";
 287         //      pinctrl-0 = <&i2s0_mclk &i2s0_sclk &i2s0_lrckrx &i2s0_lrcktx &i2s0_sdi &i2s0_sdo0 &i2s0_sdo1 &i2s0_sdo2 &i2s0_sdo3>;
 288         //      pinctrl-1 = <&i2s0_gpio>;
 289         };
 290
 291         spdif: rockchip-spdif@0xff8b0000 {
 292                 compatible = "rockchip-spdif";
 293                 reg = <0xff8b0000 0x10000>;     //8channel
 294                 //reg = <ff880000 0x2000>;//2channel
 295         //      clocks = <&clk_spdif>;
 296         //      clock-names = "spdif_mclk";
 297                 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 298         //      dmas = <&pdma0 8>;
 299                 //#dma-cells = <1>;
 300         //      dma-names = "tx";
 301         //      pinctrl-names = "default";
 302         //      pinctrl-0 = <&spdif_tx>;
 303         };
 304
 305         ion {
 306                 compatible = "rockchip,ion";
 307                 #address-cells = <1>;
 308                 #size-cells = <0>;
 309                 rockchip,ion-heap@1 { /* CMA HEAP */
 310                         compatible = "rockchip,ion-reserve";
 311                         reg = <1>;
 312                         memory-reservation = <0x00000000 0x10000000>; /* 256MB */
 313                 };
 314                 rockchip,ion-heap@3 { /* SYSTEM HEAP */
 315                         reg = <3>;
 316                 };
 317         };
 318
 319         mmc: mshc@ff0c0000 {
 320                 compatible = "rockchip,rk_mmc";
 321                 reg = <0xff0c0000 0x4000>;
 322                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; /*irq=64*/
 323                 #address-cells = <1>;
 324                 #size-cells = <0>;
 325                 //pinctrl-names = "default","suspend";
 326                 //pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_cd &sdmmc0_wp &sdmmc0_pwr &sdmmc0_bus1 &sdmmc0_bus4>;
 327                 //pinctrl-1 = <&sd0_cd_gpio>; //for int gpio?
 328                 //clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
 329                 //clock-names = "hclk_mmc","mmc";
 330                 clock-frequency = <50000000>;
 331                 clock-freq-min-max = <400000 50000000>;
 332                 num-slots = <1>;
 333                 supports-highspeed;
 334                 broken-cd;
 335                 card-detect-delay = <200>;
 336                 pwr-gpios = <&gpio3 GPIO_A1 GPIO_ACTIVE_LOW>; /*pwr_en = GPIO3_A1*/
 337                 fifo-depth = <0x100>;
 338                 emmc-compatible = <0>;
 339                 status = "okay";
 340         };
 341
 342         sdio0: mshc@ff0d0000 {
 343                 compatible = "rockchip,rk_mmc";
 344                 reg = <0xff0d0000 0x4000>;
 345                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; /*irq=65*/
 346                 #address-cells = <1>;
 347                 #size-cells = <0>;
 348                 //pinctrl-names = "default";
 349                 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 350                 //clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
 351                 //clock-names = "hclk_sdio0","sdio0";
 352                 clock-frequency = <50000000>;
 353                 clock-freq-min-max = <400000 50000000>;
 354                 num-slots = <1>;
 355                 supports-highspeed;
 356                 fifo-depth = <0x100>;
 357                 emmc-compatible = <0>;
 358                 status = "disabled";
 359         };
 360
 361         sdio1: mshc@ff0e0000 {
 362                 compatible = "rockchip,rk_mmc";
 363                 reg = <0xff0e0000 0x4000>;
 364                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; /*irq=66*/
 365                 #address-cells = <1>;
 366                 #size-cells = <0>;
 367                 //pinctrl-names = "default";
 368                 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 369                 //clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
 370                 //clock-names = "hclk_sdio1","sdio1";
 371                 clock-frequency = <50000000>;
 372                 clock-freq-min-max = <400000 50000000>;
 373                 num-slots = <1>;
 374                 supports-highspeed;
 375                 fifo-depth = <0x100>;
 376                 emmc-compatible = <0>;
 377                 status = "disabled";
 378         };
 379
 380         emmc: mshc@ff0f0000 {
 381                 compatible = "rockchip,rk_mmc";
 382                 reg = <0xff0f0000 0x4000>;
 383                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; /*irq=67*/
 384                 #address-cells = <1>;
 385                 #size-cells = <0>;
 386                 //pinctrl-names = "default";
 387                 //pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_cd &sd1_wp &sd1_bus1 &sd1_bus4>;
 388                 //clocks = <&clk_gatesX XX> , <&clk_gatesY YY>;
 389                 //clock-names = "hclk_sdio1","sdio1";
 390                 clock-frequency = <50000000>;
 391                 clock-freq-min-max = <400000 50000000>;
 392                 num-slots = <1>;
 393                 supports-highspeed;
 394                 fifo-depth = <0x100>;
 395                 emmc-compatible = <1>;
 396                 status = "disabled";
 397         };
 398
 399         vpu: vpu_service@ff9a0000 {
 400                 compatible = "vpu_service";
 401                 reg = <0xff9a0000 0x800>;
 402                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 403                 interrupt-names = "irq_enc", "irq_dec";
 404                 /*clocks = <&clk_gates3 9>, <&clk_gates3 10>;
 405                 clock-names = "aclk_vcodec", "hclk_vcodec"; */
 406                 name = "vpu_service";
 407                 status = "disabled";
 408         };
 409
 410         hevc: hevc_service@ff9c0000 {
 411                 compatible = "rockchip,hevc_service";
 412                 reg = <0xff9c0000 0x800>;
 413                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 414                 interrupt-names = "irq_dec";
 415                 /*clocks = <&clk_gates3 9>, <&clk_gates3 10>;
 416                 clock-names = "aclk_vcodec", "hclk_vcodec";*/
 417                 name = "hevc_service";
 418                 status = "disabled";
 419         };
 420
 421         iep: iep@ff900000 {
 422                 compatible = "rockchip,iep";
 423                 reg = <0xff900000 0x800>;
 424                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 425                 /*clocks = <&clk_gate3 9>, <&clk_gate3 10>;
 426                 clock_names = "aclk_iep", "hclk_iep";*/
 427                 status = "disabled";
 428         };
 429
 430         dwc_control_usb: dwc-control-usb@ff770284 {
 431                 compatible = "rockchip,rk3288-dwc-control-usb";
 432                 reg = <0xff770284 0x04>, <0xff770288 0x04>,
 433                       <0xff7702cc 0x04>, <0xff7702d4 0x04>,
 434                       <0xff770320 0x14>, <0xff770334 0x14>,
 435                       <0xff770348 0x10>, <0xff770358 0x08>,
 436                       <0xff770360 0x08>;
 437                 reg-names = "GRF_SOC_STATUS1" ,"GRF_SOC_STATUS2",
 438                             "GRF_SOC_STATUS19", "GRF_SOC_STATUS21",
 439                             "GRF_UOC0_BASE", "GRF_UOC1_BASE",
 440                             "GRF_UOC2_BASE", "GRF_UOC3_BASE",
 441                             "GRF_UOC4_BASE";
 442                 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
 443                              <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
 444                              <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 445                 interrupt-names = "otg_id", "bvalid",
 446                                   "otg_linestate", "host0_linestate",
 447                                   "host1_linestate";
 448                 /*gpios = <&gpio0 GPIO_B6 GPIO_ACTIVE_LOW>,*//*HOST_VBUS_DRV*/
 449                 /*      <&gpio0 GPIO_B4 GPIO_ACTIVE_LOW>;*//*OTG_VBUS_DRV*/
 450                 /*clocks = <&clk_gates4 5>;*/
 451                 /*clock-names = "hclk_usb_peri";*/
 452         };
 453
 454         usb1: usb@ff580000 {
 455                 compatible = "rockchip,rk3288_usb20_otg";
 456                 reg = <0xff580000 0x40000>;
 457                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 458                 /*clocks = <&clk_otgphy0_480m>, <&clk_gates5 13>;*/
 459                 /*clock-names = "otgphy0", "hclk_otg0";*/
 460         };
 461
 462         usb2: usb@ff540000 {
 463                 compatible = "rockchip,rk3288_usb20_host";
 464                 reg = <0xff540000 0x40000>;
 465                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 466                 /*clocks = <&clk_otgphy1_480m>, <&clk_gates7 3>;*/
 467                 /*clock-names = "otgphy1", "hclk_otg1";*/
 468         };
 469
 470         usb3: usb@ff520000 {
 471                 compatible = "rockchip,rk3288_rk_ohci_host";
 472                 reg = <0xff520000 0x20000>;
 473                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 474                 /*clocks = ;*/
 475                 /*clock-names = ;*/
 476         };
 477
 478         usb4: usb@ff500000 {
 479                 compatible = "rockchip,rk3288_rk_ehci_host";
 480                 reg = <0xff500000 0x20000>;
 481                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 482                 /*clocks = ;*/
 483                 /*clock-names = ;*/
 484         };
 485
 486         usb5: hsic@ff5c0000 {
 487                 compatible = "rockchip,rk3288_rk_hsic_host";
 488                 reg = <0xff5c0000 0x40000>;
 489                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 490                 /*clocks = <&clk_hsicphy480m>, <&clk_gates7 4>,*/
 491                 /*       <&clk_hsicphy12m>, <&clk_otgphy1_480m>;*/
 492                 /*clock-names = "hsicphy480m", "hclk_hsic",*/
 493                 /*            "hsicphy12m", "hsic_otgphy1";*/
 494         };
 495
 496         gmac: eth@ff290000 {
 497                 compatible = "rockchip,gmac";
 498                 reg = <0xff290000 0x10000>;
 499                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;  /*irq=59*/
 500                 interrupt-names = "macirq";
 501                 phy-mode = "rmii";
 502                 //phy-mode = "gmii";
 503                 pinctrl-names = "default";
 504                 pinctrl-0 = <&mac_clk &mac_txpins &mac_rxpins &mac_mdpins>;
 505         };
 506     gpu{
 507         compatible = "arm,malit764",
 508                      "arm,malit76x",
 509                      "arm,malit7xx",
 510                      "arm,mali-midgard";
 511         reg = <0xffa40000 0x1000>;
 512         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
 513                      <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 514                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 515         interrupt-names = "JOB",
 516                           "MMU",
 517                           "GPU";
 518     };
 519
 520     iep_mmu{
 521         dbgname = "iep";
 522         compatible = "iommu,iep_mmu";
 523         reg = <0xffa40000 0x10000>;
 524         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 525         interrupt-names = "iep_mmu";
 526     };
 527
 528     vip_mmu{
 529         dbgname = "vip";
 530         compatible = "iommu,vip_mmu";
 531         reg = <0xffa40000 0x10000>;
 532         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 533         interrupt-names = "vip_mmu";
 534     };
 535
 536     isp0_mmu{
 537         dbgname = "isp0";
 538         compatible = "iommu,isp0_mmu";
 539         reg = <0xffa40000 0x10000>;
 540         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 541         interrupt-names = "isp0_mmu";
 542     };
 543
 544     isp1_mmu{
 545         dbgname = "isp1";
 546         compatible = "iommu,isp1_mmu";
 547         reg = <0xffa40000 0x10000>;
 548         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 549         interrupt-names = "isp1_mmu";
 550     };
 551
 552     vopb_mmu{
 553         dbgname = "vopb";
 554         compatible = "iommu,vopb_mmu";
 555         reg = <0xffa40000 0x10000>;
 556         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 557         interrupt-names = "vopb_mmu";
 558     };
 559
 560     vopl_mmu{
 561         dbgname = "vopl";
 562         compatible = "iommu,vopl_mmu";
 563         reg = <0xffa40000 0x10000>;
 564         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 565         interrupt-names = "vopl_mmu";
 566     };
 567 };