arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49 #include <dt-bindings/display/drm_mipi_dsi.h>
  50 #include "skeleton.dtsi"
  51
  52 / {
  53         compatible = "rockchip,rk3288";
  54
  55         interrupt-parent = <&gic>;
  56
  57         aliases {
  58                 ethernet0 = &gmac;
  59                 i2c0 = &i2c0;
  60                 i2c1 = &i2c1;
  61                 i2c2 = &i2c2;
  62                 i2c3 = &i2c3;
  63                 i2c4 = &i2c4;
  64                 i2c5 = &i2c5;
  65                 mshc0 = &emmc;
  66                 mshc1 = &sdmmc;
  67                 mshc2 = &sdio0;
  68                 mshc3 = &sdio1;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74                 spi0 = &spi0;
  75                 spi1 = &spi1;
  76                 spi2 = &spi2;
  77         };
  78
  79         arm-pmu {
  80                 compatible = "arm,cortex-a12-pmu";
  81                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  82                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  83                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  84                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  85                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  86         };
  87
  88         cpus {
  89                 #address-cells = <1>;
  90                 #size-cells = <0>;
  91                 enable-method = "rockchip,rk3066-smp";
  92                 rockchip,pmu = <&pmu>;
  93
  94                 cpu0: cpu@500 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a12";
  97                         reg = <0x500>;
  98                         resets = <&cru SRST_CORE0>;
  99                         operating-points-v2 = <&cpu0_opp_table>;
 100                         #cooling-cells = <2>; /* min followed by max */
 101                         dynamic-power-coefficient = <322>;
 102                         clocks = <&cru ARMCLK>;
 103                 };
 104                 cpu1: cpu@501 {
 105                         device_type = "cpu";
 106                         compatible = "arm,cortex-a12";
 107                         reg = <0x501>;
 108                         resets = <&cru SRST_CORE1>;
 109                         operating-points-v2 = <&cpu0_opp_table>;
 110                 };
 111                 cpu2: cpu@502 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a12";
 114                         reg = <0x502>;
 115                         resets = <&cru SRST_CORE2>;
 116                         operating-points-v2 = <&cpu0_opp_table>;
 117                 };
 118                 cpu3: cpu@503 {
 119                         device_type = "cpu";
 120                         compatible = "arm,cortex-a12";
 121                         reg = <0x503>;
 122                         resets = <&cru SRST_CORE3>;
 123                         operating-points-v2 = <&cpu0_opp_table>;
 124                 };
 125         };
 126
 127         cpu0_opp_table: opp_table0 {
 128                 compatible = "operating-points-v2";
 129                 opp-shared;
 130
 131                 opp@126000000 {
 132                         opp-hz = /bits/ 64 <126000000>;
 133                         opp-microvolt = <900000>;
 134                         clock-latency-ns = <40000>;
 135                 };
 136                 opp@216000000 {
 137                         opp-hz = /bits/ 64 <216000000>;
 138                         opp-microvolt = <900000>;
 139                         clock-latency-ns = <40000>;
 140                 };
 141                 opp@408000000 {
 142                         opp-hz = /bits/ 64 <408000000>;
 143                         opp-microvolt = <900000>;
 144                         clock-latency-ns = <40000>;
 145                 };
 146                 opp@600000000 {
 147                         opp-hz = /bits/ 64 <600000000>;
 148                         opp-microvolt = <900000>;
 149                         clock-latency-ns = <40000>;
 150                 };
 151                 opp@696000000 {
 152                         opp-hz = /bits/ 64 <696000000>;
 153                         opp-microvolt = <950000>;
 154                         clock-latency-ns = <40000>;
 155                 };
 156                 opp@816000000 {
 157                         opp-hz = /bits/ 64 <816000000>;
 158                         opp-microvolt = <1000000>;
 159                         clock-latency-ns = <40000>;
 160                         opp-suspend;
 161                 };
 162                 opp@1008000000 {
 163                         opp-hz = /bits/ 64 <1008000000>;
 164                         opp-microvolt = <1050000>;
 165                         clock-latency-ns = <40000>;
 166                 };
 167                 opp@1200000000 {
 168                         opp-hz = /bits/ 64 <1200000000>;
 169                         opp-microvolt = <1100000>;
 170                         clock-latency-ns = <40000>;
 171                 };
 172                 opp@1416000000 {
 173                         opp-hz = /bits/ 64 <1416000000>;
 174                         opp-microvolt = <1200000>;
 175                         clock-latency-ns = <40000>;
 176                 };
 177                 opp@1512000000 {
 178                         opp-hz = /bits/ 64 <1512000000>;
 179                         opp-microvolt = <1300000>;
 180                         clock-latency-ns = <40000>;
 181                 };
 182                 opp@1608000000 {
 183                         opp-hz = /bits/ 64 <1608000000>;
 184                         opp-microvolt = <1350000>;
 185                         clock-latency-ns = <40000>;
 186                 };
 187         };
 188
 189         amba {
 190                 compatible = "arm,amba-bus";
 191                 #address-cells = <1>;
 192                 #size-cells = <1>;
 193                 ranges;
 194
 195                 dmac_peri: dma-controller@ff250000 {
 196                         compatible = "arm,pl330", "arm,primecell";
 197                         reg = <0xff250000 0x4000>;
 198                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 199                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 200                         #dma-cells = <1>;
 201                         arm,pl330-broken-no-flushp;
 202                         peripherals-req-type-burst;
 203                         clocks = <&cru ACLK_DMAC2>;
 204                         clock-names = "apb_pclk";
 205                 };
 206
 207                 dmac_bus_ns: dma-controller@ff600000 {
 208                         compatible = "arm,pl330", "arm,primecell";
 209                         reg = <0xff600000 0x4000>;
 210                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 211                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 212                         #dma-cells = <1>;
 213                         arm,pl330-broken-no-flushp;
 214                         peripherals-req-type-burst;
 215                         clocks = <&cru ACLK_DMAC1>;
 216                         clock-names = "apb_pclk";
 217                         status = "disabled";
 218                 };
 219
 220                 dmac_bus_s: dma-controller@ffb20000 {
 221                         compatible = "arm,pl330", "arm,primecell";
 222                         reg = <0xffb20000 0x4000>;
 223                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 224                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 225                         #dma-cells = <1>;
 226                         arm,pl330-broken-no-flushp;
 227                         peripherals-req-type-burst;
 228                         clocks = <&cru ACLK_DMAC1>;
 229                         clock-names = "apb_pclk";
 230                 };
 231         };
 232
 233         reserved-memory {
 234                 #address-cells = <1>;
 235                 #size-cells = <1>;
 236                 ranges;
 237
 238                 /*
 239                  * The rk3288 cannot use the memory area above 0xfe000000
 240                  * for dma operations for some reason. While there is
 241                  * probably a better solution available somewhere, we
 242                  * haven't found it yet and while devices with 2GB of ram
 243                  * are not affected, this issue prevents 4GB from booting.
 244                  * So to make these devices at least bootable, block
 245                  * this area for the time being until the real solution
 246                  * is found.
 247                  */
 248                 dma-unusable@fe000000 {
 249                         reg = <0xfe000000 0x1000000>;
 250                 };
 251         };
 252
 253         xin24m: oscillator {
 254                 compatible = "fixed-clock";
 255                 clock-frequency = <24000000>;
 256                 clock-output-names = "xin24m";
 257                 #clock-cells = <0>;
 258         };
 259
 260         timer {
 261                 compatible = "arm,armv7-timer";
 262                 arm,cpu-registers-not-fw-configured;
 263                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 264                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 265                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 266                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 267                 clock-frequency = <24000000>;
 268         };
 269
 270         timer: timer@ff810000 {
 271                 compatible = "rockchip,rk3288-timer";
 272                 reg = <0xff810000 0x20>;
 273                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 274                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 275                 clock-names = "timer", "pclk";
 276         };
 277
 278         display-subsystem {
 279                 compatible = "rockchip,display-subsystem";
 280                 ports = <&vopl_out>, <&vopb_out>;
 281         };
 282
 283         sdmmc: dwmmc@ff0c0000 {
 284                 compatible = "rockchip,rk3288-dw-mshc";
 285                 clock-freq-min-max = <400000 150000000>;
 286                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 287                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 288                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 289                 fifo-depth = <0x100>;
 290                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 291                 reg = <0xff0c0000 0x4000>;
 292                 status = "disabled";
 293         };
 294
 295         sdio0: dwmmc@ff0d0000 {
 296                 compatible = "rockchip,rk3288-dw-mshc";
 297                 clock-freq-min-max = <400000 150000000>;
 298                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 299                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 300                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 301                 fifo-depth = <0x100>;
 302                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 303                 reg = <0xff0d0000 0x4000>;
 304                 status = "disabled";
 305         };
 306
 307         sdio1: dwmmc@ff0e0000 {
 308                 compatible = "rockchip,rk3288-dw-mshc";
 309                 clock-freq-min-max = <400000 150000000>;
 310                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 311                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 312                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 313                 fifo-depth = <0x100>;
 314                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 315                 reg = <0xff0e0000 0x4000>;
 316                 status = "disabled";
 317         };
 318
 319         emmc: dwmmc@ff0f0000 {
 320                 compatible = "rockchip,rk3288-dw-mshc";
 321                 clock-freq-min-max = <400000 150000000>;
 322                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 323                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 324                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 325                 fifo-depth = <0x100>;
 326                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 327                 reg = <0xff0f0000 0x4000>;
 328                 status = "disabled";
 329                 supports-emmc;
 330         };
 331
 332         saradc: saradc@ff100000 {
 333                 compatible = "rockchip,saradc";
 334                 reg = <0xff100000 0x100>;
 335                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 336                 #io-channel-cells = <1>;
 337                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 338                 clock-names = "saradc", "apb_pclk";
 339                 resets = <&cru SRST_SARADC>;
 340                 reset-names = "saradc-apb";
 341                 status = "disabled";
 342         };
 343
 344         spi0: spi@ff110000 {
 345                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 346                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 347                 clock-names = "spiclk", "apb_pclk";
 348                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 349                 dma-names = "tx", "rx";
 350                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 351                 pinctrl-names = "default";
 352                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 353                 reg = <0xff110000 0x1000>;
 354                 #address-cells = <1>;
 355                 #size-cells = <0>;
 356                 status = "disabled";
 357         };
 358
 359         spi1: spi@ff120000 {
 360                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 361                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 362                 clock-names = "spiclk", "apb_pclk";
 363                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 364                 dma-names = "tx", "rx";
 365                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 366                 pinctrl-names = "default";
 367                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 368                 reg = <0xff120000 0x1000>;
 369                 #address-cells = <1>;
 370                 #size-cells = <0>;
 371                 status = "disabled";
 372         };
 373
 374         spi2: spi@ff130000 {
 375                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 376                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 377                 clock-names = "spiclk", "apb_pclk";
 378                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 379                 dma-names = "tx", "rx";
 380                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 381                 pinctrl-names = "default";
 382                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 383                 reg = <0xff130000 0x1000>;
 384                 #address-cells = <1>;
 385                 #size-cells = <0>;
 386                 status = "disabled";
 387         };
 388
 389         i2c0: i2c@ff650000 {
 390                 compatible = "rockchip,rk3288-i2c";
 391                 reg = <0xff650000 0x1000>;
 392                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 393                 #address-cells = <1>;
 394                 #size-cells = <0>;
 395                 clock-names = "i2c";
 396                 clocks = <&cru PCLK_I2C0>;
 397                 pinctrl-names = "default";
 398                 pinctrl-0 = <&i2c0_xfer>;
 399                 status = "disabled";
 400         };
 401
 402         i2c1: i2c@ff140000 {
 403                 compatible = "rockchip,rk3288-i2c";
 404                 reg = <0xff140000 0x1000>;
 405                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 406                 #address-cells = <1>;
 407                 #size-cells = <0>;
 408                 clock-names = "i2c";
 409                 clocks = <&cru PCLK_I2C1>;
 410                 pinctrl-names = "default";
 411                 pinctrl-0 = <&i2c1_xfer>;
 412                 status = "disabled";
 413         };
 414
 415         i2c3: i2c@ff150000 {
 416                 compatible = "rockchip,rk3288-i2c";
 417                 reg = <0xff150000 0x1000>;
 418                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 419                 #address-cells = <1>;
 420                 #size-cells = <0>;
 421                 clock-names = "i2c";
 422                 clocks = <&cru PCLK_I2C3>;
 423                 pinctrl-names = "default";
 424                 pinctrl-0 = <&i2c3_xfer>;
 425                 status = "disabled";
 426         };
 427
 428         i2c4: i2c@ff160000 {
 429                 compatible = "rockchip,rk3288-i2c";
 430                 reg = <0xff160000 0x1000>;
 431                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 432                 #address-cells = <1>;
 433                 #size-cells = <0>;
 434                 clock-names = "i2c";
 435                 clocks = <&cru PCLK_I2C4>;
 436                 pinctrl-names = "default";
 437                 pinctrl-0 = <&i2c4_xfer>;
 438                 status = "disabled";
 439         };
 440
 441         i2c5: i2c@ff170000 {
 442                 compatible = "rockchip,rk3288-i2c";
 443                 reg = <0xff170000 0x1000>;
 444                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 445                 #address-cells = <1>;
 446                 #size-cells = <0>;
 447                 clock-names = "i2c";
 448                 clocks = <&cru PCLK_I2C5>;
 449                 pinctrl-names = "default";
 450                 pinctrl-0 = <&i2c5_xfer>;
 451                 status = "disabled";
 452         };
 453
 454         uart0: serial@ff180000 {
 455                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 456                 reg = <0xff180000 0x100>;
 457                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 458                 reg-shift = <2>;
 459                 reg-io-width = <4>;
 460                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 461                 clock-names = "baudclk", "apb_pclk";
 462                 pinctrl-names = "default";
 463                 pinctrl-0 = <&uart0_xfer>;
 464                 status = "disabled";
 465         };
 466
 467         uart1: serial@ff190000 {
 468                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 469                 reg = <0xff190000 0x100>;
 470                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 471                 reg-shift = <2>;
 472                 reg-io-width = <4>;
 473                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 474                 clock-names = "baudclk", "apb_pclk";
 475                 pinctrl-names = "default";
 476                 pinctrl-0 = <&uart1_xfer>;
 477                 status = "disabled";
 478         };
 479
 480         uart2: serial@ff690000 {
 481                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 482                 reg = <0xff690000 0x100>;
 483                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 484                 reg-shift = <2>;
 485                 reg-io-width = <4>;
 486                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 487                 clock-names = "baudclk", "apb_pclk";
 488                 pinctrl-names = "default";
 489                 pinctrl-0 = <&uart2_xfer>;
 490                 status = "disabled";
 491         };
 492
 493         uart3: serial@ff1b0000 {
 494                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 495                 reg = <0xff1b0000 0x100>;
 496                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 497                 reg-shift = <2>;
 498                 reg-io-width = <4>;
 499                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 500                 clock-names = "baudclk", "apb_pclk";
 501                 pinctrl-names = "default";
 502                 pinctrl-0 = <&uart3_xfer>;
 503                 status = "disabled";
 504         };
 505
 506         uart4: serial@ff1c0000 {
 507                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 508                 reg = <0xff1c0000 0x100>;
 509                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 510                 reg-shift = <2>;
 511                 reg-io-width = <4>;
 512                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 513                 clock-names = "baudclk", "apb_pclk";
 514                 pinctrl-names = "default";
 515                 pinctrl-0 = <&uart4_xfer>;
 516                 status = "disabled";
 517         };
 518
 519         thermal_zones: thermal-zones {
 520                 soc_thermal: soc-thermal {
 521                         polling-delay-passive = <200>; /* milliseconds */
 522                         polling-delay = <1000>; /* milliseconds */
 523                         sustainable-power = <1200>; /* milliwatts */
 524
 525                         thermal-sensors = <&tsadc 1>;
 526                         trips {
 527                                 threshold: trip-point@0 {
 528                                         temperature = <75000>; /* millicelsius */
 529                                         hysteresis = <2000>; /* millicelsius */
 530                                         type = "passive";
 531                                 };
 532                                 target: trip-point@1 {
 533                                         temperature = <85000>; /* millicelsius */
 534                                         hysteresis = <2000>; /* millicelsius */
 535                                         type = "passive";
 536                                 };
 537                                 soc_crit: soc-crit {
 538                                         temperature = <90000>; /* millicelsius */
 539                                         hysteresis = <2000>; /* millicelsius */
 540                                         type = "critical";
 541                                 };
 542                         };
 543
 544                         cooling-maps {
 545                                 map0 {
 546                                         trip = <&target>;
 547                                         cooling-device =
 548                                         <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 549                                         contribution = <1024>;
 550                                 };
 551                                 map1 {
 552                                         trip = <&target>;
 553                                         cooling-device =
 554                                         <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 555                                         contribution = <1024>;
 556                                 };
 557                         };
 558                 };
 559
 560                 gpu_thermal: gpu-thermal {
 561                         polling-delay-passive = <200>; /* milliseconds */
 562                         polling-delay = <1000>; /* milliseconds */
 563                         thermal-sensors = <&tsadc 2>;
 564                 };
 565         };
 566
 567         tsadc: tsadc@ff280000 {
 568                 compatible = "rockchip,rk3288-tsadc";
 569                 reg = <0xff280000 0x100>;
 570                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 571                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 572                 clock-names = "tsadc", "apb_pclk";
 573                 assigned-clocks = <&cru SCLK_TSADC>;
 574                 assigned-clock-rates = <10000>;
 575                 resets = <&cru SRST_TSADC>;
 576                 reset-names = "tsadc-apb";
 577                 pinctrl-names = "init", "default", "sleep";
 578                 pinctrl-0 = <&otp_gpio>;
 579                 pinctrl-1 = <&otp_out>;
 580                 pinctrl-2 = <&otp_gpio>;
 581                 #thermal-sensor-cells = <1>;
 582                 rockchip,hw-tshut-temp = <95000>;
 583                 status = "disabled";
 584         };
 585
 586         gmac: ethernet@ff290000 {
 587                 compatible = "rockchip,rk3288-gmac";
 588                 reg = <0xff290000 0x10000>;
 589                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 590                                 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 591                 interrupt-names = "macirq", "eth_wake_irq";
 592                 rockchip,grf = <&grf>;
 593                 clocks = <&cru SCLK_MAC>,
 594                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 595                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 596                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 597                 clock-names = "stmmaceth",
 598                         "mac_clk_rx", "mac_clk_tx",
 599                         "clk_mac_ref", "clk_mac_refout",
 600                         "aclk_mac", "pclk_mac";
 601                 resets = <&cru SRST_MAC>;
 602                 reset-names = "stmmaceth";
 603                 status = "disabled";
 604         };
 605
 606         usb_host0_ehci: usb@ff500000 {
 607                 compatible = "generic-ehci";
 608                 reg = <0xff500000 0x100>;
 609                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 610                 clocks = <&cru HCLK_USBHOST0>;
 611                 clock-names = "usbhost";
 612                 phys = <&usbphy1>;
 613                 phy-names = "usb";
 614                 status = "disabled";
 615         };
 616
 617         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 618
 619         usb_host1: usb@ff540000 {
 620                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 621                                 "snps,dwc2";
 622                 reg = <0xff540000 0x40000>;
 623                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 624                 clocks = <&cru HCLK_USBHOST1>;
 625                 clock-names = "otg";
 626                 dr_mode = "host";
 627                 phys = <&usbphy2>;
 628                 phy-names = "usb2-phy";
 629                 status = "disabled";
 630         };
 631
 632         usb_otg: usb@ff580000 {
 633                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 634                                 "snps,dwc2";
 635                 reg = <0xff580000 0x40000>;
 636                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 637                 clocks = <&cru HCLK_OTG0>;
 638                 clock-names = "otg";
 639                 dr_mode = "otg";
 640                 g-np-tx-fifo-size = <16>;
 641                 g-rx-fifo-size = <275>;
 642                 g-tx-fifo-size = <256 128 128 64 64 32>;
 643                 g-use-dma;
 644                 phys = <&usbphy0>;
 645                 phy-names = "usb2-phy";
 646                 status = "disabled";
 647         };
 648
 649         usb_hsic: usb@ff5c0000 {
 650                 compatible = "generic-ehci";
 651                 reg = <0xff5c0000 0x100>;
 652                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 653                 clocks = <&cru HCLK_HSIC>;
 654                 clock-names = "usbhost";
 655                 status = "disabled";
 656         };
 657
 658         dmc: dmc@ff610000 {
 659                 compatible = "rockchip,rk3288-dmc", "syscon";
 660                 rockchip,cru = <&cru>;
 661                 rockchip,grf = <&grf>;
 662                 rockchip,pmu = <&pmu>;
 663                 rockchip,sgrf = <&sgrf>;
 664                 rockchip,noc = <&noc>;
 665                 reg = <0xff610000 0x3fc
 666                        0xff620000 0x294
 667                        0xff630000 0x3fc
 668                        0xff640000 0x294>;
 669                 rockchip,sram = <&ddr_sram>;
 670                 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
 671                          <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
 672                          <&cru ARMCLK>, <&cru ACLK_DMAC1>;
 673                 clock-names = "pclk_ddrupctl0", "pclk_publ0",
 674                               "pclk_ddrupctl1", "pclk_publ1",
 675                               "arm_clk", "aclk_dmac1";
 676         };
 677
 678         i2c2: i2c@ff660000 {
 679                 compatible = "rockchip,rk3288-i2c";
 680                 reg = <0xff660000 0x1000>;
 681                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 682                 #address-cells = <1>;
 683                 #size-cells = <0>;
 684                 clock-names = "i2c";
 685                 clocks = <&cru PCLK_I2C2>;
 686                 pinctrl-names = "default";
 687                 pinctrl-0 = <&i2c2_xfer>;
 688                 status = "disabled";
 689         };
 690
 691         pwm0: pwm@ff680000 {
 692                 compatible = "rockchip,rk3288-pwm";
 693                 reg = <0xff680000 0x10>;
 694                 #pwm-cells = <3>;
 695                 pinctrl-names = "default";
 696                 pinctrl-0 = <&pwm0_pin>;
 697                 clocks = <&cru PCLK_PWM>;
 698                 clock-names = "pwm";
 699                 status = "disabled";
 700         };
 701
 702         pwm1: pwm@ff680010 {
 703                 compatible = "rockchip,rk3288-pwm";
 704                 reg = <0xff680010 0x10>;
 705                 #pwm-cells = <3>;
 706                 pinctrl-names = "default";
 707                 pinctrl-0 = <&pwm1_pin>;
 708                 clocks = <&cru PCLK_PWM>;
 709                 clock-names = "pwm";
 710                 status = "disabled";
 711         };
 712
 713         pwm2: pwm@ff680020 {
 714                 compatible = "rockchip,rk3288-pwm";
 715                 reg = <0xff680020 0x10>;
 716                 #pwm-cells = <3>;
 717                 pinctrl-names = "default";
 718                 pinctrl-0 = <&pwm2_pin>;
 719                 clocks = <&cru PCLK_PWM>;
 720                 clock-names = "pwm";
 721                 status = "disabled";
 722         };
 723
 724         pwm3: pwm@ff680030 {
 725                 compatible = "rockchip,rk3288-pwm";
 726                 reg = <0xff680030 0x10>;
 727                 #pwm-cells = <2>;
 728                 pinctrl-names = "default";
 729                 pinctrl-0 = <&pwm3_pin>;
 730                 clocks = <&cru PCLK_PWM>;
 731                 clock-names = "pwm";
 732                 status = "disabled";
 733         };
 734
 735         bus_intmem@ff700000 {
 736                 compatible = "mmio-sram";
 737                 reg = <0xff700000 0x18000>;
 738                 #address-cells = <1>;
 739                 #size-cells = <1>;
 740                 ranges = <0 0xff700000 0x18000>;
 741                 smp-sram@0 {
 742                         compatible = "rockchip,rk3066-smp-sram";
 743                         reg = <0x00 0x10>;
 744                 };
 745                 ddr_sram: ddr-sram@1000 {
 746                         compatible = "rockchip,rk3288-ddr-sram";
 747                         reg = <0x1000 0x4000>;
 748                 };
 749         };
 750
 751         sram@ff720000 {
 752                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 753                 reg = <0xff720000 0x1000>;
 754         };
 755
 756         qos_gpu_r: qos@ffaa0000 {
 757                 compatible = "syscon";
 758                 reg = <0xffaa0000 0x20>;
 759         };
 760
 761         qos_gpu_w: qos@ffaa0080 {
 762                 compatible = "syscon";
 763                 reg = <0xffaa0080 0x20>;
 764         };
 765
 766         qos_vio1_vop: qos@ffad0000 {
 767                 compatible = "syscon";
 768                 reg = <0xffad0000 0x20>;
 769         };
 770
 771         qos_vio1_isp_w0: qos@ffad0100 {
 772                 compatible = "syscon";
 773                 reg = <0xffad0100 0x20>;
 774         };
 775
 776         qos_vio1_isp_w1: qos@ffad0180 {
 777                 compatible = "syscon";
 778                 reg = <0xffad0180 0x20>;
 779         };
 780
 781         qos_vio0_vop: qos@ffad0400 {
 782                 compatible = "syscon";
 783                 reg = <0xffad0400 0x20>;
 784         };
 785
 786         qos_vio0_vip: qos@ffad0480 {
 787                 compatible = "syscon";
 788                 reg = <0xffad0480 0x20>;
 789         };
 790
 791         qos_vio0_iep: qos@ffad0500 {
 792                 compatible = "syscon";
 793                 reg = <0xffad0500 0x20>;
 794         };
 795
 796         qos_vio2_rga_r: qos@ffad0800 {
 797                 compatible = "syscon";
 798                 reg = <0xffad0800 0x20>;
 799         };
 800
 801         qos_vio2_rga_w: qos@ffad0880 {
 802                 compatible = "syscon";
 803                 reg = <0xffad0880 0x20>;
 804         };
 805
 806         qos_vio1_isp_r: qos@ffad0900 {
 807                 compatible = "syscon";
 808                 reg = <0xffad0900 0x20>;
 809         };
 810
 811         qos_video: qos@ffae0000 {
 812                 compatible = "syscon";
 813                 reg = <0xffae0000 0x20>;
 814         };
 815
 816         qos_hevc_r: qos@ffaf0000 {
 817                 compatible = "syscon";
 818                 reg = <0xffaf0000 0x20>;
 819         };
 820
 821         qos_hevc_w: qos@ffaf0080 {
 822                 compatible = "syscon";
 823                 reg = <0xffaf0080 0x20>;
 824         };
 825
 826         pmu: power-management@ff730000 {
 827                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 828                 reg = <0xff730000 0x100>;
 829
 830                 power: power-controller {
 831                         compatible = "rockchip,rk3288-power-controller";
 832                         #power-domain-cells = <1>;
 833                         #address-cells = <1>;
 834                         #size-cells = <0>;
 835
 836                         /*
 837                          * Note: Although SCLK_* are the working clocks
 838                          * of device without including on the NOC, needed for
 839                          * synchronous reset.
 840                          *
 841                          * The clocks on the which NOC:
 842                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 843                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 844                          * ACLK_RGA is on ACLK_RGA_NIU.
 845                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 846                          *
 847                          * Which clock are device clocks:
 848                          *      clocks          devices
 849                          *      *_IEP           IEP:Image Enhancement Processor
 850                          *      *_ISP           ISP:Image Signal Processing
 851                          *      *_VIP           VIP:Video Input Processor
 852                          *      *_VOP*          VOP:Visual Output Processor
 853                          *      *_RGA           RGA
 854                          *      *_EDP*          EDP
 855                          *      *_LVDS_*        LVDS
 856                          *      *_HDMI          HDMI
 857                          *      *_MIPI_*        MIPI
 858                          */
 859                         pd_vio@RK3288_PD_VIO {
 860                                 reg = <RK3288_PD_VIO>;
 861                                 clocks = <&cru ACLK_IEP>,
 862                                          <&cru ACLK_ISP>,
 863                                          <&cru ACLK_RGA>,
 864                                          <&cru ACLK_VIP>,
 865                                          <&cru ACLK_VOP0>,
 866                                          <&cru ACLK_VOP1>,
 867                                          <&cru DCLK_VOP0>,
 868                                          <&cru DCLK_VOP1>,
 869                                          <&cru HCLK_IEP>,
 870                                          <&cru HCLK_ISP>,
 871                                          <&cru HCLK_RGA>,
 872                                          <&cru HCLK_VIP>,
 873                                          <&cru HCLK_VOP0>,
 874                                          <&cru HCLK_VOP1>,
 875                                          <&cru PCLK_EDP_CTRL>,
 876                                          <&cru PCLK_HDMI_CTRL>,
 877                                          <&cru PCLK_LVDS_PHY>,
 878                                          <&cru PCLK_MIPI_CSI>,
 879                                          <&cru PCLK_MIPI_DSI0>,
 880                                          <&cru PCLK_MIPI_DSI1>,
 881                                          <&cru SCLK_EDP_24M>,
 882                                          <&cru SCLK_EDP>,
 883                                          <&cru SCLK_ISP_JPE>,
 884                                          <&cru SCLK_ISP>,
 885                                          <&cru SCLK_RGA>;
 886                                 pm_qos = <&qos_vio0_iep>,
 887                                          <&qos_vio1_vop>,
 888                                          <&qos_vio1_isp_w0>,
 889                                          <&qos_vio1_isp_w1>,
 890                                          <&qos_vio0_vop>,
 891                                          <&qos_vio0_vip>,
 892                                          <&qos_vio2_rga_r>,
 893                                          <&qos_vio2_rga_w>,
 894                                          <&qos_vio1_isp_r>;
 895                         };
 896
 897                         /*
 898                          * Note: The following 3 are HEVC(H.265) clocks,
 899                          * and on the ACLK_HEVC_NIU (NOC).
 900                          */
 901                         pd_hevc@RK3288_PD_HEVC {
 902                                 reg = <RK3288_PD_HEVC>;
 903                                 clocks = <&cru ACLK_HEVC>,
 904                                          <&cru SCLK_HEVC_CABAC>,
 905                                          <&cru SCLK_HEVC_CORE>;
 906                                 pm_qos = <&qos_hevc_r>,
 907                                          <&qos_hevc_w>;
 908                         };
 909
 910                         /*
 911                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 912                          * (video endecoder & decoder) clocks that on the
 913                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 914                          */
 915                         pd_video@RK3288_PD_VIDEO {
 916                                 reg = <RK3288_PD_VIDEO>;
 917                                 clocks = <&cru ACLK_VCODEC>,
 918                                          <&cru HCLK_VCODEC>;
 919                                 pm_qos = <&qos_video>;
 920                         };
 921
 922                         /*
 923                          * Note: ACLK_GPU is the GPU clock,
 924                          * and on the ACLK_GPU_NIU (NOC).
 925                          */
 926                         pd_gpu@RK3288_PD_GPU {
 927                                 reg = <RK3288_PD_GPU>;
 928                                 clocks = <&cru ACLK_GPU>;
 929                                 pm_qos = <&qos_gpu_r>,
 930                                          <&qos_gpu_w>;
 931                         };
 932                 };
 933
 934                 reboot-mode {
 935                         compatible = "syscon-reboot-mode";
 936                         offset = <0x94>;
 937                         mode-normal = <BOOT_NORMAL>;
 938                         mode-recovery = <BOOT_RECOVERY>;
 939                         mode-bootloader = <BOOT_FASTBOOT>;
 940                         mode-loader = <BOOT_BL_DOWNLOAD>;
 941                         mode-ums = <BOOT_UMS>;
 942                 };
 943         };
 944
 945         sgrf: syscon@ff740000 {
 946                 compatible = "rockchip,rk3288-sgrf", "syscon";
 947                 reg = <0xff740000 0x1000>;
 948         };
 949
 950         cru: clock-controller@ff760000 {
 951                 compatible = "rockchip,rk3288-cru";
 952                 reg = <0xff760000 0x1000>;
 953                 rockchip,grf = <&grf>;
 954                 #clock-cells = <1>;
 955                 #reset-cells = <1>;
 956                 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
 957                                   <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 958                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 959                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 960                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 961                                   <&cru PCLK_PERI>;
 962                 assigned-clock-rates = <0>, <0>,
 963                                        <594000000>, <400000000>,
 964                                        <500000000>, <300000000>,
 965                                        <150000000>, <75000000>,
 966                                        <300000000>, <150000000>,
 967                                        <75000000>;
 968                 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
 969         };
 970
 971         grf: syscon@ff770000 {
 972                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 973                 reg = <0xff770000 0x1000>;
 974
 975                 edp_phy: edp-phy {
 976                         compatible = "rockchip,rk3288-dp-phy";
 977                         clocks = <&cru SCLK_EDP_24M>;
 978                         clock-names = "24m";
 979                         #phy-cells = <0>;
 980                         status = "disabled";
 981                 };
 982
 983                 io_domains: io-domains {
 984                         compatible = "rockchip,rk3288-io-voltage-domain";
 985                         status = "disabled";
 986                 };
 987
 988                 usbphy: usbphy {
 989                         compatible = "rockchip,rk3288-usb-phy";
 990                         #address-cells = <1>;
 991                         #size-cells = <0>;
 992                         status = "disabled";
 993
 994                         usbphy0: usb-phy@320 {
 995                                 #phy-cells = <0>;
 996                                 reg = <0x320>;
 997                                 clocks = <&cru SCLK_OTGPHY0>;
 998                                 clock-names = "phyclk";
 999                                 #clock-cells = <0>;
1000                                 resets = <&cru SRST_USBOTG_PHY>;
1001                                 reset-names = "phy-reset";
1002                         };
1003
1004                         usbphy1: usb-phy@334 {
1005                                 #phy-cells = <0>;
1006                                 reg = <0x334>;
1007                                 clocks = <&cru SCLK_OTGPHY1>;
1008                                 clock-names = "phyclk";
1009                                 #clock-cells = <0>;
1010                         };
1011
1012                         usbphy2: usb-phy@348 {
1013                                 #phy-cells = <0>;
1014                                 reg = <0x348>;
1015                                 clocks = <&cru SCLK_OTGPHY2>;
1016                                 clock-names = "phyclk";
1017                                 #clock-cells = <0>;
1018                                 resets = <&cru SRST_USBHOST1_PHY>;
1019                                 reset-names = "phy-reset";
1020                         };
1021                 };
1022         };
1023
1024         wdt: watchdog@ff800000 {
1025                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
1026                 reg = <0xff800000 0x100>;
1027                 clocks = <&cru PCLK_WDT>;
1028                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1029                 status = "disabled";
1030         };
1031
1032         spdif: sound@ff8b0000 {
1033                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
1034                 reg = <0xff8b0000 0x10000>;
1035                 #sound-dai-cells = <0>;
1036                 clock-names = "hclk", "mclk";
1037                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
1038                 dmas = <&dmac_bus_s 3>;
1039                 dma-names = "tx";
1040                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1041                 pinctrl-names = "default";
1042                 pinctrl-0 = <&spdif_tx>;
1043                 rockchip,grf = <&grf>;
1044                 status = "disabled";
1045         };
1046
1047         i2s: i2s@ff890000 {
1048                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
1049                 reg = <0xff890000 0x10000>;
1050                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1051                 #address-cells = <1>;
1052                 #size-cells = <0>;
1053                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
1054                 dma-names = "tx", "rx";
1055                 clock-names = "i2s_hclk", "i2s_clk";
1056                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
1057                 pinctrl-names = "default";
1058                 pinctrl-0 = <&i2s0_bus>;
1059                 rockchip,playback-channels = <8>;
1060                 rockchip,capture-channels = <2>;
1061                 status = "disabled";
1062         };
1063
1064         cif_isp0: cif_isp@ff910000 {
1065                 compatible = "rockchip,rk3288-cif-isp";
1066                 rockchip,grf = <&grf>;
1067                 reg = <0xff910000 0x10000>, <0xff968000 0x4000>;
1068                 reg-names = "register", "csihost-register";
1069                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1070                         <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
1071                         <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
1072                         <&cru SCLK_MIPIDSI_24M>;
1073                 clock-names = "aclk_isp", "hclk_isp",
1074                         "sclk_isp", "sclk_isp_jpe",
1075                         "pclk_mipi_csi", "pclk_isp_in",
1076                         "sclk_mipidsi_24m";
1077                 resets = <&cru SRST_ISP>;
1078                 reset-names = "rst_isp";
1079                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1080                 interrupt-names = "cif_isp10_irq";
1081                 status = "disabled";
1082         };
1083
1084         isp: isp@ff910000 {
1085                 compatible = "rockchip,rk3288-isp", "rockchip,isp";
1086                 reg = <0xff910000 0x4000>;
1087                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1088                 power-domains = <&power RK3288_PD_VIO>;
1089                 clocks =
1090                         <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
1091                         <&cru SCLK_ISP_JPE>, <&cru PCLK_ISP_IN>,
1092                         <&cru SCLK_VIP_OUT>, <&cru SCLK_MIPIDSI_24M>,
1093                         <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>;
1094                 clock-names =
1095                         "aclk_isp", "hclk_isp", "clk_isp",
1096                         "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
1097                         "clk_mipi_24m", "clk_cif_pll", "hclk_mipiphy1";
1098                 pinctrl-names =
1099                         "default", "isp_dvp8bit2", "isp_dvp10bit",
1100                         "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl",
1101                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
1102                         "isp_flash_as_trigger_out";
1103                 pinctrl-0 = <&isp_mipi>;
1104                 pinctrl-1 = <&isp_mipi &isp_dvp_d2d9>;
1105                 pinctrl-2 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1>;
1106                 pinctrl-3 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1
1107                                         &isp_dvp_d10d11>;
1108                 pinctrl-4 = <&isp_mipi &isp_dvp_d0d7>;
1109                 pinctrl-5 = <&isp_mipi>;
1110                 pinctrl-6 = <&isp_mipi &isp_prelight>;
1111                 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1112                 pinctrl-8 = <&isp_flash_trigger>;
1113                 rockchip,isp,mipiphy = <2>;
1114                 rockchip,isp,cifphy = <1>;
1115                 rockchip,isp,mipiphy1,reg = <0xff968000 0x4000>;
1116                 rockchip,grf = <&grf>;
1117                 rockchip,cru = <&cru>;
1118                 rockchip,gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>;
1119                 rockchip,isp,iommu_enable = <1>;
1120                 iommus = <&isp_mmu>;
1121                 status = "disabled";
1122         };
1123
1124         isp_mmu: iommu@ff914000 {
1125                 compatible = "rockchip,iommu";
1126                 reg = <0xff914000 0x100>, <0xff915000 0x100>;
1127                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1128                 interrupt-names = "isp_mmu";
1129                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1130                 clock-names = "aclk", "hclk";
1131                 rk_iommu,disable_reset_quirk;
1132                 #iommu-cells = <0>;
1133                 power-domains = <&power RK3288_PD_VIO>;
1134                 status = "disabled";
1135         };
1136
1137         rga: rga@ff920000 {
1138                 compatible = "rockchip,rk3288-rga";
1139                 reg = <0xff920000 0x180>;
1140                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1141                 interrupt-names = "rga";
1142                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1143                 clock-names = "aclk", "hclk", "sclk";
1144                 power-domains = <&power RK3288_PD_VIO>;
1145                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1146                 reset-names = "core", "axi", "ahb";
1147                 dma-coherent;
1148                 status = "disabled";
1149         };
1150
1151         vopb: vop@ff930000 {
1152                 compatible = "rockchip,rk3288-vop";
1153                 reg = <0xff930000 0x19c>;
1154                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1155                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1156                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1157                 power-domains = <&power RK3288_PD_VIO>;
1158                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1159                 reset-names = "axi", "ahb", "dclk";
1160                 iommus = <&vopb_mmu>;
1161                 status = "disabled";
1162
1163                 vopb_out: port {
1164                         #address-cells = <1>;
1165                         #size-cells = <0>;
1166
1167                         vopb_out_hdmi: endpoint@0 {
1168                                 reg = <0>;
1169                                 remote-endpoint = <&hdmi_in_vopb>;
1170                         };
1171
1172                         vopb_out_edp: endpoint@1 {
1173                                 reg = <1>;
1174                                 remote-endpoint = <&edp_in_vopb>;
1175                         };
1176
1177                         vopb_out_mipi: endpoint@2 {
1178                                 reg = <2>;
1179                                 remote-endpoint = <&mipi_in_vopb>;
1180                         };
1181
1182                         vopb_out_lvds: endpoint@3 {
1183                                 reg = <3>;
1184                                 remote-endpoint = <&lvds_in_vopb>;
1185                         };
1186                 };
1187         };
1188
1189         vopb_mmu: iommu@ff930300 {
1190                 compatible = "rockchip,iommu";
1191                 reg = <0xff930300 0x100>;
1192                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1193                 interrupt-names = "vopb_mmu";
1194                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1195                 clock-names = "aclk", "hclk";
1196                 power-domains = <&power RK3288_PD_VIO>;
1197                 #iommu-cells = <0>;
1198                 status = "disabled";
1199         };
1200
1201         vopl: vop@ff940000 {
1202                 compatible = "rockchip,rk3288-vop";
1203                 reg = <0xff940000 0x19c>;
1204                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1205                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1206                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1207                 power-domains = <&power RK3288_PD_VIO>;
1208                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1209                 reset-names = "axi", "ahb", "dclk";
1210                 iommus = <&vopl_mmu>;
1211                 status = "disabled";
1212
1213                 vopl_out: port {
1214                         #address-cells = <1>;
1215                         #size-cells = <0>;
1216
1217                         vopl_out_hdmi: endpoint@0 {
1218                                 reg = <0>;
1219                                 remote-endpoint = <&hdmi_in_vopl>;
1220                         };
1221
1222                         vopl_out_edp: endpoint@1 {
1223                                 reg = <1>;
1224                                 remote-endpoint = <&edp_in_vopl>;
1225                         };
1226
1227                         vopl_out_mipi: endpoint@2 {
1228                                 reg = <2>;
1229                                 remote-endpoint = <&mipi_in_vopl>;
1230                         };
1231
1232                         vopl_out_lvds: endpoint@3 {
1233                                 reg = <3>;
1234                                 remote-endpoint = <&lvds_in_vopl>;
1235                         };
1236
1237                 };
1238         };
1239
1240         vopl_mmu: iommu@ff940300 {
1241                 compatible = "rockchip,iommu";
1242                 reg = <0xff940300 0x100>;
1243                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1244                 interrupt-names = "vopl_mmu";
1245                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1246                 clock-names = "aclk", "hclk";
1247                 power-domains = <&power RK3288_PD_VIO>;
1248                 #iommu-cells = <0>;
1249                 status = "disabled";
1250         };
1251
1252         mipi_dsi: mipi@ff960000 {
1253                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1254                 reg = <0xff960000 0x4000>;
1255                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1256                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1257                 clock-names = "ref", "pclk";
1258                 power-domains = <&power RK3288_PD_VIO>;
1259                 rockchip,grf = <&grf>;
1260                 #address-cells = <1>;
1261                 #size-cells = <0>;
1262                 status = "disabled";
1263
1264                 ports {
1265                         mipi_in: port {
1266                                 #address-cells = <1>;
1267                                 #size-cells = <0>;
1268                                 mipi_in_vopb: endpoint@0 {
1269                                         reg = <0>;
1270                                         remote-endpoint = <&vopb_out_mipi>;
1271                                 };
1272                                 mipi_in_vopl: endpoint@1 {
1273                                         reg = <1>;
1274                                         remote-endpoint = <&vopl_out_mipi>;
1275                                 };
1276                         };
1277                 };
1278         };
1279
1280         edp: dp@ff970000 {
1281                 compatible = "rockchip,rk3288-dp";
1282                 reg = <0xff970000 0x4000>;
1283                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1284                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1285                 clock-names = "dp", "pclk";
1286                 power-domains = <&power RK3288_PD_VIO>;
1287                 phys = <&edp_phy>;
1288                 phy-names = "dp";
1289                 resets = <&cru SRST_EDP>;
1290                 reset-names = "dp";
1291                 rockchip,grf = <&grf>;
1292                 status = "disabled";
1293
1294                 ports {
1295                         #address-cells = <1>;
1296                         #size-cells = <0>;
1297                         edp_in: port@0 {
1298                                 reg = <0>;
1299                                 #address-cells = <1>;
1300                                 #size-cells = <0>;
1301                                 edp_in_vopb: endpoint@0 {
1302                                         reg = <0>;
1303                                         remote-endpoint = <&vopb_out_edp>;
1304                                 };
1305                                 edp_in_vopl: endpoint@1 {
1306                                         reg = <1>;
1307                                         remote-endpoint = <&vopl_out_edp>;
1308                                 };
1309                         };
1310                 };
1311         };
1312
1313         lvds: lvds@ff96c000 {
1314                 compatible = "rockchip,rk3288-lvds";
1315                 reg = <0xff96c000 0x4000>;
1316                 clocks = <&cru PCLK_LVDS_PHY>;
1317                 clock-names = "pclk_lvds";
1318                 pinctrl-names = "default";
1319                 pinctrl-0 = <&lcdc0_ctl>;
1320                 power-domains = <&power RK3288_PD_VIO>;
1321                 rockchip,grf = <&grf>;
1322                 status = "disabled";
1323
1324                 ports {
1325                         #address-cells = <1>;
1326                         #size-cells = <0>;
1327
1328                         lvds_in: port@0 {
1329                                 reg = <0>;
1330
1331                                 #address-cells = <1>;
1332                                 #size-cells = <0>;
1333
1334                                 lvds_in_vopb: endpoint@0 {
1335                                         reg = <0>;
1336                                         remote-endpoint = <&vopb_out_lvds>;
1337                                 };
1338                                 lvds_in_vopl: endpoint@1 {
1339                                         reg = <1>;
1340                                         remote-endpoint = <&vopl_out_lvds>;
1341                                 };
1342                         };
1343                 };
1344         };
1345
1346         hdmi: hdmi@ff980000 {
1347                 compatible = "rockchip,rk3288-dw-hdmi";
1348                 reg = <0xff980000 0x20000>;
1349                 reg-io-width = <4>;
1350                 rockchip,grf = <&grf>;
1351                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1352                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1353                 clock-names = "iahb", "isfr";
1354                 pinctrl-names = "default";
1355                 pinctrl-0 = <&hdmi_ddc>;
1356                 power-domains = <&power RK3288_PD_VIO>;
1357                 status = "disabled";
1358
1359                 ports {
1360                         hdmi_in: port {
1361                                 #address-cells = <1>;
1362                                 #size-cells = <0>;
1363                                 hdmi_in_vopb: endpoint@0 {
1364                                         reg = <0>;
1365                                         remote-endpoint = <&vopb_out_hdmi>;
1366                                 };
1367                                 hdmi_in_vopl: endpoint@1 {
1368                                         reg = <1>;
1369                                         remote-endpoint = <&vopl_out_hdmi>;
1370                                 };
1371                         };
1372                 };
1373         };
1374
1375         vpu: video-codec@ff9a0000 {
1376                 compatible = "rockchip,rk3288-vpu";
1377                 reg = <0xff9a0000 0x800>;
1378                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1379                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1380                 interrupt-names = "vepu", "vdpu";
1381                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1382                 clock-names = "aclk", "hclk";
1383                 power-domains = <&power RK3288_PD_VIDEO>;
1384                 iommus = <&vpu_mmu>;
1385                 assigned-clocks = <&cru ACLK_VCODEC>;
1386                 assigned-clock-rates = <400000000>;
1387                 status = "disabled";
1388         };
1389
1390         vpu_service: vpu-service@ff9a0000 {
1391                 compatible = "rockchip,vpu_service";
1392                 reg = <0xff9a0000 0x800>;
1393                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1394                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1395                 interrupt-names = "irq_enc", "irq_dec";
1396                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1397                 clock-names = "aclk_vcodec", "hclk_vcodec";
1398                 power-domains = <&power RK3288_PD_VIDEO>;
1399                 rockchip,grf = <&grf>;
1400                 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
1401                 reset-names = "video_a", "video_h";
1402                 iommus = <&vpu_mmu>;
1403                 iommu_enabled = <1>;
1404                 dev_mode = <0>;
1405                 status = "disabled";
1406                 /* 0 means ion, 1 means drm */
1407                 allocator = <1>;
1408         };
1409
1410         vpu_mmu: iommu@ff9a0800 {
1411                 compatible = "rockchip,iommu";
1412                 reg = <0xff9a0800 0x100>;
1413                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1414                 interrupt-names = "vpu_mmu";
1415                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1416                 clock-names = "aclk", "hclk";
1417                 power-domains = <&power RK3288_PD_VIDEO>;
1418                 #iommu-cells = <0>;
1419         };
1420
1421         hevc_service: hevc-service@ff9c0000 {
1422                 compatible = "rockchip,hevc_service";
1423                 reg = <0xff9c0000 0x400>;
1424                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1425                 interrupt-names = "irq_dec";
1426                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1427                         <&cru SCLK_HEVC_CORE>,
1428                         <&cru SCLK_HEVC_CABAC>;
1429                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
1430                         "clk_cabac";
1431                 /*
1432                  * The 4K hevc would also work well with 500/125/300/300,
1433                  * no more err irq and reset request.
1434                  */
1435                 assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1436                                   <&cru SCLK_HEVC_CORE>,
1437                                   <&cru SCLK_HEVC_CABAC>;
1438                 assigned-clock-rates = <400000000>, <100000000>,
1439                                        <300000000>, <300000000>;
1440
1441                 resets = <&cru SRST_HEVC>;
1442                 reset-names = "video";
1443                 power-domains = <&power RK3288_PD_HEVC>;
1444                 rockchip,grf = <&grf>;
1445                 dev_mode = <1>;
1446                 iommus = <&hevc_mmu>;
1447                 iommu_enabled = <1>;
1448                 status = "disabled";
1449                 /* 0 means ion, 1 means drm */
1450                 allocator = <1>;
1451         };
1452
1453         hevc_mmu: iommu@ff9c0440 {
1454                 compatible = "rockchip,iommu";
1455                 reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
1456                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1457                 interrupt-names = "hevc_mmu";
1458                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1459                         <&cru SCLK_HEVC_CORE>,
1460                         <&cru SCLK_HEVC_CABAC>;
1461                 clock-names = "aclk", "hclk", "clk_core",
1462                         "clk_cabac";
1463                 power-domains = <&power RK3288_PD_HEVC>;
1464                 #iommu-cells = <0>;
1465         };
1466
1467         gpu: gpu@ffa30000 {
1468                 compatible = "arm,malit764",
1469                              "arm,malit76x",
1470                              "arm,malit7xx",
1471                              "arm,mali-midgard";
1472                 reg = <0xffa30000 0x10000>;
1473                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1474                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1475                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1476                 interrupt-names = "JOB", "MMU", "GPU";
1477                 clocks = <&cru ACLK_GPU>;
1478                 clock-names = "clk_mali";
1479                 operating-points-v2 = <&gpu_opp_table>;
1480                 #cooling-cells = <2>; /* min followed by max */
1481                 power-domains = <&power RK3288_PD_GPU>;
1482                 status = "disabled";
1483
1484                 upthreshold = <75>;
1485                 downdifferential = <10>;
1486
1487                 gpu_power_model: power_model {
1488                         compatible = "arm,mali-simple-power-model";
1489                         voltage = <950>;
1490                         frequency = <500>;
1491                         static-power = <300>;
1492                         dynamic-power = <396>;
1493                         ts = <32000 4700 (-80) 2>;
1494                         thermal-zone = "gpu-thermal";
1495                 };
1496         };
1497
1498         gpu_opp_table: opp-table1 {
1499                 compatible = "operating-points-v2";
1500
1501                 opp@100000000 {
1502                         opp-hz = /bits/ 64 <100000000>;
1503                         opp-microvolt = <950000>;
1504                 };
1505                 opp@200000000 {
1506                         opp-hz = /bits/ 64 <200000000>;
1507                         opp-microvolt = <950000>;
1508                 };
1509                 opp@300000000 {
1510                         opp-hz = /bits/ 64 <300000000>;
1511                         opp-microvolt = <1000000>;
1512                 };
1513                 opp@400000000 {
1514                         opp-hz = /bits/ 64 <400000000>;
1515                         opp-microvolt = <1100000>;
1516                 };
1517                 opp@600000000 {
1518                         opp-hz = /bits/ 64 <600000000>;
1519                         opp-microvolt = <1250000>;
1520                 };
1521         };
1522
1523         noc: syscon@ffac0000 {
1524                 compatible = "rockchip,rk3288-noc", "syscon";
1525                 reg = <0xffac0000 0x2000>;
1526         };
1527
1528         efuse: efuse@ffb40000 {
1529                 compatible = "rockchip,rockchip-efuse";
1530                 reg = <0xffb40000 0x20>;
1531                 #address-cells = <1>;
1532                 #size-cells = <1>;
1533                 clocks = <&cru PCLK_EFUSE256>;
1534                 clock-names = "pclk_efuse";
1535
1536                 cpu_leakage: cpu_leakage@17 {
1537                         reg = <0x17 0x1>;
1538                 };
1539         };
1540
1541         gic: interrupt-controller@ffc01000 {
1542                 compatible = "arm,gic-400";
1543                 interrupt-controller;
1544                 #interrupt-cells = <3>;
1545                 #address-cells = <0>;
1546
1547                 reg = <0xffc01000 0x1000>,
1548                       <0xffc02000 0x2000>,
1549                       <0xffc04000 0x2000>,
1550                       <0xffc06000 0x2000>;
1551                 interrupts = <GIC_PPI 9 0xf04>;
1552         };
1553
1554         pinctrl: pinctrl {
1555                 compatible = "rockchip,rk3288-pinctrl";
1556                 rockchip,grf = <&grf>;
1557                 rockchip,pmu = <&pmu>;
1558                 #address-cells = <1>;
1559                 #size-cells = <1>;
1560                 ranges;
1561
1562                 gpio0: gpio0@ff750000 {
1563                         compatible = "rockchip,gpio-bank";
1564                         reg =   <0xff750000 0x100>;
1565                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1566                         clocks = <&cru PCLK_GPIO0>;
1567
1568                         gpio-controller;
1569                         #gpio-cells = <2>;
1570
1571                         interrupt-controller;
1572                         #interrupt-cells = <2>;
1573                 };
1574
1575                 gpio1: gpio1@ff780000 {
1576                         compatible = "rockchip,gpio-bank";
1577                         reg = <0xff780000 0x100>;
1578                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1579                         clocks = <&cru PCLK_GPIO1>;
1580
1581                         gpio-controller;
1582                         #gpio-cells = <2>;
1583
1584                         interrupt-controller;
1585                         #interrupt-cells = <2>;
1586                 };
1587
1588                 gpio2: gpio2@ff790000 {
1589                         compatible = "rockchip,gpio-bank";
1590                         reg = <0xff790000 0x100>;
1591                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1592                         clocks = <&cru PCLK_GPIO2>;
1593
1594                         gpio-controller;
1595                         #gpio-cells = <2>;
1596
1597                         interrupt-controller;
1598                         #interrupt-cells = <2>;
1599                 };
1600
1601                 gpio3: gpio3@ff7a0000 {
1602                         compatible = "rockchip,gpio-bank";
1603                         reg = <0xff7a0000 0x100>;
1604                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1605                         clocks = <&cru PCLK_GPIO3>;
1606
1607                         gpio-controller;
1608                         #gpio-cells = <2>;
1609
1610                         interrupt-controller;
1611                         #interrupt-cells = <2>;
1612                 };
1613
1614                 gpio4: gpio4@ff7b0000 {
1615                         compatible = "rockchip,gpio-bank";
1616                         reg = <0xff7b0000 0x100>;
1617                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1618                         clocks = <&cru PCLK_GPIO4>;
1619
1620                         gpio-controller;
1621                         #gpio-cells = <2>;
1622
1623                         interrupt-controller;
1624                         #interrupt-cells = <2>;
1625                 };
1626
1627                 gpio5: gpio5@ff7c0000 {
1628                         compatible = "rockchip,gpio-bank";
1629                         reg = <0xff7c0000 0x100>;
1630                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1631                         clocks = <&cru PCLK_GPIO5>;
1632
1633                         gpio-controller;
1634                         #gpio-cells = <2>;
1635
1636                         interrupt-controller;
1637                         #interrupt-cells = <2>;
1638                 };
1639
1640                 gpio6: gpio6@ff7d0000 {
1641                         compatible = "rockchip,gpio-bank";
1642                         reg = <0xff7d0000 0x100>;
1643                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1644                         clocks = <&cru PCLK_GPIO6>;
1645
1646                         gpio-controller;
1647                         #gpio-cells = <2>;
1648
1649                         interrupt-controller;
1650                         #interrupt-cells = <2>;
1651                 };
1652
1653                 gpio7: gpio7@ff7e0000 {
1654                         compatible = "rockchip,gpio-bank";
1655                         reg = <0xff7e0000 0x100>;
1656                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1657                         clocks = <&cru PCLK_GPIO7>;
1658
1659                         gpio-controller;
1660                         #gpio-cells = <2>;
1661
1662                         interrupt-controller;
1663                         #interrupt-cells = <2>;
1664                 };
1665
1666                 gpio8: gpio8@ff7f0000 {
1667                         compatible = "rockchip,gpio-bank";
1668                         reg = <0xff7f0000 0x100>;
1669                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1670                         clocks = <&cru PCLK_GPIO8>;
1671
1672                         gpio-controller;
1673                         #gpio-cells = <2>;
1674
1675                         interrupt-controller;
1676                         #interrupt-cells = <2>;
1677                 };
1678
1679                 hdmi {
1680                         hdmi_ddc: hdmi-ddc {
1681                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1682                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1683                         };
1684                 };
1685
1686                 pcfg_pull_up: pcfg-pull-up {
1687                         bias-pull-up;
1688                 };
1689
1690                 pcfg_pull_down: pcfg-pull-down {
1691                         bias-pull-down;
1692                 };
1693
1694                 pcfg_pull_none: pcfg-pull-none {
1695                         bias-disable;
1696                 };
1697
1698                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1699                         bias-disable;
1700                         drive-strength = <12>;
1701                 };
1702
1703                 sleep {
1704                         global_pwroff: global-pwroff {
1705                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1706                         };
1707
1708                         ddrio_pwroff: ddrio-pwroff {
1709                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1710                         };
1711
1712                         ddr0_retention: ddr0-retention {
1713                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1714                         };
1715
1716                         ddr1_retention: ddr1-retention {
1717                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1718                         };
1719                 };
1720
1721                 edp {
1722                         edp_hpd: edp-hpd {
1723                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1724                         };
1725                 };
1726
1727                 i2c0 {
1728                         i2c0_xfer: i2c0-xfer {
1729                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1730                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1731                         };
1732                 };
1733
1734                 i2c1 {
1735                         i2c1_xfer: i2c1-xfer {
1736                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1737                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1738                         };
1739                 };
1740
1741                 i2c2 {
1742                         i2c2_xfer: i2c2-xfer {
1743                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1744                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1745                         };
1746                 };
1747
1748                 i2c3 {
1749                         i2c3_xfer: i2c3-xfer {
1750                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1751                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1752                         };
1753                 };
1754
1755                 i2c4 {
1756                         i2c4_xfer: i2c4-xfer {
1757                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1758                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1759                         };
1760                 };
1761
1762                 i2c5 {
1763                         i2c5_xfer: i2c5-xfer {
1764                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1765                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1766                         };
1767                 };
1768
1769                 i2s0 {
1770                         i2s0_bus: i2s0-bus {
1771                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1772                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1773                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1774                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1775                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1776                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1777                         };
1778                 };
1779
1780                 lcdc0 {
1781                         lcdc0_ctl: lcdc0-ctl {
1782                                 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1783                                                 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1784                                                 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1785                                                 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1786                         };
1787                 };
1788
1789                 sdmmc {
1790                         sdmmc_clk: sdmmc-clk {
1791                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1792                         };
1793
1794                         sdmmc_cmd: sdmmc-cmd {
1795                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1796                         };
1797
1798                         sdmmc_cd: sdmmc-cd {
1799                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1800                         };
1801
1802                         sdmmc_bus1: sdmmc-bus1 {
1803                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1804                         };
1805
1806                         sdmmc_bus4: sdmmc-bus4 {
1807                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1808                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1809                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1810                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1811                         };
1812                 };
1813
1814                 sdio0 {
1815                         sdio0_bus1: sdio0-bus1 {
1816                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1817                         };
1818
1819                         sdio0_bus4: sdio0-bus4 {
1820                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1821                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1822                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1823                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1824                         };
1825
1826                         sdio0_cmd: sdio0-cmd {
1827                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1828                         };
1829
1830                         sdio0_clk: sdio0-clk {
1831                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1832                         };
1833
1834                         sdio0_cd: sdio0-cd {
1835                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1836                         };
1837
1838                         sdio0_wp: sdio0-wp {
1839                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1840                         };
1841
1842                         sdio0_pwr: sdio0-pwr {
1843                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1844                         };
1845
1846                         sdio0_bkpwr: sdio0-bkpwr {
1847                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1848                         };
1849
1850                         sdio0_int: sdio0-int {
1851                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1852                         };
1853                 };
1854
1855                 sdio1 {
1856                         sdio1_bus1: sdio1-bus1 {
1857                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1858                         };
1859
1860                         sdio1_bus4: sdio1-bus4 {
1861                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1862                                                 <3 25 4 &pcfg_pull_up>,
1863                                                 <3 26 4 &pcfg_pull_up>,
1864                                                 <3 27 4 &pcfg_pull_up>;
1865                         };
1866
1867                         sdio1_cd: sdio1-cd {
1868                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1869                         };
1870
1871                         sdio1_wp: sdio1-wp {
1872                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1873                         };
1874
1875                         sdio1_bkpwr: sdio1-bkpwr {
1876                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1877                         };
1878
1879                         sdio1_int: sdio1-int {
1880                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1881                         };
1882
1883                         sdio1_cmd: sdio1-cmd {
1884                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1885                         };
1886
1887                         sdio1_clk: sdio1-clk {
1888                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1889                         };
1890
1891                         sdio1_pwr: sdio1-pwr {
1892                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1893                         };
1894                 };
1895
1896                 emmc {
1897                         emmc_clk: emmc-clk {
1898                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1899                         };
1900
1901                         emmc_cmd: emmc-cmd {
1902                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1903                         };
1904
1905                         emmc_pwr: emmc-pwr {
1906                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1907                         };
1908
1909                         emmc_bus1: emmc-bus1 {
1910                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1911                         };
1912
1913                         emmc_bus4: emmc-bus4 {
1914                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1915                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1916                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1917                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1918                         };
1919
1920                         emmc_bus8: emmc-bus8 {
1921                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1922                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1923                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1924                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1925                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1926                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1927                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1928                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1929                         };
1930                 };
1931
1932                 spi0 {
1933                         spi0_clk: spi0-clk {
1934                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1935                         };
1936                         spi0_cs0: spi0-cs0 {
1937                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1938                         };
1939                         spi0_tx: spi0-tx {
1940                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1941                         };
1942                         spi0_rx: spi0-rx {
1943                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1944                         };
1945                         spi0_cs1: spi0-cs1 {
1946                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1947                         };
1948                 };
1949                 spi1 {
1950                         spi1_clk: spi1-clk {
1951                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1952                         };
1953                         spi1_cs0: spi1-cs0 {
1954                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1955                         };
1956                         spi1_rx: spi1-rx {
1957                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1958                         };
1959                         spi1_tx: spi1-tx {
1960                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1961                         };
1962                 };
1963
1964                 spi2 {
1965                         spi2_cs1: spi2-cs1 {
1966                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1967                         };
1968                         spi2_clk: spi2-clk {
1969                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1970                         };
1971                         spi2_cs0: spi2-cs0 {
1972                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1973                         };
1974                         spi2_rx: spi2-rx {
1975                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1976                         };
1977                         spi2_tx: spi2-tx {
1978                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1979                         };
1980                 };
1981
1982                 uart0 {
1983                         uart0_xfer: uart0-xfer {
1984                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1985                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1986                         };
1987
1988                         uart0_cts: uart0-cts {
1989                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1990                         };
1991
1992                         uart0_rts: uart0-rts {
1993                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1994                         };
1995                 };
1996
1997                 uart1 {
1998                         uart1_xfer: uart1-xfer {
1999                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
2000                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
2001                         };
2002
2003                         uart1_cts: uart1-cts {
2004                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
2005                         };
2006
2007                         uart1_rts: uart1-rts {
2008                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
2009                         };
2010                 };
2011
2012                 uart2 {
2013                         uart2_xfer: uart2-xfer {
2014                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
2015                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
2016                         };
2017                         /* no rts / cts for uart2 */
2018                 };
2019
2020                 uart3 {
2021                         uart3_xfer: uart3-xfer {
2022                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
2023                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
2024                         };
2025
2026                         uart3_cts: uart3-cts {
2027                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
2028                         };
2029
2030                         uart3_rts: uart3-rts {
2031                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
2032                         };
2033                 };
2034
2035                 uart4 {
2036                         uart4_xfer: uart4-xfer {
2037                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
2038                                                 <5 13 3 &pcfg_pull_none>;
2039                         };
2040
2041                         uart4_cts: uart4-cts {
2042                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
2043                         };
2044
2045                         uart4_rts: uart4-rts {
2046                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
2047                         };
2048                 };
2049
2050                 tsadc {
2051                         otp_gpio: otp-gpio {
2052                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
2053                         };
2054
2055                         otp_out: otp-out {
2056                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
2057                         };
2058                 };
2059
2060                 pwm0 {
2061                         pwm0_pin: pwm0-pin {
2062                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
2063                         };
2064                 };
2065
2066                 pwm1 {
2067                         pwm1_pin: pwm1-pin {
2068                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
2069                         };
2070                 };
2071
2072                 pwm2 {
2073                         pwm2_pin: pwm2-pin {
2074                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
2075                         };
2076                 };
2077
2078                 pwm3 {
2079                         pwm3_pin: pwm3-pin {
2080                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
2081                         };
2082                 };
2083
2084                 gmac {
2085                         rgmii_pins: rgmii-pins {
2086                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
2087                                                 <3 31 3 &pcfg_pull_none>,
2088                                                 <3 26 3 &pcfg_pull_none>,
2089                                                 <3 27 3 &pcfg_pull_none>,
2090                                                 <3 28 3 &pcfg_pull_none_12ma>,
2091                                                 <3 29 3 &pcfg_pull_none_12ma>,
2092                                                 <3 24 3 &pcfg_pull_none_12ma>,
2093                                                 <3 25 3 &pcfg_pull_none_12ma>,
2094                                                 <4 0 3 &pcfg_pull_none>,
2095                                                 <4 5 3 &pcfg_pull_none>,
2096                                                 <4 6 3 &pcfg_pull_none>,
2097                                                 <4 9 3 &pcfg_pull_none_12ma>,
2098                                                 <4 4 3 &pcfg_pull_none_12ma>,
2099                                                 <4 1 3 &pcfg_pull_none>,
2100                                                 <4 3 3 &pcfg_pull_none>;
2101                         };
2102
2103                         rmii_pins: rmii-pins {
2104                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
2105                                                 <3 31 3 &pcfg_pull_none>,
2106                                                 <3 28 3 &pcfg_pull_none>,
2107                                                 <3 29 3 &pcfg_pull_none>,
2108                                                 <4 0 3 &pcfg_pull_none>,
2109                                                 <4 5 3 &pcfg_pull_none>,
2110                                                 <4 4 3 &pcfg_pull_none>,
2111                                                 <4 1 3 &pcfg_pull_none>,
2112                                                 <4 2 3 &pcfg_pull_none>,
2113                                                 <4 3 3 &pcfg_pull_none>;
2114                         };
2115                 };
2116
2117                 spdif {
2118                         spdif_tx: spdif-tx {
2119                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
2120                         };
2121                 };
2122
2123                 cif {
2124                         cif_dvp_d2d9: cif-dvp-d2d9 {
2125                                 rockchip,pins = <2 0 RK_FUNC_1 &pcfg_pull_none>,
2126                                                 <2 1 RK_FUNC_1 &pcfg_pull_none>,
2127                                                 <2 2 RK_FUNC_1 &pcfg_pull_none>,
2128                                                 <2 3 RK_FUNC_1 &pcfg_pull_none>,
2129                                                 <2 4 RK_FUNC_1 &pcfg_pull_none>,
2130                                                 <2 5 RK_FUNC_1 &pcfg_pull_none>,
2131                                                 <2 6 RK_FUNC_1 &pcfg_pull_none>,
2132                                                 <2 7 RK_FUNC_1 &pcfg_pull_none>,
2133                                                 <2 8 RK_FUNC_1 &pcfg_pull_none>,
2134                                                 <2 9 RK_FUNC_1 &pcfg_pull_none>,
2135                                                 <2 11 RK_FUNC_1 &pcfg_pull_none>;
2136                         };
2137                 };
2138
2139                 isp_pin {
2140                         isp_mipi: isp-mipi {
2141                                 rockchip,pins =
2142                                         /* cif_clkout */
2143                                         <2 11 RK_FUNC_1 &pcfg_pull_none>;
2144                         };
2145
2146                         isp_dvp_d2d9: isp-d2d9 {
2147                                 rockchip,pins =
2148                                         /* cif_data2 ... cif_data9 */
2149                                         <2 0 RK_FUNC_1 &pcfg_pull_none>,
2150                                         <2 1 RK_FUNC_1 &pcfg_pull_none>,
2151                                         <2 2 RK_FUNC_1 &pcfg_pull_none>,
2152                                         <2 3 RK_FUNC_1 &pcfg_pull_none>,
2153                                         <2 4 RK_FUNC_1 &pcfg_pull_none>,
2154                                         <2 5 RK_FUNC_1 &pcfg_pull_none>,
2155                                         <2 6 RK_FUNC_1 &pcfg_pull_none>,
2156                                         <2 7 RK_FUNC_1 &pcfg_pull_none>,
2157                                         /* cif_sync, cif_href */
2158                                         <2 8 RK_FUNC_1 &pcfg_pull_none>,
2159                                         <2 9 RK_FUNC_1 &pcfg_pull_none>,
2160                                         /* cif_clkin, cif_clkout */
2161                                         <2 10 RK_FUNC_1 &pcfg_pull_none>,
2162                                         <2 11 RK_FUNC_1 &pcfg_pull_none>;
2163                         };
2164
2165                         isp_dvp_d0d1: isp-d0d1 {
2166                                 rockchip,pins =
2167                                         /* cif_data0, cif_data1 */
2168                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
2169                                         <2 13 RK_FUNC_1 &pcfg_pull_none>;
2170                         };
2171
2172                         isp_dvp_d10d11: isp-d10d11 {
2173                                 rockchip,pins =
2174                                         /* cif_data10, cif_data11 */
2175                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
2176                                         <2 15 RK_FUNC_1 &pcfg_pull_none>;
2177                         };
2178
2179                         isp_dvp_d0d7: isp-d0d7 {
2180                                 rockchip,pins =
2181                                         /* cif_data0 ... cif_data7 */
2182                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
2183                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
2184                                         <2 0 RK_FUNC_1 &pcfg_pull_none>,
2185                                         <2 1 RK_FUNC_1 &pcfg_pull_none>,
2186                                         <2 2 RK_FUNC_1 &pcfg_pull_none>,
2187                                         <2 3 RK_FUNC_1 &pcfg_pull_none>,
2188                                         <2 4 RK_FUNC_1 &pcfg_pull_none>,
2189                                         <2 5 RK_FUNC_1 &pcfg_pull_none>;
2190                         };
2191
2192                         isp_shutter: isp-shutter {
2193                                 rockchip,pins =
2194                                         /* SHUTTEREN, SHUTTERTRIG */
2195                                         <7 12 RK_FUNC_2 &pcfg_pull_none>,
2196                                         <7 15 RK_FUNC_2 &pcfg_pull_none>;
2197                         };
2198
2199                         isp_flash_trigger: isp-flash-trigger {
2200                                 rockchip,pins =
2201                                         /* ISP_FLASHTRIGOU */
2202                                         <7 13 RK_FUNC_2 &pcfg_pull_none>;
2203                         };
2204
2205                         isp_prelight: isp-prelight {
2206                                 rockchip,pins =
2207                                         /* ISP_PRELIGHTTRIG */
2208                                         <7 14 RK_FUNC_2 &pcfg_pull_none>;
2209                         };
2210
2211                         isp_flash_trigger_as_gpio: isp-flash-trigger-as-gpio {
2212                                 rockchip,pins =
2213                                         /* ISP_FLASHTRIGOU */
2214                                         <7 13 RK_FUNC_2 &pcfg_pull_none>;
2215                         };
2216                 };
2217
2218         };
2219 };