arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49 #include <dt-bindings/display/drm_mipi_dsi.h>
  50 #include "skeleton.dtsi"
  51
  52 / {
  53         compatible = "rockchip,rk3288";
  54
  55         interrupt-parent = <&gic>;
  56
  57         aliases {
  58                 ethernet0 = &gmac;
  59                 i2c0 = &i2c0;
  60                 i2c1 = &i2c1;
  61                 i2c2 = &i2c2;
  62                 i2c3 = &i2c3;
  63                 i2c4 = &i2c4;
  64                 i2c5 = &i2c5;
  65                 mshc0 = &emmc;
  66                 mshc1 = &sdmmc;
  67                 mshc2 = &sdio0;
  68                 mshc3 = &sdio1;
  69                 serial0 = &uart0;
  70                 serial1 = &uart1;
  71                 serial2 = &uart2;
  72                 serial3 = &uart3;
  73                 serial4 = &uart4;
  74                 spi0 = &spi0;
  75                 spi1 = &spi1;
  76                 spi2 = &spi2;
  77         };
  78
  79         arm-pmu {
  80                 compatible = "arm,cortex-a12-pmu";
  81                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  82                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  83                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  84                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  85                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  86         };
  87
  88         cpus {
  89                 #address-cells = <1>;
  90                 #size-cells = <0>;
  91                 enable-method = "rockchip,rk3066-smp";
  92                 rockchip,pmu = <&pmu>;
  93
  94                 cpu0: cpu@500 {
  95                         device_type = "cpu";
  96                         compatible = "arm,cortex-a12";
  97                         reg = <0x500>;
  98                         resets = <&cru SRST_CORE0>;
  99                         operating-points-v2 = <&cpu0_opp_table>;
 100                         #cooling-cells = <2>; /* min followed by max */
 101                         dynamic-power-coefficient = <322>;
 102                         clocks = <&cru ARMCLK>;
 103                 };
 104                 cpu1: cpu@501 {
 105                         device_type = "cpu";
 106                         compatible = "arm,cortex-a12";
 107                         reg = <0x501>;
 108                         resets = <&cru SRST_CORE1>;
 109                         operating-points-v2 = <&cpu0_opp_table>;
 110                 };
 111                 cpu2: cpu@502 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a12";
 114                         reg = <0x502>;
 115                         resets = <&cru SRST_CORE2>;
 116                         operating-points-v2 = <&cpu0_opp_table>;
 117                 };
 118                 cpu3: cpu@503 {
 119                         device_type = "cpu";
 120                         compatible = "arm,cortex-a12";
 121                         reg = <0x503>;
 122                         resets = <&cru SRST_CORE3>;
 123                         operating-points-v2 = <&cpu0_opp_table>;
 124                 };
 125         };
 126
 127         cpu0_opp_table: opp_table0 {
 128                 compatible = "operating-points-v2";
 129                 opp-shared;
 130
 131                 opp-126000000 {
 132                         opp-hz = /bits/ 64 <126000000>;
 133                         opp-microvolt = <900000>;
 134                         clock-latency-ns = <40000>;
 135                 };
 136                 opp-216000000 {
 137                         opp-hz = /bits/ 64 <216000000>;
 138                         opp-microvolt = <900000>;
 139                         clock-latency-ns = <40000>;
 140                 };
 141                 opp-408000000 {
 142                         opp-hz = /bits/ 64 <408000000>;
 143                         opp-microvolt = <900000>;
 144                         clock-latency-ns = <40000>;
 145                 };
 146                 opp-600000000 {
 147                         opp-hz = /bits/ 64 <600000000>;
 148                         opp-microvolt = <900000>;
 149                         clock-latency-ns = <40000>;
 150                 };
 151                 opp-696000000 {
 152                         opp-hz = /bits/ 64 <696000000>;
 153                         opp-microvolt = <950000>;
 154                         clock-latency-ns = <40000>;
 155                 };
 156                 opp-816000000 {
 157                         opp-hz = /bits/ 64 <816000000>;
 158                         opp-microvolt = <1000000>;
 159                         clock-latency-ns = <40000>;
 160                         opp-suspend;
 161                 };
 162                 opp-1008000000 {
 163                         opp-hz = /bits/ 64 <1008000000>;
 164                         opp-microvolt = <1050000>;
 165                         clock-latency-ns = <40000>;
 166                 };
 167                 opp-1200000000 {
 168                         opp-hz = /bits/ 64 <1200000000>;
 169                         opp-microvolt = <1100000>;
 170                         clock-latency-ns = <40000>;
 171                 };
 172                 opp-1416000000 {
 173                         opp-hz = /bits/ 64 <1416000000>;
 174                         opp-microvolt = <1200000>;
 175                         clock-latency-ns = <40000>;
 176                 };
 177                 opp-1512000000 {
 178                         opp-hz = /bits/ 64 <1512000000>;
 179                         opp-microvolt = <1300000>;
 180                         clock-latency-ns = <40000>;
 181                 };
 182                 opp-1608000000 {
 183                         opp-hz = /bits/ 64 <1608000000>;
 184                         opp-microvolt = <1350000>;
 185                         clock-latency-ns = <40000>;
 186                 };
 187         };
 188
 189         amba {
 190                 compatible = "arm,amba-bus";
 191                 #address-cells = <1>;
 192                 #size-cells = <1>;
 193                 ranges;
 194
 195                 dmac_peri: dma-controller@ff250000 {
 196                         compatible = "arm,pl330", "arm,primecell";
 197                         reg = <0xff250000 0x4000>;
 198                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 199                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 200                         #dma-cells = <1>;
 201                         arm,pl330-broken-no-flushp;
 202                         peripherals-req-type-burst;
 203                         clocks = <&cru ACLK_DMAC2>;
 204                         clock-names = "apb_pclk";
 205                 };
 206
 207                 dmac_bus_ns: dma-controller@ff600000 {
 208                         compatible = "arm,pl330", "arm,primecell";
 209                         reg = <0xff600000 0x4000>;
 210                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 211                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 212                         #dma-cells = <1>;
 213                         arm,pl330-broken-no-flushp;
 214                         peripherals-req-type-burst;
 215                         clocks = <&cru ACLK_DMAC1>;
 216                         clock-names = "apb_pclk";
 217                         status = "disabled";
 218                 };
 219
 220                 dmac_bus_s: dma-controller@ffb20000 {
 221                         compatible = "arm,pl330", "arm,primecell";
 222                         reg = <0xffb20000 0x4000>;
 223                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 224                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 225                         #dma-cells = <1>;
 226                         arm,pl330-broken-no-flushp;
 227                         peripherals-req-type-burst;
 228                         clocks = <&cru ACLK_DMAC1>;
 229                         clock-names = "apb_pclk";
 230                 };
 231         };
 232
 233         reserved-memory {
 234                 #address-cells = <1>;
 235                 #size-cells = <1>;
 236                 ranges;
 237
 238                 /*
 239                  * The rk3288 cannot use the memory area above 0xfe000000
 240                  * for dma operations for some reason. While there is
 241                  * probably a better solution available somewhere, we
 242                  * haven't found it yet and while devices with 2GB of ram
 243                  * are not affected, this issue prevents 4GB from booting.
 244                  * So to make these devices at least bootable, block
 245                  * this area for the time being until the real solution
 246                  * is found.
 247                  */
 248                 dma-unusable@fe000000 {
 249                         reg = <0xfe000000 0x1000000>;
 250                 };
 251         };
 252
 253         xin24m: oscillator {
 254                 compatible = "fixed-clock";
 255                 clock-frequency = <24000000>;
 256                 clock-output-names = "xin24m";
 257                 #clock-cells = <0>;
 258         };
 259
 260         timer {
 261                 compatible = "arm,armv7-timer";
 262                 arm,cpu-registers-not-fw-configured;
 263                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 264                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 265                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 266                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 267                 clock-frequency = <24000000>;
 268         };
 269
 270         timer: timer@ff810000 {
 271                 compatible = "rockchip,rk3288-timer";
 272                 reg = <0xff810000 0x20>;
 273                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 274                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 275                 clock-names = "timer", "pclk";
 276         };
 277
 278         display-subsystem {
 279                 compatible = "rockchip,display-subsystem";
 280                 ports = <&vopl_out>, <&vopb_out>;
 281         };
 282
 283         sdmmc: dwmmc@ff0c0000 {
 284                 compatible = "rockchip,rk3288-dw-mshc";
 285                 clock-freq-min-max = <400000 150000000>;
 286                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 287                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 288                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 289                 fifo-depth = <0x100>;
 290                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 291                 reg = <0xff0c0000 0x4000>;
 292                 status = "disabled";
 293         };
 294
 295         sdio0: dwmmc@ff0d0000 {
 296                 compatible = "rockchip,rk3288-dw-mshc";
 297                 clock-freq-min-max = <400000 150000000>;
 298                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 299                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 300                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 301                 fifo-depth = <0x100>;
 302                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 303                 reg = <0xff0d0000 0x4000>;
 304                 status = "disabled";
 305         };
 306
 307         sdio1: dwmmc@ff0e0000 {
 308                 compatible = "rockchip,rk3288-dw-mshc";
 309                 clock-freq-min-max = <400000 150000000>;
 310                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 311                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 312                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 313                 fifo-depth = <0x100>;
 314                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 315                 reg = <0xff0e0000 0x4000>;
 316                 status = "disabled";
 317         };
 318
 319         emmc: dwmmc@ff0f0000 {
 320                 compatible = "rockchip,rk3288-dw-mshc";
 321                 clock-freq-min-max = <400000 150000000>;
 322                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 323                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 324                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 325                 fifo-depth = <0x100>;
 326                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 327                 reg = <0xff0f0000 0x4000>;
 328                 status = "disabled";
 329                 supports-emmc;
 330         };
 331
 332         saradc: saradc@ff100000 {
 333                 compatible = "rockchip,saradc";
 334                 reg = <0xff100000 0x100>;
 335                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 336                 #io-channel-cells = <1>;
 337                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 338                 clock-names = "saradc", "apb_pclk";
 339                 resets = <&cru SRST_SARADC>;
 340                 reset-names = "saradc-apb";
 341                 status = "disabled";
 342         };
 343
 344         spi0: spi@ff110000 {
 345                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 346                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 347                 clock-names = "spiclk", "apb_pclk";
 348                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 349                 dma-names = "tx", "rx";
 350                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 351                 pinctrl-names = "default";
 352                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 353                 reg = <0xff110000 0x1000>;
 354                 #address-cells = <1>;
 355                 #size-cells = <0>;
 356                 status = "disabled";
 357         };
 358
 359         spi1: spi@ff120000 {
 360                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 361                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 362                 clock-names = "spiclk", "apb_pclk";
 363                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 364                 dma-names = "tx", "rx";
 365                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 366                 pinctrl-names = "default";
 367                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 368                 reg = <0xff120000 0x1000>;
 369                 #address-cells = <1>;
 370                 #size-cells = <0>;
 371                 status = "disabled";
 372         };
 373
 374         spi2: spi@ff130000 {
 375                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 376                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 377                 clock-names = "spiclk", "apb_pclk";
 378                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 379                 dma-names = "tx", "rx";
 380                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 381                 pinctrl-names = "default";
 382                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 383                 reg = <0xff130000 0x1000>;
 384                 #address-cells = <1>;
 385                 #size-cells = <0>;
 386                 status = "disabled";
 387         };
 388
 389         i2c0: i2c@ff650000 {
 390                 compatible = "rockchip,rk3288-i2c";
 391                 reg = <0xff650000 0x1000>;
 392                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 393                 #address-cells = <1>;
 394                 #size-cells = <0>;
 395                 clock-names = "i2c";
 396                 clocks = <&cru PCLK_I2C0>;
 397                 pinctrl-names = "default";
 398                 pinctrl-0 = <&i2c0_xfer>;
 399                 status = "disabled";
 400         };
 401
 402         i2c1: i2c@ff140000 {
 403                 compatible = "rockchip,rk3288-i2c";
 404                 reg = <0xff140000 0x1000>;
 405                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 406                 #address-cells = <1>;
 407                 #size-cells = <0>;
 408                 clock-names = "i2c";
 409                 clocks = <&cru PCLK_I2C1>;
 410                 pinctrl-names = "default";
 411                 pinctrl-0 = <&i2c1_xfer>;
 412                 status = "disabled";
 413         };
 414
 415         i2c3: i2c@ff150000 {
 416                 compatible = "rockchip,rk3288-i2c";
 417                 reg = <0xff150000 0x1000>;
 418                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 419                 #address-cells = <1>;
 420                 #size-cells = <0>;
 421                 clock-names = "i2c";
 422                 clocks = <&cru PCLK_I2C3>;
 423                 pinctrl-names = "default";
 424                 pinctrl-0 = <&i2c3_xfer>;
 425                 status = "disabled";
 426         };
 427
 428         i2c4: i2c@ff160000 {
 429                 compatible = "rockchip,rk3288-i2c";
 430                 reg = <0xff160000 0x1000>;
 431                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 432                 #address-cells = <1>;
 433                 #size-cells = <0>;
 434                 clock-names = "i2c";
 435                 clocks = <&cru PCLK_I2C4>;
 436                 pinctrl-names = "default";
 437                 pinctrl-0 = <&i2c4_xfer>;
 438                 status = "disabled";
 439         };
 440
 441         i2c5: i2c@ff170000 {
 442                 compatible = "rockchip,rk3288-i2c";
 443                 reg = <0xff170000 0x1000>;
 444                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 445                 #address-cells = <1>;
 446                 #size-cells = <0>;
 447                 clock-names = "i2c";
 448                 clocks = <&cru PCLK_I2C5>;
 449                 pinctrl-names = "default";
 450                 pinctrl-0 = <&i2c5_xfer>;
 451                 status = "disabled";
 452         };
 453
 454         uart0: serial@ff180000 {
 455                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 456                 reg = <0xff180000 0x100>;
 457                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 458                 reg-shift = <2>;
 459                 reg-io-width = <4>;
 460                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 461                 clock-names = "baudclk", "apb_pclk";
 462                 pinctrl-names = "default";
 463                 pinctrl-0 = <&uart0_xfer>;
 464                 status = "disabled";
 465         };
 466
 467         uart1: serial@ff190000 {
 468                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 469                 reg = <0xff190000 0x100>;
 470                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 471                 reg-shift = <2>;
 472                 reg-io-width = <4>;
 473                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 474                 clock-names = "baudclk", "apb_pclk";
 475                 pinctrl-names = "default";
 476                 pinctrl-0 = <&uart1_xfer>;
 477                 status = "disabled";
 478         };
 479
 480         uart2: serial@ff690000 {
 481                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 482                 reg = <0xff690000 0x100>;
 483                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 484                 reg-shift = <2>;
 485                 reg-io-width = <4>;
 486                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 487                 clock-names = "baudclk", "apb_pclk";
 488                 pinctrl-names = "default";
 489                 pinctrl-0 = <&uart2_xfer>;
 490                 status = "disabled";
 491         };
 492
 493         uart3: serial@ff1b0000 {
 494                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 495                 reg = <0xff1b0000 0x100>;
 496                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 497                 reg-shift = <2>;
 498                 reg-io-width = <4>;
 499                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 500                 clock-names = "baudclk", "apb_pclk";
 501                 pinctrl-names = "default";
 502                 pinctrl-0 = <&uart3_xfer>;
 503                 status = "disabled";
 504         };
 505
 506         uart4: serial@ff1c0000 {
 507                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 508                 reg = <0xff1c0000 0x100>;
 509                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 510                 reg-shift = <2>;
 511                 reg-io-width = <4>;
 512                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 513                 clock-names = "baudclk", "apb_pclk";
 514                 pinctrl-names = "default";
 515                 pinctrl-0 = <&uart4_xfer>;
 516                 status = "disabled";
 517         };
 518
 519         thermal_zones: thermal-zones {
 520                 soc_thermal: soc-thermal {
 521                         polling-delay-passive = <200>; /* milliseconds */
 522                         polling-delay = <1000>; /* milliseconds */
 523                         sustainable-power = <1200>; /* milliwatts */
 524
 525                         thermal-sensors = <&tsadc 1>;
 526                         trips {
 527                                 threshold: trip-point@0 {
 528                                         temperature = <75000>; /* millicelsius */
 529                                         hysteresis = <2000>; /* millicelsius */
 530                                         type = "passive";
 531                                 };
 532                                 target: trip-point@1 {
 533                                         temperature = <85000>; /* millicelsius */
 534                                         hysteresis = <2000>; /* millicelsius */
 535                                         type = "passive";
 536                                 };
 537                                 soc_crit: soc-crit {
 538                                         temperature = <90000>; /* millicelsius */
 539                                         hysteresis = <2000>; /* millicelsius */
 540                                         type = "critical";
 541                                 };
 542                         };
 543
 544                         cooling-maps {
 545                                 map0 {
 546                                         trip = <&target>;
 547                                         cooling-device =
 548                                         <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 549                                         contribution = <1024>;
 550                                 };
 551                                 map1 {
 552                                         trip = <&target>;
 553                                         cooling-device =
 554                                         <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 555                                         contribution = <1024>;
 556                                 };
 557                         };
 558                 };
 559
 560                 gpu_thermal: gpu-thermal {
 561                         polling-delay-passive = <200>; /* milliseconds */
 562                         polling-delay = <1000>; /* milliseconds */
 563                         thermal-sensors = <&tsadc 2>;
 564                 };
 565         };
 566
 567         tsadc: tsadc@ff280000 {
 568                 compatible = "rockchip,rk3288-tsadc";
 569                 reg = <0xff280000 0x100>;
 570                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 571                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 572                 clock-names = "tsadc", "apb_pclk";
 573                 assigned-clocks = <&cru SCLK_TSADC>;
 574                 assigned-clock-rates = <10000>;
 575                 resets = <&cru SRST_TSADC>;
 576                 reset-names = "tsadc-apb";
 577                 pinctrl-names = "init", "default", "sleep";
 578                 pinctrl-0 = <&otp_gpio>;
 579                 pinctrl-1 = <&otp_out>;
 580                 pinctrl-2 = <&otp_gpio>;
 581                 #thermal-sensor-cells = <1>;
 582                 rockchip,hw-tshut-temp = <95000>;
 583                 status = "disabled";
 584         };
 585
 586         gmac: ethernet@ff290000 {
 587                 compatible = "rockchip,rk3288-gmac";
 588                 reg = <0xff290000 0x10000>;
 589                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 590                                 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 591                 interrupt-names = "macirq", "eth_wake_irq";
 592                 rockchip,grf = <&grf>;
 593                 clocks = <&cru SCLK_MAC>,
 594                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 595                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 596                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 597                 clock-names = "stmmaceth",
 598                         "mac_clk_rx", "mac_clk_tx",
 599                         "clk_mac_ref", "clk_mac_refout",
 600                         "aclk_mac", "pclk_mac";
 601                 resets = <&cru SRST_MAC>;
 602                 reset-names = "stmmaceth";
 603                 status = "disabled";
 604         };
 605
 606         usb_host0_ehci: usb@ff500000 {
 607                 compatible = "generic-ehci";
 608                 reg = <0xff500000 0x100>;
 609                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 610                 clocks = <&cru HCLK_USBHOST0>;
 611                 clock-names = "usbhost";
 612                 phys = <&usbphy1>;
 613                 phy-names = "usb";
 614                 status = "disabled";
 615         };
 616
 617         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 618
 619         usb_host1: usb@ff540000 {
 620                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 621                                 "snps,dwc2";
 622                 reg = <0xff540000 0x40000>;
 623                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 624                 clocks = <&cru HCLK_USBHOST1>;
 625                 clock-names = "otg";
 626                 dr_mode = "host";
 627                 phys = <&usbphy2>;
 628                 phy-names = "usb2-phy";
 629                 status = "disabled";
 630         };
 631
 632         usb_otg: usb@ff580000 {
 633                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 634                                 "snps,dwc2";
 635                 reg = <0xff580000 0x40000>;
 636                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 637                 clocks = <&cru HCLK_OTG0>;
 638                 clock-names = "otg";
 639                 dr_mode = "otg";
 640                 g-np-tx-fifo-size = <16>;
 641                 g-rx-fifo-size = <275>;
 642                 g-tx-fifo-size = <256 128 128 64 64 32>;
 643                 g-use-dma;
 644                 phys = <&usbphy0>;
 645                 phy-names = "usb2-phy";
 646                 status = "disabled";
 647         };
 648
 649         usb_hsic: usb@ff5c0000 {
 650                 compatible = "generic-ehci";
 651                 reg = <0xff5c0000 0x100>;
 652                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 653                 clocks = <&cru HCLK_HSIC>;
 654                 clock-names = "usbhost";
 655                 status = "disabled";
 656         };
 657
 658         dmc: dmc@ff610000 {
 659                 compatible = "rockchip,rk3288-dmc", "syscon";
 660                 rockchip,cru = <&cru>;
 661                 rockchip,grf = <&grf>;
 662                 rockchip,pmu = <&pmu>;
 663                 rockchip,sgrf = <&sgrf>;
 664                 rockchip,noc = <&noc>;
 665                 reg = <0xff610000 0x3fc
 666                        0xff620000 0x294
 667                        0xff630000 0x3fc
 668                        0xff640000 0x294>;
 669                 rockchip,sram = <&ddr_sram>;
 670                 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
 671                          <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
 672                          <&cru ARMCLK>, <&cru ACLK_DMAC1>;
 673                 clock-names = "pclk_ddrupctl0", "pclk_publ0",
 674                               "pclk_ddrupctl1", "pclk_publ1",
 675                               "arm_clk", "aclk_dmac1";
 676         };
 677
 678         i2c2: i2c@ff660000 {
 679                 compatible = "rockchip,rk3288-i2c";
 680                 reg = <0xff660000 0x1000>;
 681                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 682                 #address-cells = <1>;
 683                 #size-cells = <0>;
 684                 clock-names = "i2c";
 685                 clocks = <&cru PCLK_I2C2>;
 686                 pinctrl-names = "default";
 687                 pinctrl-0 = <&i2c2_xfer>;
 688                 status = "disabled";
 689         };
 690
 691         pwm0: pwm@ff680000 {
 692                 compatible = "rockchip,rk3288-pwm";
 693                 reg = <0xff680000 0x10>;
 694                 #pwm-cells = <3>;
 695                 pinctrl-names = "default";
 696                 pinctrl-0 = <&pwm0_pin>;
 697                 clocks = <&cru PCLK_PWM>;
 698                 clock-names = "pwm";
 699                 status = "disabled";
 700         };
 701
 702         pwm1: pwm@ff680010 {
 703                 compatible = "rockchip,rk3288-pwm";
 704                 reg = <0xff680010 0x10>;
 705                 #pwm-cells = <3>;
 706                 pinctrl-names = "default";
 707                 pinctrl-0 = <&pwm1_pin>;
 708                 clocks = <&cru PCLK_PWM>;
 709                 clock-names = "pwm";
 710                 status = "disabled";
 711         };
 712
 713         pwm2: pwm@ff680020 {
 714                 compatible = "rockchip,rk3288-pwm";
 715                 reg = <0xff680020 0x10>;
 716                 #pwm-cells = <3>;
 717                 pinctrl-names = "default";
 718                 pinctrl-0 = <&pwm2_pin>;
 719                 clocks = <&cru PCLK_PWM>;
 720                 clock-names = "pwm";
 721                 status = "disabled";
 722         };
 723
 724         pwm3: pwm@ff680030 {
 725                 compatible = "rockchip,rk3288-pwm";
 726                 reg = <0xff680030 0x10>;
 727                 #pwm-cells = <2>;
 728                 pinctrl-names = "default";
 729                 pinctrl-0 = <&pwm3_pin>;
 730                 clocks = <&cru PCLK_PWM>;
 731                 clock-names = "pwm";
 732                 status = "disabled";
 733         };
 734
 735         bus_intmem@ff700000 {
 736                 compatible = "mmio-sram";
 737                 reg = <0xff700000 0x18000>;
 738                 #address-cells = <1>;
 739                 #size-cells = <1>;
 740                 ranges = <0 0xff700000 0x18000>;
 741                 smp-sram@0 {
 742                         compatible = "rockchip,rk3066-smp-sram";
 743                         reg = <0x00 0x10>;
 744                 };
 745                 ddr_sram: ddr-sram@1000 {
 746                         compatible = "rockchip,rk3288-ddr-sram";
 747                         reg = <0x1000 0x4000>;
 748                 };
 749         };
 750
 751         sram@ff720000 {
 752                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 753                 reg = <0xff720000 0x1000>;
 754         };
 755
 756         qos_gpu_r: qos@ffaa0000 {
 757                 compatible = "syscon";
 758                 reg = <0xffaa0000 0x20>;
 759         };
 760
 761         qos_gpu_w: qos@ffaa0080 {
 762                 compatible = "syscon";
 763                 reg = <0xffaa0080 0x20>;
 764         };
 765
 766         qos_vio1_vop: qos@ffad0000 {
 767                 compatible = "syscon";
 768                 reg = <0xffad0000 0x20>;
 769         };
 770
 771         qos_vio1_isp_w0: qos@ffad0100 {
 772                 compatible = "syscon";
 773                 reg = <0xffad0100 0x20>;
 774         };
 775
 776         qos_vio1_isp_w1: qos@ffad0180 {
 777                 compatible = "syscon";
 778                 reg = <0xffad0180 0x20>;
 779         };
 780
 781         qos_vio0_vop: qos@ffad0400 {
 782                 compatible = "syscon";
 783                 reg = <0xffad0400 0x20>;
 784         };
 785
 786         qos_vio0_vip: qos@ffad0480 {
 787                 compatible = "syscon";
 788                 reg = <0xffad0480 0x20>;
 789         };
 790
 791         qos_vio0_iep: qos@ffad0500 {
 792                 compatible = "syscon";
 793                 reg = <0xffad0500 0x20>;
 794         };
 795
 796         qos_vio2_rga_r: qos@ffad0800 {
 797                 compatible = "syscon";
 798                 reg = <0xffad0800 0x20>;
 799         };
 800
 801         qos_vio2_rga_w: qos@ffad0880 {
 802                 compatible = "syscon";
 803                 reg = <0xffad0880 0x20>;
 804         };
 805
 806         qos_vio1_isp_r: qos@ffad0900 {
 807                 compatible = "syscon";
 808                 reg = <0xffad0900 0x20>;
 809         };
 810
 811         qos_video: qos@ffae0000 {
 812                 compatible = "syscon";
 813                 reg = <0xffae0000 0x20>;
 814         };
 815
 816         qos_hevc_r: qos@ffaf0000 {
 817                 compatible = "syscon";
 818                 reg = <0xffaf0000 0x20>;
 819         };
 820
 821         qos_hevc_w: qos@ffaf0080 {
 822                 compatible = "syscon";
 823                 reg = <0xffaf0080 0x20>;
 824         };
 825
 826         pmu: power-management@ff730000 {
 827                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 828                 reg = <0xff730000 0x100>;
 829
 830                 power: power-controller {
 831                         compatible = "rockchip,rk3288-power-controller";
 832                         #power-domain-cells = <1>;
 833                         #address-cells = <1>;
 834                         #size-cells = <0>;
 835
 836                         /*
 837                          * Note: Although SCLK_* are the working clocks
 838                          * of device without including on the NOC, needed for
 839                          * synchronous reset.
 840                          *
 841                          * The clocks on the which NOC:
 842                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 843                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 844                          * ACLK_RGA is on ACLK_RGA_NIU.
 845                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 846                          *
 847                          * Which clock are device clocks:
 848                          *      clocks          devices
 849                          *      *_IEP           IEP:Image Enhancement Processor
 850                          *      *_ISP           ISP:Image Signal Processing
 851                          *      *_VIP           VIP:Video Input Processor
 852                          *      *_VOP*          VOP:Visual Output Processor
 853                          *      *_RGA           RGA
 854                          *      *_EDP*          EDP
 855                          *      *_LVDS_*        LVDS
 856                          *      *_HDMI          HDMI
 857                          *      *_MIPI_*        MIPI
 858                          */
 859                         pd_vio@RK3288_PD_VIO {
 860                                 reg = <RK3288_PD_VIO>;
 861                                 clocks = <&cru ACLK_IEP>,
 862                                          <&cru ACLK_ISP>,
 863                                          <&cru ACLK_RGA>,
 864                                          <&cru ACLK_VIP>,
 865                                          <&cru ACLK_VOP0>,
 866                                          <&cru ACLK_VOP1>,
 867                                          <&cru DCLK_VOP0>,
 868                                          <&cru DCLK_VOP1>,
 869                                          <&cru HCLK_IEP>,
 870                                          <&cru HCLK_ISP>,
 871                                          <&cru HCLK_RGA>,
 872                                          <&cru HCLK_VIP>,
 873                                          <&cru HCLK_VOP0>,
 874                                          <&cru HCLK_VOP1>,
 875                                          <&cru PCLK_EDP_CTRL>,
 876                                          <&cru PCLK_HDMI_CTRL>,
 877                                          <&cru PCLK_LVDS_PHY>,
 878                                          <&cru PCLK_MIPI_CSI>,
 879                                          <&cru PCLK_MIPI_DSI0>,
 880                                          <&cru PCLK_MIPI_DSI1>,
 881                                          <&cru SCLK_EDP_24M>,
 882                                          <&cru SCLK_EDP>,
 883                                          <&cru SCLK_ISP_JPE>,
 884                                          <&cru SCLK_ISP>,
 885                                          <&cru SCLK_RGA>;
 886                                 pm_qos = <&qos_vio0_iep>,
 887                                          <&qos_vio1_vop>,
 888                                          <&qos_vio1_isp_w0>,
 889                                          <&qos_vio1_isp_w1>,
 890                                          <&qos_vio0_vop>,
 891                                          <&qos_vio0_vip>,
 892                                          <&qos_vio2_rga_r>,
 893                                          <&qos_vio2_rga_w>,
 894                                          <&qos_vio1_isp_r>;
 895                         };
 896
 897                         /*
 898                          * Note: The following 3 are HEVC(H.265) clocks,
 899                          * and on the ACLK_HEVC_NIU (NOC).
 900                          */
 901                         pd_hevc@RK3288_PD_HEVC {
 902                                 reg = <RK3288_PD_HEVC>;
 903                                 clocks = <&cru ACLK_HEVC>,
 904                                          <&cru SCLK_HEVC_CABAC>,
 905                                          <&cru SCLK_HEVC_CORE>;
 906                                 pm_qos = <&qos_hevc_r>,
 907                                          <&qos_hevc_w>;
 908                         };
 909
 910                         /*
 911                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 912                          * (video endecoder & decoder) clocks that on the
 913                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 914                          */
 915                         pd_video@RK3288_PD_VIDEO {
 916                                 reg = <RK3288_PD_VIDEO>;
 917                                 clocks = <&cru ACLK_VCODEC>,
 918                                          <&cru HCLK_VCODEC>;
 919                                 pm_qos = <&qos_video>;
 920                         };
 921
 922                         /*
 923                          * Note: ACLK_GPU is the GPU clock,
 924                          * and on the ACLK_GPU_NIU (NOC).
 925                          */
 926                         pd_gpu@RK3288_PD_GPU {
 927                                 reg = <RK3288_PD_GPU>;
 928                                 clocks = <&cru ACLK_GPU>;
 929                                 pm_qos = <&qos_gpu_r>,
 930                                          <&qos_gpu_w>;
 931                         };
 932                 };
 933
 934                 reboot-mode {
 935                         compatible = "syscon-reboot-mode";
 936                         offset = <0x94>;
 937                         mode-normal = <BOOT_NORMAL>;
 938                         mode-recovery = <BOOT_RECOVERY>;
 939                         mode-bootloader = <BOOT_FASTBOOT>;
 940                         mode-loader = <BOOT_BL_DOWNLOAD>;
 941                         mode-ums = <BOOT_UMS>;
 942                 };
 943         };
 944
 945         sgrf: syscon@ff740000 {
 946                 compatible = "rockchip,rk3288-sgrf", "syscon";
 947                 reg = <0xff740000 0x1000>;
 948         };
 949
 950         cru: clock-controller@ff760000 {
 951                 compatible = "rockchip,rk3288-cru";
 952                 reg = <0xff760000 0x1000>;
 953                 rockchip,grf = <&grf>;
 954                 #clock-cells = <1>;
 955                 #reset-cells = <1>;
 956                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 957                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 958                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 959                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 960                                   <&cru PCLK_PERI>;
 961                 assigned-clock-rates = <594000000>, <400000000>,
 962                                        <500000000>, <300000000>,
 963                                        <150000000>, <75000000>,
 964                                        <300000000>, <150000000>,
 965                                        <75000000>;
 966                 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
 967         };
 968
 969         grf: syscon@ff770000 {
 970                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 971                 reg = <0xff770000 0x1000>;
 972
 973                 edp_phy: edp-phy {
 974                         compatible = "rockchip,rk3288-dp-phy";
 975                         clocks = <&cru SCLK_EDP_24M>;
 976                         clock-names = "24m";
 977                         #phy-cells = <0>;
 978                         status = "disabled";
 979                 };
 980
 981                 io_domains: io-domains {
 982                         compatible = "rockchip,rk3288-io-voltage-domain";
 983                         status = "disabled";
 984                 };
 985
 986                 usbphy: usbphy {
 987                         compatible = "rockchip,rk3288-usb-phy";
 988                         #address-cells = <1>;
 989                         #size-cells = <0>;
 990                         status = "disabled";
 991
 992                         usbphy0: usb-phy@320 {
 993                                 #phy-cells = <0>;
 994                                 reg = <0x320>;
 995                                 clocks = <&cru SCLK_OTGPHY0>;
 996                                 clock-names = "phyclk";
 997                                 #clock-cells = <0>;
 998                                 resets = <&cru SRST_USBOTG_PHY>;
 999                                 reset-names = "phy-reset";
1000                         };
1001
1002                         usbphy1: usb-phy@334 {
1003                                 #phy-cells = <0>;
1004                                 reg = <0x334>;
1005                                 clocks = <&cru SCLK_OTGPHY1>;
1006                                 clock-names = "phyclk";
1007                                 #clock-cells = <0>;
1008                         };
1009
1010                         usbphy2: usb-phy@348 {
1011                                 #phy-cells = <0>;
1012                                 reg = <0x348>;
1013                                 clocks = <&cru SCLK_OTGPHY2>;
1014                                 clock-names = "phyclk";
1015                                 #clock-cells = <0>;
1016                                 resets = <&cru SRST_USBHOST1_PHY>;
1017                                 reset-names = "phy-reset";
1018                         };
1019                 };
1020         };
1021
1022         wdt: watchdog@ff800000 {
1023                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
1024                 reg = <0xff800000 0x100>;
1025                 clocks = <&cru PCLK_WDT>;
1026                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1027                 status = "disabled";
1028         };
1029
1030         spdif: sound@ff8b0000 {
1031                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
1032                 reg = <0xff8b0000 0x10000>;
1033                 #sound-dai-cells = <0>;
1034                 clock-names = "hclk", "mclk";
1035                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
1036                 dmas = <&dmac_bus_s 3>;
1037                 dma-names = "tx";
1038                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1039                 pinctrl-names = "default";
1040                 pinctrl-0 = <&spdif_tx>;
1041                 rockchip,grf = <&grf>;
1042                 status = "disabled";
1043         };
1044
1045         i2s: i2s@ff890000 {
1046                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
1047                 reg = <0xff890000 0x10000>;
1048                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1049                 #address-cells = <1>;
1050                 #size-cells = <0>;
1051                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
1052                 dma-names = "tx", "rx";
1053                 clock-names = "i2s_hclk", "i2s_clk";
1054                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
1055                 pinctrl-names = "default";
1056                 pinctrl-0 = <&i2s0_bus>;
1057                 rockchip,playback-channels = <8>;
1058                 rockchip,capture-channels = <2>;
1059                 status = "disabled";
1060         };
1061
1062         cif_isp0: cif_isp@ff910000 {
1063                 compatible = "rockchip,rk3288-cif-isp";
1064                 rockchip,grf = <&grf>;
1065                 reg = <0xff910000 0x10000>, <0xff968000 0x4000>;
1066                 reg-names = "register", "csihost-register";
1067                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1068                         <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
1069                         <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
1070                         <&cru SCLK_MIPIDSI_24M>;
1071                 clock-names = "aclk_isp", "hclk_isp",
1072                         "sclk_isp", "sclk_isp_jpe",
1073                         "pclk_mipi_csi", "pclk_isp_in",
1074                         "sclk_mipidsi_24m";
1075                 resets = <&cru SRST_ISP>;
1076                 reset-names = "rst_isp";
1077                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1078                 interrupt-names = "cif_isp10_irq";
1079                 status = "disabled";
1080         };
1081
1082         isp: isp@ff910000 {
1083                 compatible = "rockchip,rk3288-isp", "rockchip,isp";
1084                 reg = <0xff910000 0x4000>;
1085                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1086                 power-domains = <&power RK3288_PD_VIO>;
1087                 clocks =
1088                         <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
1089                         <&cru SCLK_ISP_JPE>, <&cru PCLK_ISP_IN>,
1090                         <&cru SCLK_VIP_OUT>, <&cru SCLK_MIPIDSI_24M>,
1091                         <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>;
1092                 clock-names =
1093                         "aclk_isp", "hclk_isp", "clk_isp",
1094                         "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
1095                         "clk_mipi_24m", "clk_cif_pll", "hclk_mipiphy1";
1096                 pinctrl-names =
1097                         "default", "isp_dvp8bit2", "isp_dvp10bit",
1098                         "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl",
1099                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
1100                         "isp_flash_as_trigger_out";
1101                 pinctrl-0 = <&isp_mipi>;
1102                 pinctrl-1 = <&isp_mipi &isp_dvp_d2d9>;
1103                 pinctrl-2 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1>;
1104                 pinctrl-3 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1
1105                                         &isp_dvp_d10d11>;
1106                 pinctrl-4 = <&isp_mipi &isp_dvp_d0d7>;
1107                 pinctrl-5 = <&isp_mipi>;
1108                 pinctrl-6 = <&isp_mipi &isp_prelight>;
1109                 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1110                 pinctrl-8 = <&isp_flash_trigger>;
1111                 rockchip,isp,mipiphy = <2>;
1112                 rockchip,isp,cifphy = <1>;
1113                 rockchip,isp,mipiphy1,reg = <0xff968000 0x4000>;
1114                 rockchip,grf = <&grf>;
1115                 rockchip,cru = <&cru>;
1116                 rockchip,gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>;
1117                 rockchip,isp,iommu_enable = <1>;
1118                 iommus = <&isp_mmu>;
1119                 status = "disabled";
1120         };
1121
1122         isp_mmu: iommu@ff914000 {
1123                 compatible = "rockchip,iommu";
1124                 reg = <0xff914000 0x100>, <0xff915000 0x100>;
1125                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1126                 interrupt-names = "isp_mmu";
1127                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1128                 clock-names = "aclk", "hclk";
1129                 rk_iommu,disable_reset_quirk;
1130                 #iommu-cells = <0>;
1131                 power-domains = <&power RK3288_PD_VIO>;
1132                 status = "disabled";
1133         };
1134
1135         rga: rga@ff920000 {
1136                 compatible = "rockchip,rk3288-rga";
1137                 reg = <0xff920000 0x180>;
1138                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1139                 interrupt-names = "rga";
1140                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1141                 clock-names = "aclk", "hclk", "sclk";
1142                 power-domains = <&power RK3288_PD_VIO>;
1143                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1144                 reset-names = "core", "axi", "ahb";
1145                 dma-coherent;
1146                 status = "disabled";
1147         };
1148
1149         vopb: vop@ff930000 {
1150                 compatible = "rockchip,rk3288-vop";
1151                 reg = <0xff930000 0x19c>;
1152                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1153                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1154                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1155                 power-domains = <&power RK3288_PD_VIO>;
1156                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1157                 reset-names = "axi", "ahb", "dclk";
1158                 iommus = <&vopb_mmu>;
1159                 status = "disabled";
1160
1161                 vopb_out: port {
1162                         #address-cells = <1>;
1163                         #size-cells = <0>;
1164
1165                         vopb_out_hdmi: endpoint@0 {
1166                                 reg = <0>;
1167                                 remote-endpoint = <&hdmi_in_vopb>;
1168                         };
1169
1170                         vopb_out_edp: endpoint@1 {
1171                                 reg = <1>;
1172                                 remote-endpoint = <&edp_in_vopb>;
1173                         };
1174
1175                         vopb_out_mipi: endpoint@2 {
1176                                 reg = <2>;
1177                                 remote-endpoint = <&mipi_in_vopb>;
1178                         };
1179
1180                         vopb_out_lvds: endpoint@3 {
1181                                 reg = <3>;
1182                                 remote-endpoint = <&lvds_in_vopb>;
1183                         };
1184                 };
1185         };
1186
1187         vopb_mmu: iommu@ff930300 {
1188                 compatible = "rockchip,iommu";
1189                 reg = <0xff930300 0x100>;
1190                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1191                 interrupt-names = "vopb_mmu";
1192                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1193                 clock-names = "aclk", "hclk";
1194                 power-domains = <&power RK3288_PD_VIO>;
1195                 #iommu-cells = <0>;
1196                 status = "disabled";
1197         };
1198
1199         vopl: vop@ff940000 {
1200                 compatible = "rockchip,rk3288-vop";
1201                 reg = <0xff940000 0x19c>;
1202                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1203                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1204                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1205                 power-domains = <&power RK3288_PD_VIO>;
1206                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1207                 reset-names = "axi", "ahb", "dclk";
1208                 iommus = <&vopl_mmu>;
1209                 status = "disabled";
1210
1211                 vopl_out: port {
1212                         #address-cells = <1>;
1213                         #size-cells = <0>;
1214
1215                         vopl_out_hdmi: endpoint@0 {
1216                                 reg = <0>;
1217                                 remote-endpoint = <&hdmi_in_vopl>;
1218                         };
1219
1220                         vopl_out_edp: endpoint@1 {
1221                                 reg = <1>;
1222                                 remote-endpoint = <&edp_in_vopl>;
1223                         };
1224
1225                         vopl_out_mipi: endpoint@2 {
1226                                 reg = <2>;
1227                                 remote-endpoint = <&mipi_in_vopl>;
1228                         };
1229
1230                         vopl_out_lvds: endpoint@3 {
1231                                 reg = <3>;
1232                                 remote-endpoint = <&lvds_in_vopl>;
1233                         };
1234
1235                 };
1236         };
1237
1238         vopl_mmu: iommu@ff940300 {
1239                 compatible = "rockchip,iommu";
1240                 reg = <0xff940300 0x100>;
1241                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1242                 interrupt-names = "vopl_mmu";
1243                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1244                 clock-names = "aclk", "hclk";
1245                 power-domains = <&power RK3288_PD_VIO>;
1246                 #iommu-cells = <0>;
1247                 status = "disabled";
1248         };
1249
1250         mipi_dsi: mipi@ff960000 {
1251                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1252                 reg = <0xff960000 0x4000>;
1253                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1254                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1255                 clock-names = "ref", "pclk";
1256                 power-domains = <&power RK3288_PD_VIO>;
1257                 rockchip,grf = <&grf>;
1258                 #address-cells = <1>;
1259                 #size-cells = <0>;
1260                 status = "disabled";
1261
1262                 ports {
1263                         mipi_in: port {
1264                                 #address-cells = <1>;
1265                                 #size-cells = <0>;
1266                                 mipi_in_vopb: endpoint@0 {
1267                                         reg = <0>;
1268                                         remote-endpoint = <&vopb_out_mipi>;
1269                                 };
1270                                 mipi_in_vopl: endpoint@1 {
1271                                         reg = <1>;
1272                                         remote-endpoint = <&vopl_out_mipi>;
1273                                 };
1274                         };
1275                 };
1276         };
1277
1278         edp: dp@ff970000 {
1279                 compatible = "rockchip,rk3288-dp";
1280                 reg = <0xff970000 0x4000>;
1281                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1282                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1283                 clock-names = "dp", "pclk";
1284                 power-domains = <&power RK3288_PD_VIO>;
1285                 phys = <&edp_phy>;
1286                 phy-names = "dp";
1287                 resets = <&cru SRST_EDP>;
1288                 reset-names = "dp";
1289                 rockchip,grf = <&grf>;
1290                 status = "disabled";
1291
1292                 ports {
1293                         #address-cells = <1>;
1294                         #size-cells = <0>;
1295                         edp_in: port@0 {
1296                                 reg = <0>;
1297                                 #address-cells = <1>;
1298                                 #size-cells = <0>;
1299                                 edp_in_vopb: endpoint@0 {
1300                                         reg = <0>;
1301                                         remote-endpoint = <&vopb_out_edp>;
1302                                 };
1303                                 edp_in_vopl: endpoint@1 {
1304                                         reg = <1>;
1305                                         remote-endpoint = <&vopl_out_edp>;
1306                                 };
1307                         };
1308                 };
1309         };
1310
1311         lvds: lvds@ff96c000 {
1312                 compatible = "rockchip,rk3288-lvds";
1313                 reg = <0xff96c000 0x4000>;
1314                 clocks = <&cru PCLK_LVDS_PHY>;
1315                 clock-names = "pclk_lvds";
1316                 pinctrl-names = "default";
1317                 pinctrl-0 = <&lcdc0_ctl>;
1318                 power-domains = <&power RK3288_PD_VIO>;
1319                 rockchip,grf = <&grf>;
1320                 status = "disabled";
1321
1322                 ports {
1323                         #address-cells = <1>;
1324                         #size-cells = <0>;
1325
1326                         lvds_in: port@0 {
1327                                 reg = <0>;
1328
1329                                 #address-cells = <1>;
1330                                 #size-cells = <0>;
1331
1332                                 lvds_in_vopb: endpoint@0 {
1333                                         reg = <0>;
1334                                         remote-endpoint = <&vopb_out_lvds>;
1335                                 };
1336                                 lvds_in_vopl: endpoint@1 {
1337                                         reg = <1>;
1338                                         remote-endpoint = <&vopl_out_lvds>;
1339                                 };
1340                         };
1341                 };
1342         };
1343
1344         hdmi: hdmi@ff980000 {
1345                 compatible = "rockchip,rk3288-dw-hdmi";
1346                 reg = <0xff980000 0x20000>;
1347                 reg-io-width = <4>;
1348                 rockchip,grf = <&grf>;
1349                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1350                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1351                 clock-names = "iahb", "isfr";
1352                 pinctrl-names = "default";
1353                 pinctrl-0 = <&hdmi_ddc>;
1354                 power-domains = <&power RK3288_PD_VIO>;
1355                 status = "disabled";
1356
1357                 ports {
1358                         hdmi_in: port {
1359                                 #address-cells = <1>;
1360                                 #size-cells = <0>;
1361                                 hdmi_in_vopb: endpoint@0 {
1362                                         reg = <0>;
1363                                         remote-endpoint = <&vopb_out_hdmi>;
1364                                 };
1365                                 hdmi_in_vopl: endpoint@1 {
1366                                         reg = <1>;
1367                                         remote-endpoint = <&vopl_out_hdmi>;
1368                                 };
1369                         };
1370                 };
1371         };
1372
1373         vpu: video-codec@ff9a0000 {
1374                 compatible = "rockchip,rk3288-vpu";
1375                 reg = <0xff9a0000 0x800>;
1376                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1377                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1378                 interrupt-names = "vepu", "vdpu";
1379                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1380                 clock-names = "aclk", "hclk";
1381                 power-domains = <&power RK3288_PD_VIDEO>;
1382                 iommus = <&vpu_mmu>;
1383                 assigned-clocks = <&cru ACLK_VCODEC>;
1384                 assigned-clock-rates = <400000000>;
1385                 status = "disabled";
1386         };
1387
1388         vpu_service: vpu-service@ff9a0000 {
1389                 compatible = "rockchip,vpu_service";
1390                 reg = <0xff9a0000 0x800>;
1391                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1392                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1393                 interrupt-names = "irq_enc", "irq_dec";
1394                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1395                 clock-names = "aclk_vcodec", "hclk_vcodec";
1396                 power-domains = <&power RK3288_PD_VIDEO>;
1397                 rockchip,grf = <&grf>;
1398                 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
1399                 reset-names = "video_a", "video_h";
1400                 iommus = <&vpu_mmu>;
1401                 iommu_enabled = <1>;
1402                 dev_mode = <0>;
1403                 status = "disabled";
1404                 /* 0 means ion, 1 means drm */
1405                 allocator = <1>;
1406         };
1407
1408         vpu_mmu: iommu@ff9a0800 {
1409                 compatible = "rockchip,iommu";
1410                 reg = <0xff9a0800 0x100>;
1411                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1412                 interrupt-names = "vpu_mmu";
1413                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1414                 clock-names = "aclk", "hclk";
1415                 power-domains = <&power RK3288_PD_VIDEO>;
1416                 #iommu-cells = <0>;
1417         };
1418
1419         hevc_service: hevc-service@ff9c0000 {
1420                 compatible = "rockchip,hevc_service";
1421                 reg = <0xff9c0000 0x400>;
1422                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1423                 interrupt-names = "irq_dec";
1424                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1425                         <&cru SCLK_HEVC_CORE>,
1426                         <&cru SCLK_HEVC_CABAC>;
1427                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
1428                         "clk_cabac";
1429                 /*
1430                  * The 4K hevc would also work well with 500/125/300/300,
1431                  * no more err irq and reset request.
1432                  */
1433                 assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1434                                   <&cru SCLK_HEVC_CORE>,
1435                                   <&cru SCLK_HEVC_CABAC>;
1436                 assigned-clock-rates = <400000000>, <100000000>,
1437                                        <300000000>, <300000000>;
1438
1439                 resets = <&cru SRST_HEVC>;
1440                 reset-names = "video";
1441                 power-domains = <&power RK3288_PD_HEVC>;
1442                 rockchip,grf = <&grf>;
1443                 dev_mode = <1>;
1444                 iommus = <&hevc_mmu>;
1445                 iommu_enabled = <1>;
1446                 status = "disabled";
1447                 /* 0 means ion, 1 means drm */
1448                 allocator = <1>;
1449         };
1450
1451         hevc_mmu: iommu@ff9c0440 {
1452                 compatible = "rockchip,iommu";
1453                 reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
1454                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1455                 interrupt-names = "hevc_mmu";
1456                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1457                         <&cru SCLK_HEVC_CORE>,
1458                         <&cru SCLK_HEVC_CABAC>;
1459                 clock-names = "aclk", "hclk", "clk_core",
1460                         "clk_cabac";
1461                 power-domains = <&power RK3288_PD_HEVC>;
1462                 #iommu-cells = <0>;
1463         };
1464
1465         gpu: gpu@ffa30000 {
1466                 compatible = "arm,malit764",
1467                              "arm,malit76x",
1468                              "arm,malit7xx",
1469                              "arm,mali-midgard";
1470                 reg = <0xffa30000 0x10000>;
1471                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1472                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1473                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1474                 interrupt-names = "JOB", "MMU", "GPU";
1475                 clocks = <&cru ACLK_GPU>;
1476                 clock-names = "clk_mali";
1477                 operating-points-v2 = <&gpu_opp_table>;
1478                 #cooling-cells = <2>; /* min followed by max */
1479                 power-domains = <&power RK3288_PD_GPU>;
1480                 status = "disabled";
1481
1482                 upthreshold = <75>;
1483                 downdifferential = <10>;
1484
1485                 gpu_power_model: power_model {
1486                         compatible = "arm,mali-simple-power-model";
1487                         voltage = <950>;
1488                         frequency = <500>;
1489                         static-power = <300>;
1490                         dynamic-power = <396>;
1491                         ts = <32000 4700 (-80) 2>;
1492                         thermal-zone = "gpu-thermal";
1493                 };
1494         };
1495
1496         gpu_opp_table: opp-table1 {
1497                 compatible = "operating-points-v2";
1498
1499                 opp-100000000 {
1500                         opp-hz = /bits/ 64 <100000000>;
1501                         opp-microvolt = <950000>;
1502                 };
1503                 opp-200000000 {
1504                         opp-hz = /bits/ 64 <200000000>;
1505                         opp-microvolt = <950000>;
1506                 };
1507                 opp-300000000 {
1508                         opp-hz = /bits/ 64 <300000000>;
1509                         opp-microvolt = <1000000>;
1510                 };
1511                 opp-400000000 {
1512                         opp-hz = /bits/ 64 <400000000>;
1513                         opp-microvolt = <1100000>;
1514                 };
1515                 opp-600000000 {
1516                         opp-hz = /bits/ 64 <600000000>;
1517                         opp-microvolt = <1250000>;
1518                 };
1519         };
1520
1521         noc: syscon@ffac0000 {
1522                 compatible = "rockchip,rk3288-noc", "syscon";
1523                 reg = <0xffac0000 0x2000>;
1524         };
1525
1526         efuse: efuse@ffb40000 {
1527                 compatible = "rockchip,rockchip-efuse";
1528                 reg = <0xffb40000 0x20>;
1529                 #address-cells = <1>;
1530                 #size-cells = <1>;
1531                 clocks = <&cru PCLK_EFUSE256>;
1532                 clock-names = "pclk_efuse";
1533
1534                 cpu_leakage: cpu_leakage@17 {
1535                         reg = <0x17 0x1>;
1536                 };
1537         };
1538
1539         gic: interrupt-controller@ffc01000 {
1540                 compatible = "arm,gic-400";
1541                 interrupt-controller;
1542                 #interrupt-cells = <3>;
1543                 #address-cells = <0>;
1544
1545                 reg = <0xffc01000 0x1000>,
1546                       <0xffc02000 0x2000>,
1547                       <0xffc04000 0x2000>,
1548                       <0xffc06000 0x2000>;
1549                 interrupts = <GIC_PPI 9 0xf04>;
1550         };
1551
1552         pinctrl: pinctrl {
1553                 compatible = "rockchip,rk3288-pinctrl";
1554                 rockchip,grf = <&grf>;
1555                 rockchip,pmu = <&pmu>;
1556                 #address-cells = <1>;
1557                 #size-cells = <1>;
1558                 ranges;
1559
1560                 gpio0: gpio0@ff750000 {
1561                         compatible = "rockchip,gpio-bank";
1562                         reg =   <0xff750000 0x100>;
1563                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1564                         clocks = <&cru PCLK_GPIO0>;
1565
1566                         gpio-controller;
1567                         #gpio-cells = <2>;
1568
1569                         interrupt-controller;
1570                         #interrupt-cells = <2>;
1571                 };
1572
1573                 gpio1: gpio1@ff780000 {
1574                         compatible = "rockchip,gpio-bank";
1575                         reg = <0xff780000 0x100>;
1576                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1577                         clocks = <&cru PCLK_GPIO1>;
1578
1579                         gpio-controller;
1580                         #gpio-cells = <2>;
1581
1582                         interrupt-controller;
1583                         #interrupt-cells = <2>;
1584                 };
1585
1586                 gpio2: gpio2@ff790000 {
1587                         compatible = "rockchip,gpio-bank";
1588                         reg = <0xff790000 0x100>;
1589                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1590                         clocks = <&cru PCLK_GPIO2>;
1591
1592                         gpio-controller;
1593                         #gpio-cells = <2>;
1594
1595                         interrupt-controller;
1596                         #interrupt-cells = <2>;
1597                 };
1598
1599                 gpio3: gpio3@ff7a0000 {
1600                         compatible = "rockchip,gpio-bank";
1601                         reg = <0xff7a0000 0x100>;
1602                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1603                         clocks = <&cru PCLK_GPIO3>;
1604
1605                         gpio-controller;
1606                         #gpio-cells = <2>;
1607
1608                         interrupt-controller;
1609                         #interrupt-cells = <2>;
1610                 };
1611
1612                 gpio4: gpio4@ff7b0000 {
1613                         compatible = "rockchip,gpio-bank";
1614                         reg = <0xff7b0000 0x100>;
1615                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1616                         clocks = <&cru PCLK_GPIO4>;
1617
1618                         gpio-controller;
1619                         #gpio-cells = <2>;
1620
1621                         interrupt-controller;
1622                         #interrupt-cells = <2>;
1623                 };
1624
1625                 gpio5: gpio5@ff7c0000 {
1626                         compatible = "rockchip,gpio-bank";
1627                         reg = <0xff7c0000 0x100>;
1628                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1629                         clocks = <&cru PCLK_GPIO5>;
1630
1631                         gpio-controller;
1632                         #gpio-cells = <2>;
1633
1634                         interrupt-controller;
1635                         #interrupt-cells = <2>;
1636                 };
1637
1638                 gpio6: gpio6@ff7d0000 {
1639                         compatible = "rockchip,gpio-bank";
1640                         reg = <0xff7d0000 0x100>;
1641                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1642                         clocks = <&cru PCLK_GPIO6>;
1643
1644                         gpio-controller;
1645                         #gpio-cells = <2>;
1646
1647                         interrupt-controller;
1648                         #interrupt-cells = <2>;
1649                 };
1650
1651                 gpio7: gpio7@ff7e0000 {
1652                         compatible = "rockchip,gpio-bank";
1653                         reg = <0xff7e0000 0x100>;
1654                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1655                         clocks = <&cru PCLK_GPIO7>;
1656
1657                         gpio-controller;
1658                         #gpio-cells = <2>;
1659
1660                         interrupt-controller;
1661                         #interrupt-cells = <2>;
1662                 };
1663
1664                 gpio8: gpio8@ff7f0000 {
1665                         compatible = "rockchip,gpio-bank";
1666                         reg = <0xff7f0000 0x100>;
1667                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1668                         clocks = <&cru PCLK_GPIO8>;
1669
1670                         gpio-controller;
1671                         #gpio-cells = <2>;
1672
1673                         interrupt-controller;
1674                         #interrupt-cells = <2>;
1675                 };
1676
1677                 hdmi {
1678                         hdmi_ddc: hdmi-ddc {
1679                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1680                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1681                         };
1682                 };
1683
1684                 pcfg_pull_up: pcfg-pull-up {
1685                         bias-pull-up;
1686                 };
1687
1688                 pcfg_pull_down: pcfg-pull-down {
1689                         bias-pull-down;
1690                 };
1691
1692                 pcfg_pull_none: pcfg-pull-none {
1693                         bias-disable;
1694                 };
1695
1696                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1697                         bias-disable;
1698                         drive-strength = <12>;
1699                 };
1700
1701                 sleep {
1702                         global_pwroff: global-pwroff {
1703                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1704                         };
1705
1706                         ddrio_pwroff: ddrio-pwroff {
1707                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1708                         };
1709
1710                         ddr0_retention: ddr0-retention {
1711                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1712                         };
1713
1714                         ddr1_retention: ddr1-retention {
1715                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1716                         };
1717                 };
1718
1719                 edp {
1720                         edp_hpd: edp-hpd {
1721                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1722                         };
1723                 };
1724
1725                 i2c0 {
1726                         i2c0_xfer: i2c0-xfer {
1727                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1728                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1729                         };
1730                 };
1731
1732                 i2c1 {
1733                         i2c1_xfer: i2c1-xfer {
1734                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1735                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1736                         };
1737                 };
1738
1739                 i2c2 {
1740                         i2c2_xfer: i2c2-xfer {
1741                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1742                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1743                         };
1744                 };
1745
1746                 i2c3 {
1747                         i2c3_xfer: i2c3-xfer {
1748                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1749                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1750                         };
1751                 };
1752
1753                 i2c4 {
1754                         i2c4_xfer: i2c4-xfer {
1755                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1756                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1757                         };
1758                 };
1759
1760                 i2c5 {
1761                         i2c5_xfer: i2c5-xfer {
1762                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1763                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1764                         };
1765                 };
1766
1767                 i2s0 {
1768                         i2s0_bus: i2s0-bus {
1769                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1770                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1771                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1772                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1773                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1774                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1775                         };
1776                 };
1777
1778                 lcdc0 {
1779                         lcdc0_ctl: lcdc0-ctl {
1780                                 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1781                                                 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1782                                                 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1783                                                 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1784                         };
1785                 };
1786
1787                 sdmmc {
1788                         sdmmc_clk: sdmmc-clk {
1789                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1790                         };
1791
1792                         sdmmc_cmd: sdmmc-cmd {
1793                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1794                         };
1795
1796                         sdmmc_cd: sdmmc-cd {
1797                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1798                         };
1799
1800                         sdmmc_bus1: sdmmc-bus1 {
1801                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1802                         };
1803
1804                         sdmmc_bus4: sdmmc-bus4 {
1805                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1806                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1807                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1808                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1809                         };
1810                 };
1811
1812                 sdio0 {
1813                         sdio0_bus1: sdio0-bus1 {
1814                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1815                         };
1816
1817                         sdio0_bus4: sdio0-bus4 {
1818                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1819                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1820                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1821                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1822                         };
1823
1824                         sdio0_cmd: sdio0-cmd {
1825                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1826                         };
1827
1828                         sdio0_clk: sdio0-clk {
1829                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1830                         };
1831
1832                         sdio0_cd: sdio0-cd {
1833                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1834                         };
1835
1836                         sdio0_wp: sdio0-wp {
1837                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1838                         };
1839
1840                         sdio0_pwr: sdio0-pwr {
1841                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1842                         };
1843
1844                         sdio0_bkpwr: sdio0-bkpwr {
1845                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1846                         };
1847
1848                         sdio0_int: sdio0-int {
1849                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1850                         };
1851                 };
1852
1853                 sdio1 {
1854                         sdio1_bus1: sdio1-bus1 {
1855                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1856                         };
1857
1858                         sdio1_bus4: sdio1-bus4 {
1859                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1860                                                 <3 25 4 &pcfg_pull_up>,
1861                                                 <3 26 4 &pcfg_pull_up>,
1862                                                 <3 27 4 &pcfg_pull_up>;
1863                         };
1864
1865                         sdio1_cd: sdio1-cd {
1866                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1867                         };
1868
1869                         sdio1_wp: sdio1-wp {
1870                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1871                         };
1872
1873                         sdio1_bkpwr: sdio1-bkpwr {
1874                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1875                         };
1876
1877                         sdio1_int: sdio1-int {
1878                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1879                         };
1880
1881                         sdio1_cmd: sdio1-cmd {
1882                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1883                         };
1884
1885                         sdio1_clk: sdio1-clk {
1886                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1887                         };
1888
1889                         sdio1_pwr: sdio1-pwr {
1890                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1891                         };
1892                 };
1893
1894                 emmc {
1895                         emmc_clk: emmc-clk {
1896                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1897                         };
1898
1899                         emmc_cmd: emmc-cmd {
1900                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1901                         };
1902
1903                         emmc_pwr: emmc-pwr {
1904                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1905                         };
1906
1907                         emmc_bus1: emmc-bus1 {
1908                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1909                         };
1910
1911                         emmc_bus4: emmc-bus4 {
1912                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1913                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1914                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1915                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1916                         };
1917
1918                         emmc_bus8: emmc-bus8 {
1919                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1920                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1921                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1922                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1923                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1924                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1925                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1926                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1927                         };
1928                 };
1929
1930                 spi0 {
1931                         spi0_clk: spi0-clk {
1932                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1933                         };
1934                         spi0_cs0: spi0-cs0 {
1935                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1936                         };
1937                         spi0_tx: spi0-tx {
1938                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1939                         };
1940                         spi0_rx: spi0-rx {
1941                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1942                         };
1943                         spi0_cs1: spi0-cs1 {
1944                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1945                         };
1946                 };
1947                 spi1 {
1948                         spi1_clk: spi1-clk {
1949                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1950                         };
1951                         spi1_cs0: spi1-cs0 {
1952                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1953                         };
1954                         spi1_rx: spi1-rx {
1955                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1956                         };
1957                         spi1_tx: spi1-tx {
1958                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1959                         };
1960                 };
1961
1962                 spi2 {
1963                         spi2_cs1: spi2-cs1 {
1964                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1965                         };
1966                         spi2_clk: spi2-clk {
1967                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1968                         };
1969                         spi2_cs0: spi2-cs0 {
1970                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1971                         };
1972                         spi2_rx: spi2-rx {
1973                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1974                         };
1975                         spi2_tx: spi2-tx {
1976                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1977                         };
1978                 };
1979
1980                 uart0 {
1981                         uart0_xfer: uart0-xfer {
1982                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1983                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1984                         };
1985
1986                         uart0_cts: uart0-cts {
1987                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1988                         };
1989
1990                         uart0_rts: uart0-rts {
1991                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1992                         };
1993                 };
1994
1995                 uart1 {
1996                         uart1_xfer: uart1-xfer {
1997                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1998                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1999                         };
2000
2001                         uart1_cts: uart1-cts {
2002                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
2003                         };
2004
2005                         uart1_rts: uart1-rts {
2006                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
2007                         };
2008                 };
2009
2010                 uart2 {
2011                         uart2_xfer: uart2-xfer {
2012                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
2013                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
2014                         };
2015                         /* no rts / cts for uart2 */
2016                 };
2017
2018                 uart3 {
2019                         uart3_xfer: uart3-xfer {
2020                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
2021                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
2022                         };
2023
2024                         uart3_cts: uart3-cts {
2025                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
2026                         };
2027
2028                         uart3_rts: uart3-rts {
2029                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
2030                         };
2031                 };
2032
2033                 uart4 {
2034                         uart4_xfer: uart4-xfer {
2035                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
2036                                                 <5 13 3 &pcfg_pull_none>;
2037                         };
2038
2039                         uart4_cts: uart4-cts {
2040                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
2041                         };
2042
2043                         uart4_rts: uart4-rts {
2044                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
2045                         };
2046                 };
2047
2048                 tsadc {
2049                         otp_gpio: otp-gpio {
2050                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
2051                         };
2052
2053                         otp_out: otp-out {
2054                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
2055                         };
2056                 };
2057
2058                 pwm0 {
2059                         pwm0_pin: pwm0-pin {
2060                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
2061                         };
2062                 };
2063
2064                 pwm1 {
2065                         pwm1_pin: pwm1-pin {
2066                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
2067                         };
2068                 };
2069
2070                 pwm2 {
2071                         pwm2_pin: pwm2-pin {
2072                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
2073                         };
2074                 };
2075
2076                 pwm3 {
2077                         pwm3_pin: pwm3-pin {
2078                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
2079                         };
2080                 };
2081
2082                 gmac {
2083                         rgmii_pins: rgmii-pins {
2084                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
2085                                                 <3 31 3 &pcfg_pull_none>,
2086                                                 <3 26 3 &pcfg_pull_none>,
2087                                                 <3 27 3 &pcfg_pull_none>,
2088                                                 <3 28 3 &pcfg_pull_none_12ma>,
2089                                                 <3 29 3 &pcfg_pull_none_12ma>,
2090                                                 <3 24 3 &pcfg_pull_none_12ma>,
2091                                                 <3 25 3 &pcfg_pull_none_12ma>,
2092                                                 <4 0 3 &pcfg_pull_none>,
2093                                                 <4 5 3 &pcfg_pull_none>,
2094                                                 <4 6 3 &pcfg_pull_none>,
2095                                                 <4 9 3 &pcfg_pull_none_12ma>,
2096                                                 <4 4 3 &pcfg_pull_none_12ma>,
2097                                                 <4 1 3 &pcfg_pull_none>,
2098                                                 <4 3 3 &pcfg_pull_none>;
2099                         };
2100
2101                         rmii_pins: rmii-pins {
2102                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
2103                                                 <3 31 3 &pcfg_pull_none>,
2104                                                 <3 28 3 &pcfg_pull_none>,
2105                                                 <3 29 3 &pcfg_pull_none>,
2106                                                 <4 0 3 &pcfg_pull_none>,
2107                                                 <4 5 3 &pcfg_pull_none>,
2108                                                 <4 4 3 &pcfg_pull_none>,
2109                                                 <4 1 3 &pcfg_pull_none>,
2110                                                 <4 2 3 &pcfg_pull_none>,
2111                                                 <4 3 3 &pcfg_pull_none>;
2112                         };
2113                 };
2114
2115                 spdif {
2116                         spdif_tx: spdif-tx {
2117                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
2118                         };
2119                 };
2120
2121                 cif {
2122                         cif_dvp_d2d9: cif-dvp-d2d9 {
2123                                 rockchip,pins = <2 0 RK_FUNC_1 &pcfg_pull_none>,
2124                                                 <2 1 RK_FUNC_1 &pcfg_pull_none>,
2125                                                 <2 2 RK_FUNC_1 &pcfg_pull_none>,
2126                                                 <2 3 RK_FUNC_1 &pcfg_pull_none>,
2127                                                 <2 4 RK_FUNC_1 &pcfg_pull_none>,
2128                                                 <2 5 RK_FUNC_1 &pcfg_pull_none>,
2129                                                 <2 6 RK_FUNC_1 &pcfg_pull_none>,
2130                                                 <2 7 RK_FUNC_1 &pcfg_pull_none>,
2131                                                 <2 8 RK_FUNC_1 &pcfg_pull_none>,
2132                                                 <2 9 RK_FUNC_1 &pcfg_pull_none>,
2133                                                 <2 11 RK_FUNC_1 &pcfg_pull_none>;
2134                         };
2135                 };
2136
2137                 isp_pin {
2138                         isp_mipi: isp-mipi {
2139                                 rockchip,pins =
2140                                         /* cif_clkout */
2141                                         <2 11 RK_FUNC_1 &pcfg_pull_none>;
2142                         };
2143
2144                         isp_dvp_d2d9: isp-d2d9 {
2145                                 rockchip,pins =
2146                                         /* cif_data2 ... cif_data9 */
2147                                         <2 0 RK_FUNC_1 &pcfg_pull_none>,
2148                                         <2 1 RK_FUNC_1 &pcfg_pull_none>,
2149                                         <2 2 RK_FUNC_1 &pcfg_pull_none>,
2150                                         <2 3 RK_FUNC_1 &pcfg_pull_none>,
2151                                         <2 4 RK_FUNC_1 &pcfg_pull_none>,
2152                                         <2 5 RK_FUNC_1 &pcfg_pull_none>,
2153                                         <2 6 RK_FUNC_1 &pcfg_pull_none>,
2154                                         <2 7 RK_FUNC_1 &pcfg_pull_none>,
2155                                         /* cif_sync, cif_href */
2156                                         <2 8 RK_FUNC_1 &pcfg_pull_none>,
2157                                         <2 9 RK_FUNC_1 &pcfg_pull_none>,
2158                                         /* cif_clkin, cif_clkout */
2159                                         <2 10 RK_FUNC_1 &pcfg_pull_none>,
2160                                         <2 11 RK_FUNC_1 &pcfg_pull_none>;
2161                         };
2162
2163                         isp_dvp_d0d1: isp-d0d1 {
2164                                 rockchip,pins =
2165                                         /* cif_data0, cif_data1 */
2166                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
2167                                         <2 13 RK_FUNC_1 &pcfg_pull_none>;
2168                         };
2169
2170                         isp_dvp_d10d11: isp-d10d11 {
2171                                 rockchip,pins =
2172                                         /* cif_data10, cif_data11 */
2173                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
2174                                         <2 15 RK_FUNC_1 &pcfg_pull_none>;
2175                         };
2176
2177                         isp_dvp_d0d7: isp-d0d7 {
2178                                 rockchip,pins =
2179                                         /* cif_data0 ... cif_data7 */
2180                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
2181                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
2182                                         <2 0 RK_FUNC_1 &pcfg_pull_none>,
2183                                         <2 1 RK_FUNC_1 &pcfg_pull_none>,
2184                                         <2 2 RK_FUNC_1 &pcfg_pull_none>,
2185                                         <2 3 RK_FUNC_1 &pcfg_pull_none>,
2186                                         <2 4 RK_FUNC_1 &pcfg_pull_none>,
2187                                         <2 5 RK_FUNC_1 &pcfg_pull_none>;
2188                         };
2189
2190                         isp_shutter: isp-shutter {
2191                                 rockchip,pins =
2192                                         /* SHUTTEREN, SHUTTERTRIG */
2193                                         <7 12 RK_FUNC_2 &pcfg_pull_none>,
2194                                         <7 15 RK_FUNC_2 &pcfg_pull_none>;
2195                         };
2196
2197                         isp_flash_trigger: isp-flash-trigger {
2198                                 rockchip,pins =
2199                                         /* ISP_FLASHTRIGOU */
2200                                         <7 13 RK_FUNC_2 &pcfg_pull_none>;
2201                         };
2202
2203                         isp_prelight: isp-prelight {
2204                                 rockchip,pins =
2205                                         /* ISP_PRELIGHTTRIG */
2206                                         <7 14 RK_FUNC_2 &pcfg_pull_none>;
2207                         };
2208
2209                         isp_flash_trigger_as_gpio: isp-flash-trigger-as-gpio {
2210                                 rockchip,pins =
2211                                         /* ISP_FLASHTRIGOU */
2212                                         <7 13 RK_FUNC_2 &pcfg_pull_none>;
2213                         };
2214                 };
2215
2216         };
2217 };