2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
15 #include <dt-bindings/interrupt-controller/arm-gic.h>
16 #include <dt-bindings/pinctrl/rockchip.h>
17 #include <dt-bindings/clock/rk3288-cru.h>
18 #include <dt-bindings/thermal/thermal.h>
19 #include "skeleton.dtsi"
22 compatible = "rockchip,rk3288";
24 interrupt-parent = <&gic>;
48 compatible = "arm,cortex-a12-pmu";
49 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
50 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
51 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
52 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
58 enable-method = "rockchip,rk3066-smp";
59 rockchip,pmu = <&pmu>;
63 compatible = "arm,cortex-a12";
65 resets = <&cru SRST_CORE0>;
81 #cooling-cells = <2>; /* min followed by max */
82 clock-latency = <40000>;
83 clocks = <&cru ARMCLK>;
87 compatible = "arm,cortex-a12";
89 resets = <&cru SRST_CORE1>;
93 compatible = "arm,cortex-a12";
95 resets = <&cru SRST_CORE2>;
99 compatible = "arm,cortex-a12";
101 resets = <&cru SRST_CORE3>;
106 compatible = "arm,amba-bus";
107 #address-cells = <1>;
111 dmac_peri: dma-controller@ff250000 {
112 compatible = "arm,pl330", "arm,primecell";
113 reg = <0xff250000 0x4000>;
114 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
115 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
117 clocks = <&cru ACLK_DMAC2>;
118 clock-names = "apb_pclk";
121 dmac_bus_ns: dma-controller@ff600000 {
122 compatible = "arm,pl330", "arm,primecell";
123 reg = <0xff600000 0x4000>;
124 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
127 clocks = <&cru ACLK_DMAC1>;
128 clock-names = "apb_pclk";
132 dmac_bus_s: dma-controller@ffb20000 {
133 compatible = "arm,pl330", "arm,primecell";
134 reg = <0xffb20000 0x4000>;
135 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
136 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
138 clocks = <&cru ACLK_DMAC1>;
139 clock-names = "apb_pclk";
144 compatible = "fixed-clock";
145 clock-frequency = <24000000>;
146 clock-output-names = "xin24m";
151 compatible = "arm,armv7-timer";
152 arm,cpu-registers-not-fw-configured;
153 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
154 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
155 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
156 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
157 clock-frequency = <24000000>;
160 timer: timer@ff810000 {
161 compatible = "rockchip,rk3288-timer";
162 reg = <0xff810000 0x20>;
163 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&xin24m>, <&cru PCLK_TIMER>;
165 clock-names = "timer", "pclk";
169 compatible = "rockchip,display-subsystem";
170 ports = <&vopl_out>, <&vopb_out>;
173 sdmmc: dwmmc@ff0c0000 {
174 compatible = "rockchip,rk3288-dw-mshc";
175 clock-freq-min-max = <400000 150000000>;
176 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
177 clock-names = "biu", "ciu";
178 fifo-depth = <0x100>;
179 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
180 reg = <0xff0c0000 0x4000>;
184 sdio0: dwmmc@ff0d0000 {
185 compatible = "rockchip,rk3288-dw-mshc";
186 clock-freq-min-max = <400000 150000000>;
187 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;
188 clock-names = "biu", "ciu";
189 fifo-depth = <0x100>;
190 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
191 reg = <0xff0d0000 0x4000>;
195 sdio1: dwmmc@ff0e0000 {
196 compatible = "rockchip,rk3288-dw-mshc";
197 clock-freq-min-max = <400000 150000000>;
198 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;
199 clock-names = "biu", "ciu";
200 fifo-depth = <0x100>;
201 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
202 reg = <0xff0e0000 0x4000>;
206 emmc: dwmmc@ff0f0000 {
207 compatible = "rockchip,rk3288-dw-mshc";
208 clock-freq-min-max = <400000 150000000>;
209 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
210 clock-names = "biu", "ciu";
211 fifo-depth = <0x100>;
212 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
213 reg = <0xff0f0000 0x4000>;
217 saradc: saradc@ff100000 {
218 compatible = "rockchip,saradc";
219 reg = <0xff100000 0x100>;
220 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
221 #io-channel-cells = <1>;
222 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
223 clock-names = "saradc", "apb_pclk";
228 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
229 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
230 clock-names = "spiclk", "apb_pclk";
231 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
232 dma-names = "tx", "rx";
233 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
234 pinctrl-names = "default";
235 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
236 reg = <0xff110000 0x1000>;
237 #address-cells = <1>;
243 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
244 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
245 clock-names = "spiclk", "apb_pclk";
246 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
247 dma-names = "tx", "rx";
248 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
249 pinctrl-names = "default";
250 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
251 reg = <0xff120000 0x1000>;
252 #address-cells = <1>;
258 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
259 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
260 clock-names = "spiclk", "apb_pclk";
261 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
262 dma-names = "tx", "rx";
263 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
264 pinctrl-names = "default";
265 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
266 reg = <0xff130000 0x1000>;
267 #address-cells = <1>;
273 compatible = "rockchip,rk3288-i2c";
274 reg = <0xff140000 0x1000>;
275 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
276 #address-cells = <1>;
279 clocks = <&cru PCLK_I2C1>;
280 pinctrl-names = "default";
281 pinctrl-0 = <&i2c1_xfer>;
286 compatible = "rockchip,rk3288-i2c";
287 reg = <0xff150000 0x1000>;
288 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
289 #address-cells = <1>;
292 clocks = <&cru PCLK_I2C3>;
293 pinctrl-names = "default";
294 pinctrl-0 = <&i2c3_xfer>;
299 compatible = "rockchip,rk3288-i2c";
300 reg = <0xff160000 0x1000>;
301 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
302 #address-cells = <1>;
305 clocks = <&cru PCLK_I2C4>;
306 pinctrl-names = "default";
307 pinctrl-0 = <&i2c4_xfer>;
312 compatible = "rockchip,rk3288-i2c";
313 reg = <0xff170000 0x1000>;
314 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
315 #address-cells = <1>;
318 clocks = <&cru PCLK_I2C5>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&i2c5_xfer>;
324 uart0: serial@ff180000 {
325 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
326 reg = <0xff180000 0x100>;
327 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
331 clock-names = "baudclk", "apb_pclk";
332 pinctrl-names = "default";
333 pinctrl-0 = <&uart0_xfer>;
337 uart1: serial@ff190000 {
338 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
339 reg = <0xff190000 0x100>;
340 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
344 clock-names = "baudclk", "apb_pclk";
345 pinctrl-names = "default";
346 pinctrl-0 = <&uart1_xfer>;
350 uart2: serial@ff690000 {
351 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
352 reg = <0xff690000 0x100>;
353 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
356 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
357 clock-names = "baudclk", "apb_pclk";
358 pinctrl-names = "default";
359 pinctrl-0 = <&uart2_xfer>;
363 uart3: serial@ff1b0000 {
364 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
365 reg = <0xff1b0000 0x100>;
366 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
369 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
370 clock-names = "baudclk", "apb_pclk";
371 pinctrl-names = "default";
372 pinctrl-0 = <&uart3_xfer>;
376 uart4: serial@ff1c0000 {
377 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
378 reg = <0xff1c0000 0x100>;
379 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
382 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
383 clock-names = "baudclk", "apb_pclk";
384 pinctrl-names = "default";
385 pinctrl-0 = <&uart4_xfer>;
390 #include "rk3288-thermal.dtsi"
393 tsadc: tsadc@ff280000 {
394 compatible = "rockchip,rk3288-tsadc";
395 reg = <0xff280000 0x100>;
396 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
398 clock-names = "tsadc", "apb_pclk";
399 resets = <&cru SRST_TSADC>;
400 reset-names = "tsadc-apb";
401 pinctrl-names = "default";
402 pinctrl-0 = <&otp_out>;
403 #thermal-sensor-cells = <1>;
404 rockchip,hw-tshut-temp = <95000>;
408 gmac: ethernet@ff290000 {
409 compatible = "rockchip,rk3288-gmac";
410 reg = <0xff290000 0x10000>;
411 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
412 interrupt-names = "macirq";
413 rockchip,grf = <&grf>;
414 clocks = <&cru SCLK_MAC>,
415 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
416 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
417 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
418 clock-names = "stmmaceth",
419 "mac_clk_rx", "mac_clk_tx",
420 "clk_mac_ref", "clk_mac_refout",
421 "aclk_mac", "pclk_mac";
425 usb_host0_ehci: usb@ff500000 {
426 compatible = "generic-ehci";
427 reg = <0xff500000 0x100>;
428 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
429 clocks = <&cru HCLK_USBHOST0>;
430 clock-names = "usbhost";
436 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
438 usb_host1: usb@ff540000 {
439 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
441 reg = <0xff540000 0x40000>;
442 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
443 clocks = <&cru HCLK_USBHOST1>;
447 phy-names = "usb2-phy";
451 usb_otg: usb@ff580000 {
452 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
454 reg = <0xff580000 0x40000>;
455 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&cru HCLK_OTG0>;
459 g-np-tx-fifo-size = <16>;
460 g-rx-fifo-size = <275>;
461 g-tx-fifo-size = <256 128 128 64 64 32>;
464 phy-names = "usb2-phy";
468 usb_hsic: usb@ff5c0000 {
469 compatible = "generic-ehci";
470 reg = <0xff5c0000 0x100>;
471 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
472 clocks = <&cru HCLK_HSIC>;
473 clock-names = "usbhost";
478 compatible = "rockchip,rk3288-i2c";
479 reg = <0xff650000 0x1000>;
480 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
481 #address-cells = <1>;
484 clocks = <&cru PCLK_I2C0>;
485 pinctrl-names = "default";
486 pinctrl-0 = <&i2c0_xfer>;
491 compatible = "rockchip,rk3288-i2c";
492 reg = <0xff660000 0x1000>;
493 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
494 #address-cells = <1>;
497 clocks = <&cru PCLK_I2C2>;
498 pinctrl-names = "default";
499 pinctrl-0 = <&i2c2_xfer>;
504 compatible = "rockchip,rk3288-pwm";
505 reg = <0xff680000 0x10>;
507 pinctrl-names = "default";
508 pinctrl-0 = <&pwm0_pin>;
509 clocks = <&cru PCLK_PWM>;
515 compatible = "rockchip,rk3288-pwm";
516 reg = <0xff680010 0x10>;
518 pinctrl-names = "default";
519 pinctrl-0 = <&pwm1_pin>;
520 clocks = <&cru PCLK_PWM>;
526 compatible = "rockchip,rk3288-pwm";
527 reg = <0xff680020 0x10>;
529 pinctrl-names = "default";
530 pinctrl-0 = <&pwm2_pin>;
531 clocks = <&cru PCLK_PWM>;
537 compatible = "rockchip,rk3288-pwm";
538 reg = <0xff680030 0x10>;
540 pinctrl-names = "default";
541 pinctrl-0 = <&pwm3_pin>;
542 clocks = <&cru PCLK_PWM>;
547 bus_intmem@ff700000 {
548 compatible = "mmio-sram";
549 reg = <0xff700000 0x18000>;
550 #address-cells = <1>;
552 ranges = <0 0xff700000 0x18000>;
554 compatible = "rockchip,rk3066-smp-sram";
560 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
561 reg = <0xff720000 0x1000>;
564 pmu: power-management@ff730000 {
565 compatible = "rockchip,rk3288-pmu", "syscon";
566 reg = <0xff730000 0x100>;
569 sgrf: syscon@ff740000 {
570 compatible = "rockchip,rk3288-sgrf", "syscon";
571 reg = <0xff740000 0x1000>;
574 cru: clock-controller@ff760000 {
575 compatible = "rockchip,rk3288-cru";
576 reg = <0xff760000 0x1000>;
577 rockchip,grf = <&grf>;
580 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
581 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
582 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
583 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
585 assigned-clock-rates = <594000000>, <400000000>,
586 <500000000>, <300000000>,
587 <150000000>, <75000000>,
588 <300000000>, <150000000>,
592 grf: syscon@ff770000 {
593 compatible = "rockchip,rk3288-grf", "syscon";
594 reg = <0xff770000 0x1000>;
597 wdt: watchdog@ff800000 {
598 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
599 reg = <0xff800000 0x100>;
600 clocks = <&cru PCLK_WDT>;
601 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
606 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
607 reg = <0xff890000 0x10000>;
608 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
609 #address-cells = <1>;
611 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
612 dma-names = "tx", "rx";
613 clock-names = "i2s_hclk", "i2s_clk";
614 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
615 pinctrl-names = "default";
616 pinctrl-0 = <&i2s0_bus>;
621 compatible = "rockchip,rk3288-vop";
622 reg = <0xff930000 0x19c>;
623 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
624 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
625 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
626 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
627 reset-names = "axi", "ahb", "dclk";
628 iommus = <&vopb_mmu>;
632 #address-cells = <1>;
635 vopb_out_hdmi: endpoint@0 {
637 remote-endpoint = <&hdmi_in_vopb>;
642 vopb_mmu: iommu@ff930300 {
643 compatible = "rockchip,iommu";
644 reg = <0xff930300 0x100>;
645 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
646 interrupt-names = "vopb_mmu";
652 compatible = "rockchip,rk3288-vop";
653 reg = <0xff940000 0x19c>;
654 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
656 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
657 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
658 reset-names = "axi", "ahb", "dclk";
659 iommus = <&vopl_mmu>;
663 #address-cells = <1>;
666 vopl_out_hdmi: endpoint@0 {
668 remote-endpoint = <&hdmi_in_vopl>;
673 vopl_mmu: iommu@ff940300 {
674 compatible = "rockchip,iommu";
675 reg = <0xff940300 0x100>;
676 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
677 interrupt-names = "vopl_mmu";
682 hdmi: hdmi@ff980000 {
683 compatible = "rockchip,rk3288-dw-hdmi";
684 reg = <0xff980000 0x20000>;
686 rockchip,grf = <&grf>;
687 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
688 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
689 clock-names = "iahb", "isfr";
694 #address-cells = <1>;
696 hdmi_in_vopb: endpoint@0 {
698 remote-endpoint = <&vopb_out_hdmi>;
700 hdmi_in_vopl: endpoint@1 {
702 remote-endpoint = <&vopl_out_hdmi>;
708 gic: interrupt-controller@ffc01000 {
709 compatible = "arm,gic-400";
710 interrupt-controller;
711 #interrupt-cells = <3>;
712 #address-cells = <0>;
714 reg = <0xffc01000 0x1000>,
718 interrupts = <GIC_PPI 9 0xf04>;
722 compatible = "rockchip,rk3288-usb-phy";
723 rockchip,grf = <&grf>;
724 #address-cells = <1>;
731 clocks = <&cru SCLK_OTGPHY0>;
732 clock-names = "phyclk";
738 clocks = <&cru SCLK_OTGPHY1>;
739 clock-names = "phyclk";
745 clocks = <&cru SCLK_OTGPHY2>;
746 clock-names = "phyclk";
751 compatible = "rockchip,rk3288-pinctrl";
752 rockchip,grf = <&grf>;
753 rockchip,pmu = <&pmu>;
754 #address-cells = <1>;
758 gpio0: gpio0@ff750000 {
759 compatible = "rockchip,gpio-bank";
760 reg = <0xff750000 0x100>;
761 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
762 clocks = <&cru PCLK_GPIO0>;
767 interrupt-controller;
768 #interrupt-cells = <2>;
771 gpio1: gpio1@ff780000 {
772 compatible = "rockchip,gpio-bank";
773 reg = <0xff780000 0x100>;
774 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
775 clocks = <&cru PCLK_GPIO1>;
780 interrupt-controller;
781 #interrupt-cells = <2>;
784 gpio2: gpio2@ff790000 {
785 compatible = "rockchip,gpio-bank";
786 reg = <0xff790000 0x100>;
787 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
788 clocks = <&cru PCLK_GPIO2>;
793 interrupt-controller;
794 #interrupt-cells = <2>;
797 gpio3: gpio3@ff7a0000 {
798 compatible = "rockchip,gpio-bank";
799 reg = <0xff7a0000 0x100>;
800 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
801 clocks = <&cru PCLK_GPIO3>;
806 interrupt-controller;
807 #interrupt-cells = <2>;
810 gpio4: gpio4@ff7b0000 {
811 compatible = "rockchip,gpio-bank";
812 reg = <0xff7b0000 0x100>;
813 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
814 clocks = <&cru PCLK_GPIO4>;
819 interrupt-controller;
820 #interrupt-cells = <2>;
823 gpio5: gpio5@ff7c0000 {
824 compatible = "rockchip,gpio-bank";
825 reg = <0xff7c0000 0x100>;
826 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
827 clocks = <&cru PCLK_GPIO5>;
832 interrupt-controller;
833 #interrupt-cells = <2>;
836 gpio6: gpio6@ff7d0000 {
837 compatible = "rockchip,gpio-bank";
838 reg = <0xff7d0000 0x100>;
839 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
840 clocks = <&cru PCLK_GPIO6>;
845 interrupt-controller;
846 #interrupt-cells = <2>;
849 gpio7: gpio7@ff7e0000 {
850 compatible = "rockchip,gpio-bank";
851 reg = <0xff7e0000 0x100>;
852 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
853 clocks = <&cru PCLK_GPIO7>;
858 interrupt-controller;
859 #interrupt-cells = <2>;
862 gpio8: gpio8@ff7f0000 {
863 compatible = "rockchip,gpio-bank";
864 reg = <0xff7f0000 0x100>;
865 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
866 clocks = <&cru PCLK_GPIO8>;
871 interrupt-controller;
872 #interrupt-cells = <2>;
875 pcfg_pull_up: pcfg-pull-up {
879 pcfg_pull_down: pcfg-pull-down {
883 pcfg_pull_none: pcfg-pull-none {
887 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
889 drive-strength = <12>;
893 global_pwroff: global-pwroff {
894 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
897 ddrio_pwroff: ddrio-pwroff {
898 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
901 ddr0_retention: ddr0-retention {
902 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
905 ddr1_retention: ddr1-retention {
906 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
911 i2c0_xfer: i2c0-xfer {
912 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
913 <0 16 RK_FUNC_1 &pcfg_pull_none>;
918 i2c1_xfer: i2c1-xfer {
919 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
920 <8 5 RK_FUNC_1 &pcfg_pull_none>;
925 i2c2_xfer: i2c2-xfer {
926 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
927 <6 10 RK_FUNC_1 &pcfg_pull_none>;
932 i2c3_xfer: i2c3-xfer {
933 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
934 <2 17 RK_FUNC_1 &pcfg_pull_none>;
939 i2c4_xfer: i2c4-xfer {
940 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
941 <7 18 RK_FUNC_1 &pcfg_pull_none>;
946 i2c5_xfer: i2c5-xfer {
947 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
948 <7 20 RK_FUNC_1 &pcfg_pull_none>;
954 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
955 <6 1 RK_FUNC_1 &pcfg_pull_none>,
956 <6 2 RK_FUNC_1 &pcfg_pull_none>,
957 <6 3 RK_FUNC_1 &pcfg_pull_none>,
958 <6 4 RK_FUNC_1 &pcfg_pull_none>,
959 <6 8 RK_FUNC_1 &pcfg_pull_none>;
964 sdmmc_clk: sdmmc-clk {
965 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
968 sdmmc_cmd: sdmmc-cmd {
969 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
973 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
976 sdmmc_bus1: sdmmc-bus1 {
977 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
980 sdmmc_bus4: sdmmc-bus4 {
981 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
982 <6 17 RK_FUNC_1 &pcfg_pull_up>,
983 <6 18 RK_FUNC_1 &pcfg_pull_up>,
984 <6 19 RK_FUNC_1 &pcfg_pull_up>;
989 sdio0_bus1: sdio0-bus1 {
990 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
993 sdio0_bus4: sdio0-bus4 {
994 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
995 <4 21 RK_FUNC_1 &pcfg_pull_up>,
996 <4 22 RK_FUNC_1 &pcfg_pull_up>,
997 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1000 sdio0_cmd: sdio0-cmd {
1001 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1004 sdio0_clk: sdio0-clk {
1005 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1008 sdio0_cd: sdio0-cd {
1009 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1012 sdio0_wp: sdio0-wp {
1013 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1016 sdio0_pwr: sdio0-pwr {
1017 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1020 sdio0_bkpwr: sdio0-bkpwr {
1021 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1024 sdio0_int: sdio0-int {
1025 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1030 sdio1_bus1: sdio1-bus1 {
1031 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1034 sdio1_bus4: sdio1-bus4 {
1035 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1036 <3 25 4 &pcfg_pull_up>,
1037 <3 26 4 &pcfg_pull_up>,
1038 <3 27 4 &pcfg_pull_up>;
1041 sdio1_cd: sdio1-cd {
1042 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1045 sdio1_wp: sdio1-wp {
1046 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1049 sdio1_bkpwr: sdio1-bkpwr {
1050 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1053 sdio1_int: sdio1-int {
1054 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1057 sdio1_cmd: sdio1-cmd {
1058 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1061 sdio1_clk: sdio1-clk {
1062 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1065 sdio1_pwr: sdio1-pwr {
1066 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1071 emmc_clk: emmc-clk {
1072 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1075 emmc_cmd: emmc-cmd {
1076 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1079 emmc_pwr: emmc-pwr {
1080 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1083 emmc_bus1: emmc-bus1 {
1084 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1087 emmc_bus4: emmc-bus4 {
1088 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1089 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1090 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1091 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1094 emmc_bus8: emmc-bus8 {
1095 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1096 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1097 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1098 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1099 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1100 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1101 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1102 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1107 spi0_clk: spi0-clk {
1108 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1110 spi0_cs0: spi0-cs0 {
1111 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1114 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1117 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1119 spi0_cs1: spi0-cs1 {
1120 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1124 spi1_clk: spi1-clk {
1125 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1127 spi1_cs0: spi1-cs0 {
1128 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1131 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1134 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1139 spi2_cs1: spi2-cs1 {
1140 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1142 spi2_clk: spi2-clk {
1143 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1145 spi2_cs0: spi2-cs0 {
1146 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1149 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1152 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1157 uart0_xfer: uart0-xfer {
1158 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1159 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1162 uart0_cts: uart0-cts {
1163 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_none>;
1166 uart0_rts: uart0-rts {
1167 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1172 uart1_xfer: uart1-xfer {
1173 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1174 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1177 uart1_cts: uart1-cts {
1178 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_none>;
1181 uart1_rts: uart1-rts {
1182 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1187 uart2_xfer: uart2-xfer {
1188 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1189 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1191 /* no rts / cts for uart2 */
1195 uart3_xfer: uart3-xfer {
1196 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1197 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1200 uart3_cts: uart3-cts {
1201 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_none>;
1204 uart3_rts: uart3-rts {
1205 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1210 uart4_xfer: uart4-xfer {
1211 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1212 <5 13 3 &pcfg_pull_none>;
1215 uart4_cts: uart4-cts {
1216 rockchip,pins = <5 14 3 &pcfg_pull_none>;
1219 uart4_rts: uart4-rts {
1220 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1226 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1231 pwm0_pin: pwm0-pin {
1232 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1237 pwm1_pin: pwm1-pin {
1238 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1243 pwm2_pin: pwm2-pin {
1244 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1249 pwm3_pin: pwm3-pin {
1250 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1255 rgmii_pins: rgmii-pins {
1256 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1257 <3 31 3 &pcfg_pull_none>,
1258 <3 26 3 &pcfg_pull_none>,
1259 <3 27 3 &pcfg_pull_none>,
1260 <3 28 3 &pcfg_pull_none_12ma>,
1261 <3 29 3 &pcfg_pull_none_12ma>,
1262 <3 24 3 &pcfg_pull_none_12ma>,
1263 <3 25 3 &pcfg_pull_none_12ma>,
1264 <4 0 3 &pcfg_pull_none>,
1265 <4 5 3 &pcfg_pull_none>,
1266 <4 6 3 &pcfg_pull_none>,
1267 <4 9 3 &pcfg_pull_none_12ma>,
1268 <4 4 3 &pcfg_pull_none_12ma>,
1269 <4 1 3 &pcfg_pull_none>,
1270 <4 3 3 &pcfg_pull_none>;
1273 rmii_pins: rmii-pins {
1274 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1275 <3 31 3 &pcfg_pull_none>,
1276 <3 28 3 &pcfg_pull_none>,
1277 <3 29 3 &pcfg_pull_none>,
1278 <4 0 3 &pcfg_pull_none>,
1279 <4 5 3 &pcfg_pull_none>,
1280 <4 4 3 &pcfg_pull_none>,
1281 <4 1 3 &pcfg_pull_none>,
1282 <4 2 3 &pcfg_pull_none>,
1283 <4 3 3 &pcfg_pull_none>;