arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include <dt-bindings/soc/rockchip_boot-mode.h>
  49 #include "skeleton.dtsi"
  50
  51 / {
  52         compatible = "rockchip,rk3288";
  53
  54         interrupt-parent = <&gic>;
  55
  56         aliases {
  57                 i2c0 = &i2c0;
  58                 i2c1 = &i2c1;
  59                 i2c2 = &i2c2;
  60                 i2c3 = &i2c3;
  61                 i2c4 = &i2c4;
  62                 i2c5 = &i2c5;
  63                 mshc0 = &emmc;
  64                 mshc1 = &sdmmc;
  65                 mshc2 = &sdio0;
  66                 mshc3 = &sdio1;
  67                 serial0 = &uart0;
  68                 serial1 = &uart1;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71                 serial4 = &uart4;
  72                 spi0 = &spi0;
  73                 spi1 = &spi1;
  74                 spi2 = &spi2;
  75         };
  76
  77         arm-pmu {
  78                 compatible = "arm,cortex-a12-pmu";
  79                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  80                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  82                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  83                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  84         };
  85
  86         cpus {
  87                 #address-cells = <1>;
  88                 #size-cells = <0>;
  89                 enable-method = "rockchip,rk3066-smp";
  90                 rockchip,pmu = <&pmu>;
  91
  92                 cpu0: cpu@500 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a12";
  95                         reg = <0x500>;
  96                         resets = <&cru SRST_CORE0>;
  97                         operating-points = <
  98                                 /* KHz    uV */
  99                                 1608000 1350000
 100                                 1512000 1300000
 101                                 1416000 1200000
 102                                 1200000 1100000
 103                                 1008000 1050000
 104                                  816000 1000000
 105                                  696000  950000
 106                                  600000  900000
 107                                  408000  900000
 108                                  312000  900000
 109                                  216000  900000
 110                                  126000  900000
 111                         >;
 112                         #cooling-cells = <2>; /* min followed by max */
 113                         clock-latency = <40000>;
 114                         clocks = <&cru ARMCLK>;
 115                 };
 116                 cpu1: cpu@501 {
 117                         device_type = "cpu";
 118                         compatible = "arm,cortex-a12";
 119                         reg = <0x501>;
 120                         resets = <&cru SRST_CORE1>;
 121                 };
 122                 cpu2: cpu@502 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a12";
 125                         reg = <0x502>;
 126                         resets = <&cru SRST_CORE2>;
 127                 };
 128                 cpu3: cpu@503 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a12";
 131                         reg = <0x503>;
 132                         resets = <&cru SRST_CORE3>;
 133                 };
 134         };
 135
 136         amba {
 137                 compatible = "arm,amba-bus";
 138                 #address-cells = <1>;
 139                 #size-cells = <1>;
 140                 ranges;
 141
 142                 dmac_peri: dma-controller@ff250000 {
 143                         compatible = "arm,pl330", "arm,primecell";
 144                         reg = <0xff250000 0x4000>;
 145                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 146                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 147                         #dma-cells = <1>;
 148                         arm,pl330-broken-no-flushp;
 149                         peripherals-req-type-burst;
 150                         clocks = <&cru ACLK_DMAC2>;
 151                         clock-names = "apb_pclk";
 152                 };
 153
 154                 dmac_bus_ns: dma-controller@ff600000 {
 155                         compatible = "arm,pl330", "arm,primecell";
 156                         reg = <0xff600000 0x4000>;
 157                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 158                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 159                         #dma-cells = <1>;
 160                         arm,pl330-broken-no-flushp;
 161                         peripherals-req-type-burst;
 162                         clocks = <&cru ACLK_DMAC1>;
 163                         clock-names = "apb_pclk";
 164                         status = "disabled";
 165                 };
 166
 167                 dmac_bus_s: dma-controller@ffb20000 {
 168                         compatible = "arm,pl330", "arm,primecell";
 169                         reg = <0xffb20000 0x4000>;
 170                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 171                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 172                         #dma-cells = <1>;
 173                         arm,pl330-broken-no-flushp;
 174                         peripherals-req-type-burst;
 175                         clocks = <&cru ACLK_DMAC1>;
 176                         clock-names = "apb_pclk";
 177                 };
 178         };
 179
 180         reserved-memory {
 181                 #address-cells = <1>;
 182                 #size-cells = <1>;
 183                 ranges;
 184
 185                 /*
 186                  * The rk3288 cannot use the memory area above 0xfe000000
 187                  * for dma operations for some reason. While there is
 188                  * probably a better solution available somewhere, we
 189                  * haven't found it yet and while devices with 2GB of ram
 190                  * are not affected, this issue prevents 4GB from booting.
 191                  * So to make these devices at least bootable, block
 192                  * this area for the time being until the real solution
 193                  * is found.
 194                  */
 195                 dma-unusable@fe000000 {
 196                         reg = <0xfe000000 0x1000000>;
 197                 };
 198         };
 199
 200         xin24m: oscillator {
 201                 compatible = "fixed-clock";
 202                 clock-frequency = <24000000>;
 203                 clock-output-names = "xin24m";
 204                 #clock-cells = <0>;
 205         };
 206
 207         edp_phy: edp-phy {
 208                 compatible = "rockchip,rk3288-dp-phy";
 209                 clocks = <&cru SCLK_EDP_24M>;
 210                 clock-names = "24m";
 211                 rockchip,grf = <&grf>;
 212                 #phy-cells = <0>;
 213                 status = "disabled";
 214         };
 215
 216         timer {
 217                 compatible = "arm,armv7-timer";
 218                 arm,cpu-registers-not-fw-configured;
 219                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 220                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 221                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 222                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 223                 clock-frequency = <24000000>;
 224         };
 225
 226         timer: timer@ff810000 {
 227                 compatible = "rockchip,rk3288-timer";
 228                 reg = <0xff810000 0x20>;
 229                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 230                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 231                 clock-names = "timer", "pclk";
 232         };
 233
 234         display-subsystem {
 235                 compatible = "rockchip,display-subsystem";
 236                 ports = <&vopl_out>, <&vopb_out>;
 237         };
 238
 239         sdmmc: dwmmc@ff0c0000 {
 240                 compatible = "rockchip,rk3288-dw-mshc";
 241                 clock-freq-min-max = <400000 150000000>;
 242                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 243                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 244                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 245                 fifo-depth = <0x100>;
 246                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 247                 reg = <0xff0c0000 0x4000>;
 248                 status = "disabled";
 249         };
 250
 251         sdio0: dwmmc@ff0d0000 {
 252                 compatible = "rockchip,rk3288-dw-mshc";
 253                 clock-freq-min-max = <400000 150000000>;
 254                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 255                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 256                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 257                 fifo-depth = <0x100>;
 258                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 259                 reg = <0xff0d0000 0x4000>;
 260                 status = "disabled";
 261         };
 262
 263         sdio1: dwmmc@ff0e0000 {
 264                 compatible = "rockchip,rk3288-dw-mshc";
 265                 clock-freq-min-max = <400000 150000000>;
 266                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 267                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 268                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 269                 fifo-depth = <0x100>;
 270                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 271                 reg = <0xff0e0000 0x4000>;
 272                 status = "disabled";
 273         };
 274
 275         emmc: dwmmc@ff0f0000 {
 276                 compatible = "rockchip,rk3288-dw-mshc";
 277                 clock-freq-min-max = <400000 150000000>;
 278                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 279                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 280                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 281                 fifo-depth = <0x100>;
 282                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 283                 reg = <0xff0f0000 0x4000>;
 284                 status = "disabled";
 285                 supports-emmc;
 286         };
 287
 288         saradc: saradc@ff100000 {
 289                 compatible = "rockchip,saradc";
 290                 reg = <0xff100000 0x100>;
 291                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 292                 #io-channel-cells = <1>;
 293                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 294                 clock-names = "saradc", "apb_pclk";
 295                 status = "disabled";
 296         };
 297
 298         spi0: spi@ff110000 {
 299                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 300                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 301                 clock-names = "spiclk", "apb_pclk";
 302                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 303                 dma-names = "tx", "rx";
 304                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 305                 pinctrl-names = "default";
 306                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 307                 reg = <0xff110000 0x1000>;
 308                 #address-cells = <1>;
 309                 #size-cells = <0>;
 310                 status = "disabled";
 311         };
 312
 313         spi1: spi@ff120000 {
 314                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 315                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 316                 clock-names = "spiclk", "apb_pclk";
 317                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 318                 dma-names = "tx", "rx";
 319                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 320                 pinctrl-names = "default";
 321                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 322                 reg = <0xff120000 0x1000>;
 323                 #address-cells = <1>;
 324                 #size-cells = <0>;
 325                 status = "disabled";
 326         };
 327
 328         spi2: spi@ff130000 {
 329                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 330                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 331                 clock-names = "spiclk", "apb_pclk";
 332                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 333                 dma-names = "tx", "rx";
 334                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 335                 pinctrl-names = "default";
 336                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 337                 reg = <0xff130000 0x1000>;
 338                 #address-cells = <1>;
 339                 #size-cells = <0>;
 340                 status = "disabled";
 341         };
 342
 343         i2c1: i2c@ff140000 {
 344                 compatible = "rockchip,rk3288-i2c";
 345                 reg = <0xff140000 0x1000>;
 346                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 347                 #address-cells = <1>;
 348                 #size-cells = <0>;
 349                 clock-names = "i2c";
 350                 clocks = <&cru PCLK_I2C1>;
 351                 pinctrl-names = "default";
 352                 pinctrl-0 = <&i2c1_xfer>;
 353                 status = "disabled";
 354         };
 355
 356         i2c3: i2c@ff150000 {
 357                 compatible = "rockchip,rk3288-i2c";
 358                 reg = <0xff150000 0x1000>;
 359                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 360                 #address-cells = <1>;
 361                 #size-cells = <0>;
 362                 clock-names = "i2c";
 363                 clocks = <&cru PCLK_I2C3>;
 364                 pinctrl-names = "default";
 365                 pinctrl-0 = <&i2c3_xfer>;
 366                 status = "disabled";
 367         };
 368
 369         i2c4: i2c@ff160000 {
 370                 compatible = "rockchip,rk3288-i2c";
 371                 reg = <0xff160000 0x1000>;
 372                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 373                 #address-cells = <1>;
 374                 #size-cells = <0>;
 375                 clock-names = "i2c";
 376                 clocks = <&cru PCLK_I2C4>;
 377                 pinctrl-names = "default";
 378                 pinctrl-0 = <&i2c4_xfer>;
 379                 status = "disabled";
 380         };
 381
 382         i2c5: i2c@ff170000 {
 383                 compatible = "rockchip,rk3288-i2c";
 384                 reg = <0xff170000 0x1000>;
 385                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 386                 #address-cells = <1>;
 387                 #size-cells = <0>;
 388                 clock-names = "i2c";
 389                 clocks = <&cru PCLK_I2C5>;
 390                 pinctrl-names = "default";
 391                 pinctrl-0 = <&i2c5_xfer>;
 392                 status = "disabled";
 393         };
 394
 395         uart0: serial@ff180000 {
 396                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 397                 reg = <0xff180000 0x100>;
 398                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 399                 reg-shift = <2>;
 400                 reg-io-width = <4>;
 401                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 402                 clock-names = "baudclk", "apb_pclk";
 403                 pinctrl-names = "default";
 404                 pinctrl-0 = <&uart0_xfer>;
 405                 status = "disabled";
 406         };
 407
 408         uart1: serial@ff190000 {
 409                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 410                 reg = <0xff190000 0x100>;
 411                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 412                 reg-shift = <2>;
 413                 reg-io-width = <4>;
 414                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 415                 clock-names = "baudclk", "apb_pclk";
 416                 pinctrl-names = "default";
 417                 pinctrl-0 = <&uart1_xfer>;
 418                 status = "disabled";
 419         };
 420
 421         uart2: serial@ff690000 {
 422                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 423                 reg = <0xff690000 0x100>;
 424                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 425                 reg-shift = <2>;
 426                 reg-io-width = <4>;
 427                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 428                 clock-names = "baudclk", "apb_pclk";
 429                 pinctrl-names = "default";
 430                 pinctrl-0 = <&uart2_xfer>;
 431                 status = "disabled";
 432         };
 433
 434         uart3: serial@ff1b0000 {
 435                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 436                 reg = <0xff1b0000 0x100>;
 437                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 438                 reg-shift = <2>;
 439                 reg-io-width = <4>;
 440                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 441                 clock-names = "baudclk", "apb_pclk";
 442                 pinctrl-names = "default";
 443                 pinctrl-0 = <&uart3_xfer>;
 444                 status = "disabled";
 445         };
 446
 447         uart4: serial@ff1c0000 {
 448                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 449                 reg = <0xff1c0000 0x100>;
 450                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 451                 reg-shift = <2>;
 452                 reg-io-width = <4>;
 453                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 454                 clock-names = "baudclk", "apb_pclk";
 455                 pinctrl-names = "default";
 456                 pinctrl-0 = <&uart4_xfer>;
 457                 status = "disabled";
 458         };
 459
 460         thermal-zones {
 461                 #include "rk3288-thermal.dtsi"
 462         };
 463
 464         tsadc: tsadc@ff280000 {
 465                 compatible = "rockchip,rk3288-tsadc";
 466                 reg = <0xff280000 0x100>;
 467                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 468                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 469                 clock-names = "tsadc", "apb_pclk";
 470                 resets = <&cru SRST_TSADC>;
 471                 reset-names = "tsadc-apb";
 472                 pinctrl-names = "init", "default", "sleep";
 473                 pinctrl-0 = <&otp_gpio>;
 474                 pinctrl-1 = <&otp_out>;
 475                 pinctrl-2 = <&otp_gpio>;
 476                 #thermal-sensor-cells = <1>;
 477                 rockchip,hw-tshut-temp = <95000>;
 478                 status = "disabled";
 479         };
 480
 481         gmac: ethernet@ff290000 {
 482                 compatible = "rockchip,rk3288-gmac";
 483                 reg = <0xff290000 0x10000>;
 484                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 485                 interrupt-names = "macirq";
 486                 rockchip,grf = <&grf>;
 487                 clocks = <&cru SCLK_MAC>,
 488                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 489                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 490                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 491                 clock-names = "stmmaceth",
 492                         "mac_clk_rx", "mac_clk_tx",
 493                         "clk_mac_ref", "clk_mac_refout",
 494                         "aclk_mac", "pclk_mac";
 495                 resets = <&cru SRST_MAC>;
 496                 reset-names = "stmmaceth";
 497                 max-speed = <100>;
 498                 status = "disabled";
 499         };
 500
 501         usb_host0_ehci: usb@ff500000 {
 502                 compatible = "generic-ehci";
 503                 reg = <0xff500000 0x100>;
 504                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 505                 clocks = <&cru HCLK_USBHOST0>;
 506                 clock-names = "usbhost";
 507                 phys = <&usbphy1>;
 508                 phy-names = "usb";
 509                 status = "disabled";
 510         };
 511
 512         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 513
 514         usb_host1: usb@ff540000 {
 515                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 516                                 "snps,dwc2";
 517                 reg = <0xff540000 0x40000>;
 518                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 519                 clocks = <&cru HCLK_USBHOST1>;
 520                 clock-names = "otg";
 521                 dr_mode = "host";
 522                 phys = <&usbphy2>;
 523                 phy-names = "usb2-phy";
 524                 status = "disabled";
 525         };
 526
 527         usb_otg: usb@ff580000 {
 528                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 529                                 "snps,dwc2";
 530                 reg = <0xff580000 0x40000>;
 531                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 532                 clocks = <&cru HCLK_OTG0>;
 533                 clock-names = "otg";
 534                 dr_mode = "otg";
 535                 g-np-tx-fifo-size = <16>;
 536                 g-rx-fifo-size = <275>;
 537                 g-tx-fifo-size = <256 128 128 64 64 32>;
 538                 g-use-dma;
 539                 phys = <&usbphy0>;
 540                 phy-names = "usb2-phy";
 541                 status = "disabled";
 542         };
 543
 544         usb_hsic: usb@ff5c0000 {
 545                 compatible = "generic-ehci";
 546                 reg = <0xff5c0000 0x100>;
 547                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 548                 clocks = <&cru HCLK_HSIC>;
 549                 clock-names = "usbhost";
 550                 status = "disabled";
 551         };
 552
 553         i2c0: i2c@ff650000 {
 554                 compatible = "rockchip,rk3288-i2c";
 555                 reg = <0xff650000 0x1000>;
 556                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 557                 #address-cells = <1>;
 558                 #size-cells = <0>;
 559                 clock-names = "i2c";
 560                 clocks = <&cru PCLK_I2C0>;
 561                 pinctrl-names = "default";
 562                 pinctrl-0 = <&i2c0_xfer>;
 563                 status = "disabled";
 564         };
 565
 566         i2c2: i2c@ff660000 {
 567                 compatible = "rockchip,rk3288-i2c";
 568                 reg = <0xff660000 0x1000>;
 569                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 570                 #address-cells = <1>;
 571                 #size-cells = <0>;
 572                 clock-names = "i2c";
 573                 clocks = <&cru PCLK_I2C2>;
 574                 pinctrl-names = "default";
 575                 pinctrl-0 = <&i2c2_xfer>;
 576                 status = "disabled";
 577         };
 578
 579         pwm0: pwm@ff680000 {
 580                 compatible = "rockchip,rk3288-pwm";
 581                 reg = <0xff680000 0x10>;
 582                 #pwm-cells = <3>;
 583                 pinctrl-names = "default";
 584                 pinctrl-0 = <&pwm0_pin>;
 585                 clocks = <&cru PCLK_PWM>;
 586                 clock-names = "pwm";
 587                 status = "disabled";
 588         };
 589
 590         pwm1: pwm@ff680010 {
 591                 compatible = "rockchip,rk3288-pwm";
 592                 reg = <0xff680010 0x10>;
 593                 #pwm-cells = <3>;
 594                 pinctrl-names = "default";
 595                 pinctrl-0 = <&pwm1_pin>;
 596                 clocks = <&cru PCLK_PWM>;
 597                 clock-names = "pwm";
 598                 status = "disabled";
 599         };
 600
 601         pwm2: pwm@ff680020 {
 602                 compatible = "rockchip,rk3288-pwm";
 603                 reg = <0xff680020 0x10>;
 604                 #pwm-cells = <3>;
 605                 pinctrl-names = "default";
 606                 pinctrl-0 = <&pwm2_pin>;
 607                 clocks = <&cru PCLK_PWM>;
 608                 clock-names = "pwm";
 609                 status = "disabled";
 610         };
 611
 612         pwm3: pwm@ff680030 {
 613                 compatible = "rockchip,rk3288-pwm";
 614                 reg = <0xff680030 0x10>;
 615                 #pwm-cells = <2>;
 616                 pinctrl-names = "default";
 617                 pinctrl-0 = <&pwm3_pin>;
 618                 clocks = <&cru PCLK_PWM>;
 619                 clock-names = "pwm";
 620                 status = "disabled";
 621         };
 622
 623         bus_intmem@ff700000 {
 624                 compatible = "mmio-sram";
 625                 reg = <0xff700000 0x18000>;
 626                 #address-cells = <1>;
 627                 #size-cells = <1>;
 628                 ranges = <0 0xff700000 0x18000>;
 629                 smp-sram@0 {
 630                         compatible = "rockchip,rk3066-smp-sram";
 631                         reg = <0x00 0x10>;
 632                 };
 633         };
 634
 635         sram@ff720000 {
 636                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 637                 reg = <0xff720000 0x1000>;
 638         };
 639
 640         pmu: power-management@ff730000 {
 641                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 642                 reg = <0xff730000 0x100>;
 643
 644                 power: power-controller {
 645                         compatible = "rockchip,rk3288-power-controller";
 646                         #power-domain-cells = <1>;
 647                         #address-cells = <1>;
 648                         #size-cells = <0>;
 649
 650                         /*
 651                          * Note: Although SCLK_* are the working clocks
 652                          * of device without including on the NOC, needed for
 653                          * synchronous reset.
 654                          *
 655                          * The clocks on the which NOC:
 656                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 657                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 658                          * ACLK_RGA is on ACLK_RGA_NIU.
 659                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 660                          *
 661                          * Which clock are device clocks:
 662                          *      clocks          devices
 663                          *      *_IEP           IEP:Image Enhancement Processor
 664                          *      *_ISP           ISP:Image Signal Processing
 665                          *      *_VIP           VIP:Video Input Processor
 666                          *      *_VOP*          VOP:Visual Output Processor
 667                          *      *_RGA           RGA
 668                          *      *_EDP*          EDP
 669                          *      *_LVDS_*        LVDS
 670                          *      *_HDMI          HDMI
 671                          *      *_MIPI_*        MIPI
 672                          */
 673                         pd_vio {
 674                                 reg = <RK3288_PD_VIO>;
 675                                 clocks = <&cru ACLK_IEP>,
 676                                          <&cru ACLK_ISP>,
 677                                          <&cru ACLK_RGA>,
 678                                          <&cru ACLK_VIP>,
 679                                          <&cru ACLK_VOP0>,
 680                                          <&cru ACLK_VOP1>,
 681                                          <&cru DCLK_VOP0>,
 682                                          <&cru DCLK_VOP1>,
 683                                          <&cru HCLK_IEP>,
 684                                          <&cru HCLK_ISP>,
 685                                          <&cru HCLK_RGA>,
 686                                          <&cru HCLK_VIP>,
 687                                          <&cru HCLK_VOP0>,
 688                                          <&cru HCLK_VOP1>,
 689                                          <&cru PCLK_EDP_CTRL>,
 690                                          <&cru PCLK_HDMI_CTRL>,
 691                                          <&cru PCLK_LVDS_PHY>,
 692                                          <&cru PCLK_MIPI_CSI>,
 693                                          <&cru PCLK_MIPI_DSI0>,
 694                                          <&cru PCLK_MIPI_DSI1>,
 695                                          <&cru SCLK_EDP_24M>,
 696                                          <&cru SCLK_EDP>,
 697                                          <&cru SCLK_ISP_JPE>,
 698                                          <&cru SCLK_ISP>,
 699                                          <&cru SCLK_RGA>;
 700                         };
 701
 702                         /*
 703                          * Note: The following 3 are HEVC(H.265) clocks,
 704                          * and on the ACLK_HEVC_NIU (NOC).
 705                          */
 706                         pd_hevc {
 707                                 reg = <RK3288_PD_HEVC>;
 708                                 clocks = <&cru ACLK_HEVC>,
 709                                          <&cru SCLK_HEVC_CABAC>,
 710                                          <&cru SCLK_HEVC_CORE>;
 711                         };
 712
 713                         /*
 714                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 715                          * (video endecoder & decoder) clocks that on the
 716                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 717                          */
 718                         pd_video {
 719                                 reg = <RK3288_PD_VIDEO>;
 720                                 clocks = <&cru ACLK_VCODEC>,
 721                                          <&cru HCLK_VCODEC>;
 722                         };
 723
 724                         /*
 725                          * Note: ACLK_GPU is the GPU clock,
 726                          * and on the ACLK_GPU_NIU (NOC).
 727                          */
 728                         pd_gpu {
 729                                 reg = <RK3288_PD_GPU>;
 730                                 clocks = <&cru ACLK_GPU>;
 731                         };
 732                 };
 733
 734                 reboot-mode {
 735                         compatible = "syscon-reboot-mode";
 736                         offset = <0x94>;
 737                         mode-normal = <BOOT_NORMAL>;
 738                         mode-recovery = <BOOT_RECOVERY>;
 739                         mode-bootloader = <BOOT_FASTBOOT>;
 740                         mode-loader = <BOOT_LOADER>;
 741                         mode-ums = <BOOT_UMS>;
 742                 };
 743         };
 744
 745         sgrf: syscon@ff740000 {
 746                 compatible = "rockchip,rk3288-sgrf", "syscon";
 747                 reg = <0xff740000 0x1000>;
 748         };
 749
 750         cru: clock-controller@ff760000 {
 751                 compatible = "rockchip,rk3288-cru";
 752                 reg = <0xff760000 0x1000>;
 753                 rockchip,grf = <&grf>;
 754                 #clock-cells = <1>;
 755                 #reset-cells = <1>;
 756                 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
 757                                   <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 758                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 759                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 760                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 761                                   <&cru PCLK_PERI>;
 762                 assigned-clock-rates = <0>, <0>,
 763                                        <594000000>, <400000000>,
 764                                        <500000000>, <300000000>,
 765                                        <150000000>, <75000000>,
 766                                        <300000000>, <150000000>,
 767                                        <75000000>;
 768                 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
 769         };
 770
 771         grf: syscon@ff770000 {
 772                 compatible = "rockchip,rk3288-grf", "syscon";
 773                 reg = <0xff770000 0x1000>;
 774         };
 775
 776         wdt: watchdog@ff800000 {
 777                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 778                 reg = <0xff800000 0x100>;
 779                 clocks = <&cru PCLK_WDT>;
 780                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 781                 status = "disabled";
 782         };
 783
 784         spdif: sound@ff88b0000 {
 785                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 786                 reg = <0xff8b0000 0x10000>;
 787                 #sound-dai-cells = <0>;
 788                 clock-names = "hclk", "mclk";
 789                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 790                 dmas = <&dmac_bus_s 3>;
 791                 dma-names = "tx";
 792                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 793                 pinctrl-names = "default";
 794                 pinctrl-0 = <&spdif_tx>;
 795                 rockchip,grf = <&grf>;
 796                 status = "disabled";
 797         };
 798
 799         i2s: i2s@ff890000 {
 800                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 801                 reg = <0xff890000 0x10000>;
 802                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 803                 #address-cells = <1>;
 804                 #size-cells = <0>;
 805                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 806                 dma-names = "tx", "rx";
 807                 clock-names = "i2s_hclk", "i2s_clk";
 808                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 809                 pinctrl-names = "default";
 810                 pinctrl-0 = <&i2s0_bus>;
 811                 status = "disabled";
 812         };
 813
 814         vopb: vop@ff930000 {
 815                 compatible = "rockchip,rk3288-vop";
 816                 reg = <0xff930000 0x19c>;
 817                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 818                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 819                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 820                 power-domains = <&power RK3288_PD_VIO>;
 821                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 822                 reset-names = "axi", "ahb", "dclk";
 823                 iommus = <&vopb_mmu>;
 824                 status = "disabled";
 825
 826                 vopb_out: port {
 827                         #address-cells = <1>;
 828                         #size-cells = <0>;
 829
 830                         vopb_out_hdmi: endpoint@0 {
 831                                 reg = <0>;
 832                                 remote-endpoint = <&hdmi_in_vopb>;
 833                         };
 834
 835                         vopb_out_edp: endpoint@1 {
 836                                 reg = <1>;
 837                                 remote-endpoint = <&edp_in_vopb>;
 838                         };
 839
 840                         vopb_out_mipi: endpoint@2 {
 841                                 reg = <2>;
 842                                 remote-endpoint = <&mipi_in_vopb>;
 843                         };
 844
 845                         vopb_out_lvds: endpoint@3 {
 846                                 reg = <3>;
 847                                 remote-endpoint = <&lvds_in_vopb>;
 848                         };
 849                 };
 850         };
 851
 852         vopb_mmu: iommu@ff930300 {
 853                 compatible = "rockchip,iommu";
 854                 reg = <0xff930300 0x100>;
 855                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 856                 interrupt-names = "vopb_mmu";
 857                 power-domains = <&power RK3288_PD_VIO>;
 858                 #iommu-cells = <0>;
 859                 status = "disabled";
 860         };
 861
 862         vopl: vop@ff940000 {
 863                 compatible = "rockchip,rk3288-vop";
 864                 reg = <0xff940000 0x19c>;
 865                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 866                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 867                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 868                 power-domains = <&power RK3288_PD_VIO>;
 869                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 870                 reset-names = "axi", "ahb", "dclk";
 871                 iommus = <&vopl_mmu>;
 872                 status = "disabled";
 873
 874                 vopl_out: port {
 875                         #address-cells = <1>;
 876                         #size-cells = <0>;
 877
 878                         vopl_out_hdmi: endpoint@0 {
 879                                 reg = <0>;
 880                                 remote-endpoint = <&hdmi_in_vopl>;
 881                         };
 882
 883                         vopl_out_edp: endpoint@1 {
 884                                 reg = <1>;
 885                                 remote-endpoint = <&edp_in_vopl>;
 886                         };
 887
 888                         vopl_out_mipi: endpoint@2 {
 889                                 reg = <2>;
 890                                 remote-endpoint = <&mipi_in_vopl>;
 891                         };
 892
 893                         vopl_out_lvds: endpoint@3 {
 894                                 reg = <3>;
 895                                 remote-endpoint = <&lvds_in_vopl>;
 896                         };
 897
 898                 };
 899         };
 900
 901         vopl_mmu: iommu@ff940300 {
 902                 compatible = "rockchip,iommu";
 903                 reg = <0xff940300 0x100>;
 904                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 905                 interrupt-names = "vopl_mmu";
 906                 power-domains = <&power RK3288_PD_VIO>;
 907                 #iommu-cells = <0>;
 908                 status = "disabled";
 909         };
 910
 911         mipi_dsi: mipi@ff960000 {
 912                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
 913                 reg = <0xff960000 0x4000>;
 914                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 915                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
 916                 clock-names = "ref", "pclk";
 917                 rockchip,grf = <&grf>;
 918                 #address-cells = <1>;
 919                 #size-cells = <0>;
 920                 status = "disabled";
 921
 922                 ports {
 923                         #address-cells = <1>;
 924                         #size-cells = <0>;
 925                         reg = <1>;
 926
 927                         mipi_in: port {
 928                                 #address-cells = <1>;
 929                                 #size-cells = <0>;
 930                                 mipi_in_vopb: endpoint@0 {
 931                                         reg = <0>;
 932                                         remote-endpoint = <&vopb_out_mipi>;
 933                                 };
 934                                 mipi_in_vopl: endpoint@1 {
 935                                         reg = <1>;
 936                                         remote-endpoint = <&vopl_out_mipi>;
 937                                 };
 938                         };
 939                 };
 940         };
 941
 942         edp: dp@ff970000 {
 943                 compatible = "rockchip,rk3288-dp";
 944                 reg = <0xff970000 0x4000>;
 945                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 946                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
 947                 clock-names = "dp", "pclk";
 948                 phys = <&edp_phy>;
 949                 phy-names = "dp";
 950                 resets = <&cru SRST_EDP>;
 951                 reset-names = "dp";
 952                 rockchip,grf = <&grf>;
 953                 status = "disabled";
 954
 955                 ports {
 956                         #address-cells = <1>;
 957                         #size-cells = <0>;
 958                         edp_in: port@0 {
 959                                 reg = <0>;
 960                                 #address-cells = <1>;
 961                                 #size-cells = <0>;
 962                                 edp_in_vopb: endpoint@0 {
 963                                         reg = <0>;
 964                                         remote-endpoint = <&vopb_out_edp>;
 965                                 };
 966                                 edp_in_vopl: endpoint@1 {
 967                                         reg = <1>;
 968                                         remote-endpoint = <&vopl_out_edp>;
 969                                 };
 970                         };
 971                 };
 972         };
 973
 974         lvds: lvds@ff96c000 {
 975                 compatible = "rockchip,rk3288-lvds";
 976                 reg = <0xff96c000 0x4000>;
 977                 clocks = <&cru PCLK_LVDS_PHY>;
 978                 clock-names = "pclk_lvds";
 979                 pinctrl-names = "default";
 980                 pinctrl-0 = <&lcdc0_ctl>;
 981                 power-domains = <&power RK3288_PD_VIO>;
 982                 rockchip,grf = <&grf>;
 983                 status = "disabled";
 984
 985                 ports {
 986                         #address-cells = <1>;
 987                         #size-cells = <0>;
 988
 989                         lvds_in: port@0 {
 990                                 reg = <0>;
 991
 992                                 #address-cells = <1>;
 993                                 #size-cells = <0>;
 994
 995                                 lvds_in_vopb: endpoint@0 {
 996                                         reg = <0>;
 997                                         remote-endpoint = <&vopb_out_lvds>;
 998                                 };
 999                                 lvds_in_vopl: endpoint@1 {
1000                                         reg = <1>;
1001                                         remote-endpoint = <&vopl_out_lvds>;
1002                                 };
1003                         };
1004                 };
1005         };
1006
1007         hdmi: hdmi@ff980000 {
1008                 compatible = "rockchip,rk3288-dw-hdmi";
1009                 reg = <0xff980000 0x20000>;
1010                 reg-io-width = <4>;
1011                 rockchip,grf = <&grf>;
1012                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1013                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1014                 clock-names = "iahb", "isfr";
1015                 power-domains = <&power RK3288_PD_VIO>;
1016                 status = "disabled";
1017
1018                 ports {
1019                         hdmi_in: port {
1020                                 #address-cells = <1>;
1021                                 #size-cells = <0>;
1022                                 hdmi_in_vopb: endpoint@0 {
1023                                         reg = <0>;
1024                                         remote-endpoint = <&vopb_out_hdmi>;
1025                                 };
1026                                 hdmi_in_vopl: endpoint@1 {
1027                                         reg = <1>;
1028                                         remote-endpoint = <&vopl_out_hdmi>;
1029                                 };
1030                         };
1031                 };
1032         };
1033
1034         gpu: gpu@ffa30000 {
1035                 compatible = "arm,malit764",
1036                              "arm,malit76x",
1037                              "arm,malit7xx",
1038                              "arm,mali-midgard";
1039                 reg = <0xffa30000 0x10000>;
1040                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1041                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1042                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1043                 interrupt-names = "JOB", "MMU", "GPU";
1044                 clocks = <&cru ACLK_GPU>;
1045                 clock-names = "clk_mali";
1046                 operating-points = <
1047                         /* KHz uV */
1048                         600000 1250000
1049                         /* 500000 1200000 - See crosbug.com/p/33857 */
1050                         400000 1100000
1051                         300000 1000000
1052                         200000 950000
1053                         100000 950000
1054                 >;
1055                 #cooling-cells = <2>; /* min followed by max */
1056                 power-domains = <&power RK3288_PD_GPU>;
1057                 status = "disabled";
1058         };
1059
1060         vpu: video-codec@ff9a0000 {
1061                 compatible = "rockchip,rk3288-vpu";
1062                 reg = <0xff9a0000 0x800>;
1063                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1064                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1065                 interrupt-names = "vepu", "vdpu";
1066                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1067                 clock-names = "aclk", "hclk";
1068                 power-domains = <&power RK3288_PD_VIDEO>;
1069                 iommus = <&vpu_mmu>;
1070                 assigned-clocks = <&cru ACLK_VCODEC>;
1071                 assigned-clock-rates = <400000000>;
1072                 status = "disabled";
1073         };
1074
1075         vpu_mmu: iommu@ff9a0800 {
1076                 compatible = "rockchip,iommu";
1077                 reg = <0xff9a0800 0x100>;
1078                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1079                 interrupt-names = "vpu_mmu";
1080                 power-domains = <&power RK3288_PD_VIDEO>;
1081                 #iommu-cells = <0>;
1082         };
1083
1084         gic: interrupt-controller@ffc01000 {
1085                 compatible = "arm,gic-400";
1086                 interrupt-controller;
1087                 #interrupt-cells = <3>;
1088                 #address-cells = <0>;
1089
1090                 reg = <0xffc01000 0x1000>,
1091                       <0xffc02000 0x1000>,
1092                       <0xffc04000 0x2000>,
1093                       <0xffc06000 0x2000>;
1094                 interrupts = <GIC_PPI 9 0xf04>;
1095         };
1096
1097         efuse: efuse@ffb40000 {
1098                 compatible = "rockchip,rockchip-efuse";
1099                 reg = <0xffb40000 0x20>;
1100                 #address-cells = <1>;
1101                 #size-cells = <1>;
1102                 clocks = <&cru PCLK_EFUSE256>;
1103                 clock-names = "pclk_efuse";
1104
1105                 cpu_leakage: cpu_leakage@17 {
1106                         reg = <0x17 0x1>;
1107                 };
1108         };
1109
1110         usbphy: phy {
1111                 compatible = "rockchip,rk3288-usb-phy";
1112                 rockchip,grf = <&grf>;
1113                 #address-cells = <1>;
1114                 #size-cells = <0>;
1115                 status = "disabled";
1116
1117                 usbphy0: usb-phy0 {
1118                         #phy-cells = <0>;
1119                         reg = <0x320>;
1120                         clocks = <&cru SCLK_OTGPHY0>;
1121                         clock-names = "phyclk";
1122                 };
1123
1124                 usbphy1: usb-phy1 {
1125                         #phy-cells = <0>;
1126                         reg = <0x334>;
1127                         clocks = <&cru SCLK_OTGPHY1>;
1128                         clock-names = "phyclk";
1129                 };
1130
1131                 usbphy2: usb-phy2 {
1132                         #phy-cells = <0>;
1133                         reg = <0x348>;
1134                         clocks = <&cru SCLK_OTGPHY2>;
1135                         clock-names = "phyclk";
1136                 };
1137         };
1138
1139         pinctrl: pinctrl {
1140                 compatible = "rockchip,rk3288-pinctrl";
1141                 rockchip,grf = <&grf>;
1142                 rockchip,pmu = <&pmu>;
1143                 #address-cells = <1>;
1144                 #size-cells = <1>;
1145                 ranges;
1146
1147                 gpio0: gpio0@ff750000 {
1148                         compatible = "rockchip,gpio-bank";
1149                         reg =   <0xff750000 0x100>;
1150                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1151                         clocks = <&cru PCLK_GPIO0>;
1152
1153                         gpio-controller;
1154                         #gpio-cells = <2>;
1155
1156                         interrupt-controller;
1157                         #interrupt-cells = <2>;
1158                 };
1159
1160                 gpio1: gpio1@ff780000 {
1161                         compatible = "rockchip,gpio-bank";
1162                         reg = <0xff780000 0x100>;
1163                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1164                         clocks = <&cru PCLK_GPIO1>;
1165
1166                         gpio-controller;
1167                         #gpio-cells = <2>;
1168
1169                         interrupt-controller;
1170                         #interrupt-cells = <2>;
1171                 };
1172
1173                 gpio2: gpio2@ff790000 {
1174                         compatible = "rockchip,gpio-bank";
1175                         reg = <0xff790000 0x100>;
1176                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1177                         clocks = <&cru PCLK_GPIO2>;
1178
1179                         gpio-controller;
1180                         #gpio-cells = <2>;
1181
1182                         interrupt-controller;
1183                         #interrupt-cells = <2>;
1184                 };
1185
1186                 gpio3: gpio3@ff7a0000 {
1187                         compatible = "rockchip,gpio-bank";
1188                         reg = <0xff7a0000 0x100>;
1189                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1190                         clocks = <&cru PCLK_GPIO3>;
1191
1192                         gpio-controller;
1193                         #gpio-cells = <2>;
1194
1195                         interrupt-controller;
1196                         #interrupt-cells = <2>;
1197                 };
1198
1199                 gpio4: gpio4@ff7b0000 {
1200                         compatible = "rockchip,gpio-bank";
1201                         reg = <0xff7b0000 0x100>;
1202                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1203                         clocks = <&cru PCLK_GPIO4>;
1204
1205                         gpio-controller;
1206                         #gpio-cells = <2>;
1207
1208                         interrupt-controller;
1209                         #interrupt-cells = <2>;
1210                 };
1211
1212                 gpio5: gpio5@ff7c0000 {
1213                         compatible = "rockchip,gpio-bank";
1214                         reg = <0xff7c0000 0x100>;
1215                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1216                         clocks = <&cru PCLK_GPIO5>;
1217
1218                         gpio-controller;
1219                         #gpio-cells = <2>;
1220
1221                         interrupt-controller;
1222                         #interrupt-cells = <2>;
1223                 };
1224
1225                 gpio6: gpio6@ff7d0000 {
1226                         compatible = "rockchip,gpio-bank";
1227                         reg = <0xff7d0000 0x100>;
1228                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1229                         clocks = <&cru PCLK_GPIO6>;
1230
1231                         gpio-controller;
1232                         #gpio-cells = <2>;
1233
1234                         interrupt-controller;
1235                         #interrupt-cells = <2>;
1236                 };
1237
1238                 gpio7: gpio7@ff7e0000 {
1239                         compatible = "rockchip,gpio-bank";
1240                         reg = <0xff7e0000 0x100>;
1241                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1242                         clocks = <&cru PCLK_GPIO7>;
1243
1244                         gpio-controller;
1245                         #gpio-cells = <2>;
1246
1247                         interrupt-controller;
1248                         #interrupt-cells = <2>;
1249                 };
1250
1251                 gpio8: gpio8@ff7f0000 {
1252                         compatible = "rockchip,gpio-bank";
1253                         reg = <0xff7f0000 0x100>;
1254                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1255                         clocks = <&cru PCLK_GPIO8>;
1256
1257                         gpio-controller;
1258                         #gpio-cells = <2>;
1259
1260                         interrupt-controller;
1261                         #interrupt-cells = <2>;
1262                 };
1263
1264                 hdmi {
1265                         hdmi_ddc: hdmi-ddc {
1266                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1267                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1268                         };
1269                 };
1270
1271                 pcfg_pull_up: pcfg-pull-up {
1272                         bias-pull-up;
1273                 };
1274
1275                 pcfg_pull_down: pcfg-pull-down {
1276                         bias-pull-down;
1277                 };
1278
1279                 pcfg_pull_none: pcfg-pull-none {
1280                         bias-disable;
1281                 };
1282
1283                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1284                         bias-disable;
1285                         drive-strength = <12>;
1286                 };
1287
1288                 sleep {
1289                         global_pwroff: global-pwroff {
1290                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1291                         };
1292
1293                         ddrio_pwroff: ddrio-pwroff {
1294                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1295                         };
1296
1297                         ddr0_retention: ddr0-retention {
1298                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1299                         };
1300
1301                         ddr1_retention: ddr1-retention {
1302                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1303                         };
1304                 };
1305
1306                 edp {
1307                         edp_hpd: edp-hpd {
1308                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1309                         };
1310                 };
1311
1312                 i2c0 {
1313                         i2c0_xfer: i2c0-xfer {
1314                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1315                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1316                         };
1317                 };
1318
1319                 i2c1 {
1320                         i2c1_xfer: i2c1-xfer {
1321                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1322                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1323                         };
1324                 };
1325
1326                 i2c2 {
1327                         i2c2_xfer: i2c2-xfer {
1328                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1329                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1330                         };
1331                 };
1332
1333                 i2c3 {
1334                         i2c3_xfer: i2c3-xfer {
1335                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1336                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1337                         };
1338                 };
1339
1340                 i2c4 {
1341                         i2c4_xfer: i2c4-xfer {
1342                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1343                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1344                         };
1345                 };
1346
1347                 i2c5 {
1348                         i2c5_xfer: i2c5-xfer {
1349                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1350                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1351                         };
1352                 };
1353
1354                 i2s0 {
1355                         i2s0_bus: i2s0-bus {
1356                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1357                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1358                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1359                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1360                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1361                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1362                         };
1363                 };
1364
1365                 lcdc0 {
1366                         lcdc0_ctl: lcdc0-ctl {
1367                                 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1368                                                 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1369                                                 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1370                                                 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1371                         };
1372                 };
1373
1374                 sdmmc {
1375                         sdmmc_clk: sdmmc-clk {
1376                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1377                         };
1378
1379                         sdmmc_cmd: sdmmc-cmd {
1380                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1381                         };
1382
1383                         sdmmc_cd: sdmcc-cd {
1384                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1385                         };
1386
1387                         sdmmc_bus1: sdmmc-bus1 {
1388                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1389                         };
1390
1391                         sdmmc_bus4: sdmmc-bus4 {
1392                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1393                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1394                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1395                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1396                         };
1397                 };
1398
1399                 sdio0 {
1400                         sdio0_bus1: sdio0-bus1 {
1401                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1402                         };
1403
1404                         sdio0_bus4: sdio0-bus4 {
1405                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1406                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1407                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1408                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1409                         };
1410
1411                         sdio0_cmd: sdio0-cmd {
1412                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1413                         };
1414
1415                         sdio0_clk: sdio0-clk {
1416                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1417                         };
1418
1419                         sdio0_cd: sdio0-cd {
1420                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1421                         };
1422
1423                         sdio0_wp: sdio0-wp {
1424                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1425                         };
1426
1427                         sdio0_pwr: sdio0-pwr {
1428                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1429                         };
1430
1431                         sdio0_bkpwr: sdio0-bkpwr {
1432                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1433                         };
1434
1435                         sdio0_int: sdio0-int {
1436                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1437                         };
1438                 };
1439
1440                 sdio1 {
1441                         sdio1_bus1: sdio1-bus1 {
1442                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1443                         };
1444
1445                         sdio1_bus4: sdio1-bus4 {
1446                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1447                                                 <3 25 4 &pcfg_pull_up>,
1448                                                 <3 26 4 &pcfg_pull_up>,
1449                                                 <3 27 4 &pcfg_pull_up>;
1450                         };
1451
1452                         sdio1_cd: sdio1-cd {
1453                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1454                         };
1455
1456                         sdio1_wp: sdio1-wp {
1457                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1458                         };
1459
1460                         sdio1_bkpwr: sdio1-bkpwr {
1461                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1462                         };
1463
1464                         sdio1_int: sdio1-int {
1465                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1466                         };
1467
1468                         sdio1_cmd: sdio1-cmd {
1469                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1470                         };
1471
1472                         sdio1_clk: sdio1-clk {
1473                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1474                         };
1475
1476                         sdio1_pwr: sdio1-pwr {
1477                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1478                         };
1479                 };
1480
1481                 emmc {
1482                         emmc_clk: emmc-clk {
1483                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1484                         };
1485
1486                         emmc_cmd: emmc-cmd {
1487                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1488                         };
1489
1490                         emmc_pwr: emmc-pwr {
1491                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1492                         };
1493
1494                         emmc_bus1: emmc-bus1 {
1495                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1496                         };
1497
1498                         emmc_bus4: emmc-bus4 {
1499                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1500                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1501                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1502                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1503                         };
1504
1505                         emmc_bus8: emmc-bus8 {
1506                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1507                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1508                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1509                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1510                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1511                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1512                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1513                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1514                         };
1515                 };
1516
1517                 spi0 {
1518                         spi0_clk: spi0-clk {
1519                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1520                         };
1521                         spi0_cs0: spi0-cs0 {
1522                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1523                         };
1524                         spi0_tx: spi0-tx {
1525                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1526                         };
1527                         spi0_rx: spi0-rx {
1528                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1529                         };
1530                         spi0_cs1: spi0-cs1 {
1531                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1532                         };
1533                 };
1534                 spi1 {
1535                         spi1_clk: spi1-clk {
1536                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1537                         };
1538                         spi1_cs0: spi1-cs0 {
1539                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1540                         };
1541                         spi1_rx: spi1-rx {
1542                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1543                         };
1544                         spi1_tx: spi1-tx {
1545                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1546                         };
1547                 };
1548
1549                 spi2 {
1550                         spi2_cs1: spi2-cs1 {
1551                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1552                         };
1553                         spi2_clk: spi2-clk {
1554                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1555                         };
1556                         spi2_cs0: spi2-cs0 {
1557                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1558                         };
1559                         spi2_rx: spi2-rx {
1560                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1561                         };
1562                         spi2_tx: spi2-tx {
1563                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1564                         };
1565                 };
1566
1567                 uart0 {
1568                         uart0_xfer: uart0-xfer {
1569                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1570                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1571                         };
1572
1573                         uart0_cts: uart0-cts {
1574                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1575                         };
1576
1577                         uart0_rts: uart0-rts {
1578                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1579                         };
1580                 };
1581
1582                 uart1 {
1583                         uart1_xfer: uart1-xfer {
1584                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1585                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1586                         };
1587
1588                         uart1_cts: uart1-cts {
1589                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1590                         };
1591
1592                         uart1_rts: uart1-rts {
1593                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1594                         };
1595                 };
1596
1597                 uart2 {
1598                         uart2_xfer: uart2-xfer {
1599                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1600                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1601                         };
1602                         /* no rts / cts for uart2 */
1603                 };
1604
1605                 uart3 {
1606                         uart3_xfer: uart3-xfer {
1607                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1608                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1609                         };
1610
1611                         uart3_cts: uart3-cts {
1612                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1613                         };
1614
1615                         uart3_rts: uart3-rts {
1616                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1617                         };
1618                 };
1619
1620                 uart4 {
1621                         uart4_xfer: uart4-xfer {
1622                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1623                                                 <5 13 3 &pcfg_pull_none>;
1624                         };
1625
1626                         uart4_cts: uart4-cts {
1627                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1628                         };
1629
1630                         uart4_rts: uart4-rts {
1631                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1632                         };
1633                 };
1634
1635                 tsadc {
1636                         otp_gpio: otp-gpio {
1637                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1638                         };
1639
1640                         otp_out: otp-out {
1641                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1642                         };
1643                 };
1644
1645                 pwm0 {
1646                         pwm0_pin: pwm0-pin {
1647                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1648                         };
1649                 };
1650
1651                 pwm1 {
1652                         pwm1_pin: pwm1-pin {
1653                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1654                         };
1655                 };
1656
1657                 pwm2 {
1658                         pwm2_pin: pwm2-pin {
1659                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1660                         };
1661                 };
1662
1663                 pwm3 {
1664                         pwm3_pin: pwm3-pin {
1665                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1666                         };
1667                 };
1668
1669                 gmac {
1670                         rgmii_pins: rgmii-pins {
1671                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1672                                                 <3 31 3 &pcfg_pull_none>,
1673                                                 <3 26 3 &pcfg_pull_none>,
1674                                                 <3 27 3 &pcfg_pull_none>,
1675                                                 <3 28 3 &pcfg_pull_none_12ma>,
1676                                                 <3 29 3 &pcfg_pull_none_12ma>,
1677                                                 <3 24 3 &pcfg_pull_none_12ma>,
1678                                                 <3 25 3 &pcfg_pull_none_12ma>,
1679                                                 <4 0 3 &pcfg_pull_none>,
1680                                                 <4 5 3 &pcfg_pull_none>,
1681                                                 <4 6 3 &pcfg_pull_none>,
1682                                                 <4 9 3 &pcfg_pull_none_12ma>,
1683                                                 <4 4 3 &pcfg_pull_none_12ma>,
1684                                                 <4 1 3 &pcfg_pull_none>,
1685                                                 <4 3 3 &pcfg_pull_none>;
1686                         };
1687
1688                         rmii_pins: rmii-pins {
1689                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1690                                                 <3 31 3 &pcfg_pull_none>,
1691                                                 <3 28 3 &pcfg_pull_none>,
1692                                                 <3 29 3 &pcfg_pull_none>,
1693                                                 <4 0 3 &pcfg_pull_none>,
1694                                                 <4 5 3 &pcfg_pull_none>,
1695                                                 <4 4 3 &pcfg_pull_none>,
1696                                                 <4 1 3 &pcfg_pull_none>,
1697                                                 <4 2 3 &pcfg_pull_none>,
1698                                                 <4 3 3 &pcfg_pull_none>;
1699                         };
1700                 };
1701
1702                 spdif {
1703                         spdif_tx: spdif-tx {
1704                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1705                         };
1706                 };
1707         };
1708 };