arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include "skeleton.dtsi"
  49
  50 / {
  51         compatible = "rockchip,rk3288";
  52
  53         interrupt-parent = <&gic>;
  54
  55         aliases {
  56                 i2c0 = &i2c0;
  57                 i2c1 = &i2c1;
  58                 i2c2 = &i2c2;
  59                 i2c3 = &i2c3;
  60                 i2c4 = &i2c4;
  61                 i2c5 = &i2c5;
  62                 mshc0 = &emmc;
  63                 mshc1 = &sdmmc;
  64                 mshc2 = &sdio0;
  65                 mshc3 = &sdio1;
  66                 serial0 = &uart0;
  67                 serial1 = &uart1;
  68                 serial2 = &uart2;
  69                 serial3 = &uart3;
  70                 serial4 = &uart4;
  71                 spi0 = &spi0;
  72                 spi1 = &spi1;
  73                 spi2 = &spi2;
  74         };
  75
  76         arm-pmu {
  77                 compatible = "arm,cortex-a12-pmu";
  78                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  79                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  80                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  82                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  83         };
  84
  85         cpus {
  86                 #address-cells = <1>;
  87                 #size-cells = <0>;
  88                 enable-method = "rockchip,rk3066-smp";
  89                 rockchip,pmu = <&pmu>;
  90
  91                 cpu0: cpu@500 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a12";
  94                         reg = <0x500>;
  95                         resets = <&cru SRST_CORE0>;
  96                         operating-points = <
  97                                 /* KHz    uV */
  98                                 1608000 1350000
  99                                 1512000 1300000
 100                                 1416000 1200000
 101                                 1200000 1100000
 102                                 1008000 1050000
 103                                  816000 1000000
 104                                  696000  950000
 105                                  600000  900000
 106                                  408000  900000
 107                                  312000  900000
 108                                  216000  900000
 109                                  126000  900000
 110                         >;
 111                         #cooling-cells = <2>; /* min followed by max */
 112                         clock-latency = <40000>;
 113                         clocks = <&cru ARMCLK>;
 114                 };
 115                 cpu1: cpu@501 {
 116                         device_type = "cpu";
 117                         compatible = "arm,cortex-a12";
 118                         reg = <0x501>;
 119                         resets = <&cru SRST_CORE1>;
 120                 };
 121                 cpu2: cpu@502 {
 122                         device_type = "cpu";
 123                         compatible = "arm,cortex-a12";
 124                         reg = <0x502>;
 125                         resets = <&cru SRST_CORE2>;
 126                 };
 127                 cpu3: cpu@503 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a12";
 130                         reg = <0x503>;
 131                         resets = <&cru SRST_CORE3>;
 132                 };
 133         };
 134
 135         amba {
 136                 compatible = "arm,amba-bus";
 137                 #address-cells = <1>;
 138                 #size-cells = <1>;
 139                 ranges;
 140
 141                 dmac_peri: dma-controller@ff250000 {
 142                         compatible = "arm,pl330", "arm,primecell";
 143                         reg = <0xff250000 0x4000>;
 144                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 145                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 146                         #dma-cells = <1>;
 147                         arm,pl330-broken-no-flushp;
 148                         peripherals-req-type-burst;
 149                         clocks = <&cru ACLK_DMAC2>;
 150                         clock-names = "apb_pclk";
 151                 };
 152
 153                 dmac_bus_ns: dma-controller@ff600000 {
 154                         compatible = "arm,pl330", "arm,primecell";
 155                         reg = <0xff600000 0x4000>;
 156                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 157                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 158                         #dma-cells = <1>;
 159                         arm,pl330-broken-no-flushp;
 160                         peripherals-req-type-burst;
 161                         clocks = <&cru ACLK_DMAC1>;
 162                         clock-names = "apb_pclk";
 163                         status = "disabled";
 164                 };
 165
 166                 dmac_bus_s: dma-controller@ffb20000 {
 167                         compatible = "arm,pl330", "arm,primecell";
 168                         reg = <0xffb20000 0x4000>;
 169                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 170                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 171                         #dma-cells = <1>;
 172                         arm,pl330-broken-no-flushp;
 173                         peripherals-req-type-burst;
 174                         clocks = <&cru ACLK_DMAC1>;
 175                         clock-names = "apb_pclk";
 176                 };
 177         };
 178
 179         reserved-memory {
 180                 #address-cells = <1>;
 181                 #size-cells = <1>;
 182                 ranges;
 183
 184                 /*
 185                  * The rk3288 cannot use the memory area above 0xfe000000
 186                  * for dma operations for some reason. While there is
 187                  * probably a better solution available somewhere, we
 188                  * haven't found it yet and while devices with 2GB of ram
 189                  * are not affected, this issue prevents 4GB from booting.
 190                  * So to make these devices at least bootable, block
 191                  * this area for the time being until the real solution
 192                  * is found.
 193                  */
 194                 dma-unusable@fe000000 {
 195                         reg = <0xfe000000 0x1000000>;
 196                 };
 197         };
 198
 199         xin24m: oscillator {
 200                 compatible = "fixed-clock";
 201                 clock-frequency = <24000000>;
 202                 clock-output-names = "xin24m";
 203                 #clock-cells = <0>;
 204         };
 205
 206         edp_phy: edp-phy {
 207                 compatible = "rockchip,rk3288-dp-phy";
 208                 clocks = <&cru SCLK_EDP_24M>;
 209                 clock-names = "24m";
 210                 rockchip,grf = <&grf>;
 211                 #phy-cells = <0>;
 212                 status = "disabled";
 213         };
 214
 215         timer {
 216                 compatible = "arm,armv7-timer";
 217                 arm,cpu-registers-not-fw-configured;
 218                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 219                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 220                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 221                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 222                 clock-frequency = <24000000>;
 223         };
 224
 225         timer: timer@ff810000 {
 226                 compatible = "rockchip,rk3288-timer";
 227                 reg = <0xff810000 0x20>;
 228                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 229                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 230                 clock-names = "timer", "pclk";
 231         };
 232
 233         display-subsystem {
 234                 compatible = "rockchip,display-subsystem";
 235                 ports = <&vopl_out>, <&vopb_out>;
 236         };
 237
 238         sdmmc: dwmmc@ff0c0000 {
 239                 compatible = "rockchip,rk3288-dw-mshc";
 240                 clock-freq-min-max = <400000 150000000>;
 241                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 242                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 243                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 244                 fifo-depth = <0x100>;
 245                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 246                 reg = <0xff0c0000 0x4000>;
 247                 status = "disabled";
 248         };
 249
 250         sdio0: dwmmc@ff0d0000 {
 251                 compatible = "rockchip,rk3288-dw-mshc";
 252                 clock-freq-min-max = <400000 150000000>;
 253                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 254                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 255                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 256                 fifo-depth = <0x100>;
 257                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 258                 reg = <0xff0d0000 0x4000>;
 259                 status = "disabled";
 260         };
 261
 262         sdio1: dwmmc@ff0e0000 {
 263                 compatible = "rockchip,rk3288-dw-mshc";
 264                 clock-freq-min-max = <400000 150000000>;
 265                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 266                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 267                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 268                 fifo-depth = <0x100>;
 269                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 270                 reg = <0xff0e0000 0x4000>;
 271                 status = "disabled";
 272         };
 273
 274         emmc: dwmmc@ff0f0000 {
 275                 compatible = "rockchip,rk3288-dw-mshc";
 276                 clock-freq-min-max = <400000 150000000>;
 277                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 278                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 279                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 280                 fifo-depth = <0x100>;
 281                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 282                 reg = <0xff0f0000 0x4000>;
 283                 status = "disabled";
 284                 supports-emmc;
 285         };
 286
 287         saradc: saradc@ff100000 {
 288                 compatible = "rockchip,saradc";
 289                 reg = <0xff100000 0x100>;
 290                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 291                 #io-channel-cells = <1>;
 292                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 293                 clock-names = "saradc", "apb_pclk";
 294                 status = "disabled";
 295         };
 296
 297         spi0: spi@ff110000 {
 298                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 299                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 300                 clock-names = "spiclk", "apb_pclk";
 301                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 302                 dma-names = "tx", "rx";
 303                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 304                 pinctrl-names = "default";
 305                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 306                 reg = <0xff110000 0x1000>;
 307                 #address-cells = <1>;
 308                 #size-cells = <0>;
 309                 status = "disabled";
 310         };
 311
 312         spi1: spi@ff120000 {
 313                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 314                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 315                 clock-names = "spiclk", "apb_pclk";
 316                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 317                 dma-names = "tx", "rx";
 318                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 319                 pinctrl-names = "default";
 320                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 321                 reg = <0xff120000 0x1000>;
 322                 #address-cells = <1>;
 323                 #size-cells = <0>;
 324                 status = "disabled";
 325         };
 326
 327         spi2: spi@ff130000 {
 328                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 329                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 330                 clock-names = "spiclk", "apb_pclk";
 331                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 332                 dma-names = "tx", "rx";
 333                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 334                 pinctrl-names = "default";
 335                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 336                 reg = <0xff130000 0x1000>;
 337                 #address-cells = <1>;
 338                 #size-cells = <0>;
 339                 status = "disabled";
 340         };
 341
 342         i2c1: i2c@ff140000 {
 343                 compatible = "rockchip,rk3288-i2c";
 344                 reg = <0xff140000 0x1000>;
 345                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 346                 #address-cells = <1>;
 347                 #size-cells = <0>;
 348                 clock-names = "i2c";
 349                 clocks = <&cru PCLK_I2C1>;
 350                 pinctrl-names = "default";
 351                 pinctrl-0 = <&i2c1_xfer>;
 352                 status = "disabled";
 353         };
 354
 355         i2c3: i2c@ff150000 {
 356                 compatible = "rockchip,rk3288-i2c";
 357                 reg = <0xff150000 0x1000>;
 358                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 359                 #address-cells = <1>;
 360                 #size-cells = <0>;
 361                 clock-names = "i2c";
 362                 clocks = <&cru PCLK_I2C3>;
 363                 pinctrl-names = "default";
 364                 pinctrl-0 = <&i2c3_xfer>;
 365                 status = "disabled";
 366         };
 367
 368         i2c4: i2c@ff160000 {
 369                 compatible = "rockchip,rk3288-i2c";
 370                 reg = <0xff160000 0x1000>;
 371                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 372                 #address-cells = <1>;
 373                 #size-cells = <0>;
 374                 clock-names = "i2c";
 375                 clocks = <&cru PCLK_I2C4>;
 376                 pinctrl-names = "default";
 377                 pinctrl-0 = <&i2c4_xfer>;
 378                 status = "disabled";
 379         };
 380
 381         i2c5: i2c@ff170000 {
 382                 compatible = "rockchip,rk3288-i2c";
 383                 reg = <0xff170000 0x1000>;
 384                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 385                 #address-cells = <1>;
 386                 #size-cells = <0>;
 387                 clock-names = "i2c";
 388                 clocks = <&cru PCLK_I2C5>;
 389                 pinctrl-names = "default";
 390                 pinctrl-0 = <&i2c5_xfer>;
 391                 status = "disabled";
 392         };
 393
 394         uart0: serial@ff180000 {
 395                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 396                 reg = <0xff180000 0x100>;
 397                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 398                 reg-shift = <2>;
 399                 reg-io-width = <4>;
 400                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 401                 clock-names = "baudclk", "apb_pclk";
 402                 pinctrl-names = "default";
 403                 pinctrl-0 = <&uart0_xfer>;
 404                 status = "disabled";
 405         };
 406
 407         uart1: serial@ff190000 {
 408                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 409                 reg = <0xff190000 0x100>;
 410                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 411                 reg-shift = <2>;
 412                 reg-io-width = <4>;
 413                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 414                 clock-names = "baudclk", "apb_pclk";
 415                 pinctrl-names = "default";
 416                 pinctrl-0 = <&uart1_xfer>;
 417                 status = "disabled";
 418         };
 419
 420         uart2: serial@ff690000 {
 421                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 422                 reg = <0xff690000 0x100>;
 423                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 424                 reg-shift = <2>;
 425                 reg-io-width = <4>;
 426                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 427                 clock-names = "baudclk", "apb_pclk";
 428                 pinctrl-names = "default";
 429                 pinctrl-0 = <&uart2_xfer>;
 430                 status = "disabled";
 431         };
 432
 433         uart3: serial@ff1b0000 {
 434                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 435                 reg = <0xff1b0000 0x100>;
 436                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 437                 reg-shift = <2>;
 438                 reg-io-width = <4>;
 439                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 440                 clock-names = "baudclk", "apb_pclk";
 441                 pinctrl-names = "default";
 442                 pinctrl-0 = <&uart3_xfer>;
 443                 status = "disabled";
 444         };
 445
 446         uart4: serial@ff1c0000 {
 447                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 448                 reg = <0xff1c0000 0x100>;
 449                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 450                 reg-shift = <2>;
 451                 reg-io-width = <4>;
 452                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 453                 clock-names = "baudclk", "apb_pclk";
 454                 pinctrl-names = "default";
 455                 pinctrl-0 = <&uart4_xfer>;
 456                 status = "disabled";
 457         };
 458
 459         thermal-zones {
 460                 #include "rk3288-thermal.dtsi"
 461         };
 462
 463         tsadc: tsadc@ff280000 {
 464                 compatible = "rockchip,rk3288-tsadc";
 465                 reg = <0xff280000 0x100>;
 466                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 467                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 468                 clock-names = "tsadc", "apb_pclk";
 469                 resets = <&cru SRST_TSADC>;
 470                 reset-names = "tsadc-apb";
 471                 pinctrl-names = "init", "default", "sleep";
 472                 pinctrl-0 = <&otp_gpio>;
 473                 pinctrl-1 = <&otp_out>;
 474                 pinctrl-2 = <&otp_gpio>;
 475                 #thermal-sensor-cells = <1>;
 476                 rockchip,hw-tshut-temp = <95000>;
 477                 status = "disabled";
 478         };
 479
 480         gmac: ethernet@ff290000 {
 481                 compatible = "rockchip,rk3288-gmac";
 482                 reg = <0xff290000 0x10000>;
 483                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 484                 interrupt-names = "macirq";
 485                 rockchip,grf = <&grf>;
 486                 clocks = <&cru SCLK_MAC>,
 487                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 488                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 489                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 490                 clock-names = "stmmaceth",
 491                         "mac_clk_rx", "mac_clk_tx",
 492                         "clk_mac_ref", "clk_mac_refout",
 493                         "aclk_mac", "pclk_mac";
 494                 resets = <&cru SRST_MAC>;
 495                 reset-names = "stmmaceth";
 496                 status = "disabled";
 497         };
 498
 499         usb_host0_ehci: usb@ff500000 {
 500                 compatible = "generic-ehci";
 501                 reg = <0xff500000 0x100>;
 502                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 503                 clocks = <&cru HCLK_USBHOST0>;
 504                 clock-names = "usbhost";
 505                 phys = <&usbphy1>;
 506                 phy-names = "usb";
 507                 status = "disabled";
 508         };
 509
 510         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 511
 512         usb_host1: usb@ff540000 {
 513                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 514                                 "snps,dwc2";
 515                 reg = <0xff540000 0x40000>;
 516                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 517                 clocks = <&cru HCLK_USBHOST1>;
 518                 clock-names = "otg";
 519                 dr_mode = "host";
 520                 phys = <&usbphy2>;
 521                 phy-names = "usb2-phy";
 522                 status = "disabled";
 523         };
 524
 525         usb_otg: usb@ff580000 {
 526                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 527                                 "snps,dwc2";
 528                 reg = <0xff580000 0x40000>;
 529                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 530                 clocks = <&cru HCLK_OTG0>;
 531                 clock-names = "otg";
 532                 dr_mode = "otg";
 533                 g-np-tx-fifo-size = <16>;
 534                 g-rx-fifo-size = <275>;
 535                 g-tx-fifo-size = <256 128 128 64 64 32>;
 536                 g-use-dma;
 537                 phys = <&usbphy0>;
 538                 phy-names = "usb2-phy";
 539                 status = "disabled";
 540         };
 541
 542         usb_hsic: usb@ff5c0000 {
 543                 compatible = "generic-ehci";
 544                 reg = <0xff5c0000 0x100>;
 545                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 546                 clocks = <&cru HCLK_HSIC>;
 547                 clock-names = "usbhost";
 548                 status = "disabled";
 549         };
 550
 551         i2c0: i2c@ff650000 {
 552                 compatible = "rockchip,rk3288-i2c";
 553                 reg = <0xff650000 0x1000>;
 554                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 555                 #address-cells = <1>;
 556                 #size-cells = <0>;
 557                 clock-names = "i2c";
 558                 clocks = <&cru PCLK_I2C0>;
 559                 pinctrl-names = "default";
 560                 pinctrl-0 = <&i2c0_xfer>;
 561                 status = "disabled";
 562         };
 563
 564         i2c2: i2c@ff660000 {
 565                 compatible = "rockchip,rk3288-i2c";
 566                 reg = <0xff660000 0x1000>;
 567                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 568                 #address-cells = <1>;
 569                 #size-cells = <0>;
 570                 clock-names = "i2c";
 571                 clocks = <&cru PCLK_I2C2>;
 572                 pinctrl-names = "default";
 573                 pinctrl-0 = <&i2c2_xfer>;
 574                 status = "disabled";
 575         };
 576
 577         pwm0: pwm@ff680000 {
 578                 compatible = "rockchip,rk3288-pwm";
 579                 reg = <0xff680000 0x10>;
 580                 #pwm-cells = <3>;
 581                 pinctrl-names = "default";
 582                 pinctrl-0 = <&pwm0_pin>;
 583                 clocks = <&cru PCLK_PWM>;
 584                 clock-names = "pwm";
 585                 status = "disabled";
 586         };
 587
 588         pwm1: pwm@ff680010 {
 589                 compatible = "rockchip,rk3288-pwm";
 590                 reg = <0xff680010 0x10>;
 591                 #pwm-cells = <3>;
 592                 pinctrl-names = "default";
 593                 pinctrl-0 = <&pwm1_pin>;
 594                 clocks = <&cru PCLK_PWM>;
 595                 clock-names = "pwm";
 596                 status = "disabled";
 597         };
 598
 599         pwm2: pwm@ff680020 {
 600                 compatible = "rockchip,rk3288-pwm";
 601                 reg = <0xff680020 0x10>;
 602                 #pwm-cells = <3>;
 603                 pinctrl-names = "default";
 604                 pinctrl-0 = <&pwm2_pin>;
 605                 clocks = <&cru PCLK_PWM>;
 606                 clock-names = "pwm";
 607                 status = "disabled";
 608         };
 609
 610         pwm3: pwm@ff680030 {
 611                 compatible = "rockchip,rk3288-pwm";
 612                 reg = <0xff680030 0x10>;
 613                 #pwm-cells = <2>;
 614                 pinctrl-names = "default";
 615                 pinctrl-0 = <&pwm3_pin>;
 616                 clocks = <&cru PCLK_PWM>;
 617                 clock-names = "pwm";
 618                 status = "disabled";
 619         };
 620
 621         bus_intmem@ff700000 {
 622                 compatible = "mmio-sram";
 623                 reg = <0xff700000 0x18000>;
 624                 #address-cells = <1>;
 625                 #size-cells = <1>;
 626                 ranges = <0 0xff700000 0x18000>;
 627                 smp-sram@0 {
 628                         compatible = "rockchip,rk3066-smp-sram";
 629                         reg = <0x00 0x10>;
 630                 };
 631         };
 632
 633         sram@ff720000 {
 634                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 635                 reg = <0xff720000 0x1000>;
 636         };
 637
 638         pmu: power-management@ff730000 {
 639                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 640                 reg = <0xff730000 0x100>;
 641
 642                 power: power-controller {
 643                         compatible = "rockchip,rk3288-power-controller";
 644                         #power-domain-cells = <1>;
 645                         #address-cells = <1>;
 646                         #size-cells = <0>;
 647
 648                         /*
 649                          * Note: Although SCLK_* are the working clocks
 650                          * of device without including on the NOC, needed for
 651                          * synchronous reset.
 652                          *
 653                          * The clocks on the which NOC:
 654                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 655                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 656                          * ACLK_RGA is on ACLK_RGA_NIU.
 657                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 658                          *
 659                          * Which clock are device clocks:
 660                          *      clocks          devices
 661                          *      *_IEP           IEP:Image Enhancement Processor
 662                          *      *_ISP           ISP:Image Signal Processing
 663                          *      *_VIP           VIP:Video Input Processor
 664                          *      *_VOP*          VOP:Visual Output Processor
 665                          *      *_RGA           RGA
 666                          *      *_EDP*          EDP
 667                          *      *_LVDS_*        LVDS
 668                          *      *_HDMI          HDMI
 669                          *      *_MIPI_*        MIPI
 670                          */
 671                         pd_vio {
 672                                 reg = <RK3288_PD_VIO>;
 673                                 clocks = <&cru ACLK_IEP>,
 674                                          <&cru ACLK_ISP>,
 675                                          <&cru ACLK_RGA>,
 676                                          <&cru ACLK_VIP>,
 677                                          <&cru ACLK_VOP0>,
 678                                          <&cru ACLK_VOP1>,
 679                                          <&cru DCLK_VOP0>,
 680                                          <&cru DCLK_VOP1>,
 681                                          <&cru HCLK_IEP>,
 682                                          <&cru HCLK_ISP>,
 683                                          <&cru HCLK_RGA>,
 684                                          <&cru HCLK_VIP>,
 685                                          <&cru HCLK_VOP0>,
 686                                          <&cru HCLK_VOP1>,
 687                                          <&cru PCLK_EDP_CTRL>,
 688                                          <&cru PCLK_HDMI_CTRL>,
 689                                          <&cru PCLK_LVDS_PHY>,
 690                                          <&cru PCLK_MIPI_CSI>,
 691                                          <&cru PCLK_MIPI_DSI0>,
 692                                          <&cru PCLK_MIPI_DSI1>,
 693                                          <&cru SCLK_EDP_24M>,
 694                                          <&cru SCLK_EDP>,
 695                                          <&cru SCLK_ISP_JPE>,
 696                                          <&cru SCLK_ISP>,
 697                                          <&cru SCLK_RGA>;
 698                         };
 699
 700                         /*
 701                          * Note: The following 3 are HEVC(H.265) clocks,
 702                          * and on the ACLK_HEVC_NIU (NOC).
 703                          */
 704                         pd_hevc {
 705                                 reg = <RK3288_PD_HEVC>;
 706                                 clocks = <&cru ACLK_HEVC>,
 707                                          <&cru SCLK_HEVC_CABAC>,
 708                                          <&cru SCLK_HEVC_CORE>;
 709                         };
 710
 711                         /*
 712                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 713                          * (video endecoder & decoder) clocks that on the
 714                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 715                          */
 716                         pd_video {
 717                                 reg = <RK3288_PD_VIDEO>;
 718                                 clocks = <&cru ACLK_VCODEC>,
 719                                          <&cru HCLK_VCODEC>;
 720                         };
 721
 722                         /*
 723                          * Note: ACLK_GPU is the GPU clock,
 724                          * and on the ACLK_GPU_NIU (NOC).
 725                          */
 726                         pd_gpu {
 727                                 reg = <RK3288_PD_GPU>;
 728                                 clocks = <&cru ACLK_GPU>;
 729                         };
 730                 };
 731         };
 732
 733         sgrf: syscon@ff740000 {
 734                 compatible = "rockchip,rk3288-sgrf", "syscon";
 735                 reg = <0xff740000 0x1000>;
 736         };
 737
 738         cru: clock-controller@ff760000 {
 739                 compatible = "rockchip,rk3288-cru";
 740                 reg = <0xff760000 0x1000>;
 741                 rockchip,grf = <&grf>;
 742                 #clock-cells = <1>;
 743                 #reset-cells = <1>;
 744                 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
 745                                   <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 746                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 747                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 748                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 749                                   <&cru PCLK_PERI>;
 750                 assigned-clock-rates = <0>, <0>,
 751                                        <594000000>, <400000000>,
 752                                        <500000000>, <300000000>,
 753                                        <150000000>, <75000000>,
 754                                        <300000000>, <150000000>,
 755                                        <75000000>;
 756                 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
 757         };
 758
 759         grf: syscon@ff770000 {
 760                 compatible = "rockchip,rk3288-grf", "syscon";
 761                 reg = <0xff770000 0x1000>;
 762         };
 763
 764         wdt: watchdog@ff800000 {
 765                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 766                 reg = <0xff800000 0x100>;
 767                 clocks = <&cru PCLK_WDT>;
 768                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 769                 status = "disabled";
 770         };
 771
 772         spdif: sound@ff88b0000 {
 773                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 774                 reg = <0xff8b0000 0x10000>;
 775                 #sound-dai-cells = <0>;
 776                 clock-names = "hclk", "mclk";
 777                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 778                 dmas = <&dmac_bus_s 3>;
 779                 dma-names = "tx";
 780                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 781                 pinctrl-names = "default";
 782                 pinctrl-0 = <&spdif_tx>;
 783                 rockchip,grf = <&grf>;
 784                 status = "disabled";
 785         };
 786
 787         i2s: i2s@ff890000 {
 788                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 789                 reg = <0xff890000 0x10000>;
 790                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 791                 #address-cells = <1>;
 792                 #size-cells = <0>;
 793                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 794                 dma-names = "tx", "rx";
 795                 clock-names = "i2s_hclk", "i2s_clk";
 796                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 797                 pinctrl-names = "default";
 798                 pinctrl-0 = <&i2s0_bus>;
 799                 status = "disabled";
 800         };
 801
 802         vopb: vop@ff930000 {
 803                 compatible = "rockchip,rk3288-vop";
 804                 reg = <0xff930000 0x19c>;
 805                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 806                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 807                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 808                 power-domains = <&power RK3288_PD_VIO>;
 809                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 810                 reset-names = "axi", "ahb", "dclk";
 811                 iommus = <&vopb_mmu>;
 812                 status = "disabled";
 813
 814                 vopb_out: port {
 815                         #address-cells = <1>;
 816                         #size-cells = <0>;
 817
 818                         vopb_out_hdmi: endpoint@0 {
 819                                 reg = <0>;
 820                                 remote-endpoint = <&hdmi_in_vopb>;
 821                         };
 822
 823                         vopb_out_edp: endpoint@1 {
 824                                 reg = <1>;
 825                                 remote-endpoint = <&edp_in_vopb>;
 826                         };
 827
 828                         vopb_out_mipi: endpoint@2 {
 829                                 reg = <2>;
 830                                 remote-endpoint = <&mipi_in_vopb>;
 831                         };
 832
 833                         vopb_out_lvds: endpoint@3 {
 834                                 reg = <3>;
 835                                 remote-endpoint = <&lvds_in_vopb>;
 836                         };
 837                 };
 838         };
 839
 840         vopb_mmu: iommu@ff930300 {
 841                 compatible = "rockchip,iommu";
 842                 reg = <0xff930300 0x100>;
 843                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 844                 interrupt-names = "vopb_mmu";
 845                 power-domains = <&power RK3288_PD_VIO>;
 846                 #iommu-cells = <0>;
 847                 status = "disabled";
 848         };
 849
 850         vopl: vop@ff940000 {
 851                 compatible = "rockchip,rk3288-vop";
 852                 reg = <0xff940000 0x19c>;
 853                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 854                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 855                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 856                 power-domains = <&power RK3288_PD_VIO>;
 857                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 858                 reset-names = "axi", "ahb", "dclk";
 859                 iommus = <&vopl_mmu>;
 860                 status = "disabled";
 861
 862                 vopl_out: port {
 863                         #address-cells = <1>;
 864                         #size-cells = <0>;
 865
 866                         vopl_out_hdmi: endpoint@0 {
 867                                 reg = <0>;
 868                                 remote-endpoint = <&hdmi_in_vopl>;
 869                         };
 870
 871                         vopl_out_edp: endpoint@1 {
 872                                 reg = <1>;
 873                                 remote-endpoint = <&edp_in_vopl>;
 874                         };
 875
 876                         vopl_out_mipi: endpoint@2 {
 877                                 reg = <2>;
 878                                 remote-endpoint = <&mipi_in_vopl>;
 879                         };
 880
 881                         vopl_out_lvds: endpoint@3 {
 882                                 reg = <3>;
 883                                 remote-endpoint = <&lvds_in_vopl>;
 884                         };
 885
 886                 };
 887         };
 888
 889         vopl_mmu: iommu@ff940300 {
 890                 compatible = "rockchip,iommu";
 891                 reg = <0xff940300 0x100>;
 892                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 893                 interrupt-names = "vopl_mmu";
 894                 power-domains = <&power RK3288_PD_VIO>;
 895                 #iommu-cells = <0>;
 896                 status = "disabled";
 897         };
 898
 899         mipi_dsi: mipi@ff960000 {
 900                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
 901                 reg = <0xff960000 0x4000>;
 902                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 903                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
 904                 clock-names = "ref", "pclk";
 905                 rockchip,grf = <&grf>;
 906                 #address-cells = <1>;
 907                 #size-cells = <0>;
 908                 status = "disabled";
 909
 910                 ports {
 911                         #address-cells = <1>;
 912                         #size-cells = <0>;
 913                         reg = <1>;
 914
 915                         mipi_in: port {
 916                                 #address-cells = <1>;
 917                                 #size-cells = <0>;
 918                                 mipi_in_vopb: endpoint@0 {
 919                                         reg = <0>;
 920                                         remote-endpoint = <&vopb_out_mipi>;
 921                                 };
 922                                 mipi_in_vopl: endpoint@1 {
 923                                         reg = <1>;
 924                                         remote-endpoint = <&vopl_out_mipi>;
 925                                 };
 926                         };
 927                 };
 928         };
 929
 930         edp: dp@ff970000 {
 931                 compatible = "rockchip,rk3288-dp";
 932                 reg = <0xff970000 0x4000>;
 933                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 934                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
 935                 clock-names = "dp", "pclk";
 936                 phys = <&edp_phy>;
 937                 phy-names = "dp";
 938                 resets = <&cru SRST_EDP>;
 939                 reset-names = "dp";
 940                 rockchip,grf = <&grf>;
 941                 status = "disabled";
 942
 943                 ports {
 944                         #address-cells = <1>;
 945                         #size-cells = <0>;
 946                         edp_in: port@0 {
 947                                 reg = <0>;
 948                                 #address-cells = <1>;
 949                                 #size-cells = <0>;
 950                                 edp_in_vopb: endpoint@0 {
 951                                         reg = <0>;
 952                                         remote-endpoint = <&vopb_out_edp>;
 953                                 };
 954                                 edp_in_vopl: endpoint@1 {
 955                                         reg = <1>;
 956                                         remote-endpoint = <&vopl_out_edp>;
 957                                 };
 958                         };
 959                 };
 960         };
 961
 962         lvds: lvds@ff96c000 {
 963                 compatible = "rockchip,rk3288-lvds";
 964                 reg = <0xff96c000 0x4000>;
 965                 clocks = <&cru PCLK_LVDS_PHY>;
 966                 clock-names = "pclk_lvds";
 967                 pinctrl-names = "default";
 968                 pinctrl-0 = <&lcdc0_ctl>;
 969                 power-domains = <&power RK3288_PD_VIO>;
 970                 rockchip,grf = <&grf>;
 971                 status = "disabled";
 972
 973                 ports {
 974                         #address-cells = <1>;
 975                         #size-cells = <0>;
 976
 977                         lvds_in: port@0 {
 978                                 reg = <0>;
 979
 980                                 #address-cells = <1>;
 981                                 #size-cells = <0>;
 982
 983                                 lvds_in_vopb: endpoint@0 {
 984                                         reg = <0>;
 985                                         remote-endpoint = <&vopb_out_lvds>;
 986                                 };
 987                                 lvds_in_vopl: endpoint@1 {
 988                                         reg = <1>;
 989                                         remote-endpoint = <&vopl_out_lvds>;
 990                                 };
 991                         };
 992                 };
 993         };
 994
 995         hdmi: hdmi@ff980000 {
 996                 compatible = "rockchip,rk3288-dw-hdmi";
 997                 reg = <0xff980000 0x20000>;
 998                 reg-io-width = <4>;
 999                 rockchip,grf = <&grf>;
1000                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1001                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1002                 clock-names = "iahb", "isfr";
1003                 power-domains = <&power RK3288_PD_VIO>;
1004                 status = "disabled";
1005
1006                 ports {
1007                         hdmi_in: port {
1008                                 #address-cells = <1>;
1009                                 #size-cells = <0>;
1010                                 hdmi_in_vopb: endpoint@0 {
1011                                         reg = <0>;
1012                                         remote-endpoint = <&vopb_out_hdmi>;
1013                                 };
1014                                 hdmi_in_vopl: endpoint@1 {
1015                                         reg = <1>;
1016                                         remote-endpoint = <&vopl_out_hdmi>;
1017                                 };
1018                         };
1019                 };
1020         };
1021
1022         gpu: gpu@ffa30000 {
1023                 compatible = "arm,malit764",
1024                              "arm,malit76x",
1025                              "arm,malit7xx",
1026                              "arm,mali-midgard";
1027                 reg = <0xffa30000 0x10000>;
1028                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1029                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1030                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1031                 interrupt-names = "JOB", "MMU", "GPU";
1032                 clocks = <&cru ACLK_GPU>;
1033                 clock-names = "clk_mali";
1034                 operating-points = <
1035                         /* KHz uV */
1036                         600000 1250000
1037                         /* 500000 1200000 - See crosbug.com/p/33857 */
1038                         400000 1100000
1039                         300000 1000000
1040                         200000 950000
1041                         100000 950000
1042                 >;
1043                 #cooling-cells = <2>; /* min followed by max */
1044                 power-domains = <&power RK3288_PD_GPU>;
1045                 status = "disabled";
1046         };
1047
1048         vpu: video-codec@ff9a0000 {
1049                 compatible = "rockchip,rk3288-vpu";
1050                 reg = <0xff9a0000 0x800>;
1051                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1052                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1053                 interrupt-names = "vepu", "vdpu";
1054                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1055                 clock-names = "aclk", "hclk";
1056                 power-domains = <&power RK3288_PD_VIDEO>;
1057                 iommus = <&vpu_mmu>;
1058                 status = "disabled";
1059         };
1060
1061         vpu_mmu: iommu@ff9a0800 {
1062                 compatible = "rockchip,iommu";
1063                 reg = <0xff9a0800 0x100>;
1064                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1065                 interrupt-names = "vpu_mmu";
1066                 power-domains = <&power RK3288_PD_VIDEO>;
1067                 #iommu-cells = <0>;
1068         };
1069
1070         gic: interrupt-controller@ffc01000 {
1071                 compatible = "arm,gic-400";
1072                 interrupt-controller;
1073                 #interrupt-cells = <3>;
1074                 #address-cells = <0>;
1075
1076                 reg = <0xffc01000 0x1000>,
1077                       <0xffc02000 0x1000>,
1078                       <0xffc04000 0x2000>,
1079                       <0xffc06000 0x2000>;
1080                 interrupts = <GIC_PPI 9 0xf04>;
1081         };
1082
1083         usbphy: phy {
1084                 compatible = "rockchip,rk3288-usb-phy";
1085                 rockchip,grf = <&grf>;
1086                 #address-cells = <1>;
1087                 #size-cells = <0>;
1088                 status = "disabled";
1089
1090                 usbphy0: usb-phy0 {
1091                         #phy-cells = <0>;
1092                         reg = <0x320>;
1093                         clocks = <&cru SCLK_OTGPHY0>;
1094                         clock-names = "phyclk";
1095                 };
1096
1097                 usbphy1: usb-phy1 {
1098                         #phy-cells = <0>;
1099                         reg = <0x334>;
1100                         clocks = <&cru SCLK_OTGPHY1>;
1101                         clock-names = "phyclk";
1102                 };
1103
1104                 usbphy2: usb-phy2 {
1105                         #phy-cells = <0>;
1106                         reg = <0x348>;
1107                         clocks = <&cru SCLK_OTGPHY2>;
1108                         clock-names = "phyclk";
1109                 };
1110         };
1111
1112         pinctrl: pinctrl {
1113                 compatible = "rockchip,rk3288-pinctrl";
1114                 rockchip,grf = <&grf>;
1115                 rockchip,pmu = <&pmu>;
1116                 #address-cells = <1>;
1117                 #size-cells = <1>;
1118                 ranges;
1119
1120                 gpio0: gpio0@ff750000 {
1121                         compatible = "rockchip,gpio-bank";
1122                         reg =   <0xff750000 0x100>;
1123                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1124                         clocks = <&cru PCLK_GPIO0>;
1125
1126                         gpio-controller;
1127                         #gpio-cells = <2>;
1128
1129                         interrupt-controller;
1130                         #interrupt-cells = <2>;
1131                 };
1132
1133                 gpio1: gpio1@ff780000 {
1134                         compatible = "rockchip,gpio-bank";
1135                         reg = <0xff780000 0x100>;
1136                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1137                         clocks = <&cru PCLK_GPIO1>;
1138
1139                         gpio-controller;
1140                         #gpio-cells = <2>;
1141
1142                         interrupt-controller;
1143                         #interrupt-cells = <2>;
1144                 };
1145
1146                 gpio2: gpio2@ff790000 {
1147                         compatible = "rockchip,gpio-bank";
1148                         reg = <0xff790000 0x100>;
1149                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1150                         clocks = <&cru PCLK_GPIO2>;
1151
1152                         gpio-controller;
1153                         #gpio-cells = <2>;
1154
1155                         interrupt-controller;
1156                         #interrupt-cells = <2>;
1157                 };
1158
1159                 gpio3: gpio3@ff7a0000 {
1160                         compatible = "rockchip,gpio-bank";
1161                         reg = <0xff7a0000 0x100>;
1162                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1163                         clocks = <&cru PCLK_GPIO3>;
1164
1165                         gpio-controller;
1166                         #gpio-cells = <2>;
1167
1168                         interrupt-controller;
1169                         #interrupt-cells = <2>;
1170                 };
1171
1172                 gpio4: gpio4@ff7b0000 {
1173                         compatible = "rockchip,gpio-bank";
1174                         reg = <0xff7b0000 0x100>;
1175                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1176                         clocks = <&cru PCLK_GPIO4>;
1177
1178                         gpio-controller;
1179                         #gpio-cells = <2>;
1180
1181                         interrupt-controller;
1182                         #interrupt-cells = <2>;
1183                 };
1184
1185                 gpio5: gpio5@ff7c0000 {
1186                         compatible = "rockchip,gpio-bank";
1187                         reg = <0xff7c0000 0x100>;
1188                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1189                         clocks = <&cru PCLK_GPIO5>;
1190
1191                         gpio-controller;
1192                         #gpio-cells = <2>;
1193
1194                         interrupt-controller;
1195                         #interrupt-cells = <2>;
1196                 };
1197
1198                 gpio6: gpio6@ff7d0000 {
1199                         compatible = "rockchip,gpio-bank";
1200                         reg = <0xff7d0000 0x100>;
1201                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1202                         clocks = <&cru PCLK_GPIO6>;
1203
1204                         gpio-controller;
1205                         #gpio-cells = <2>;
1206
1207                         interrupt-controller;
1208                         #interrupt-cells = <2>;
1209                 };
1210
1211                 gpio7: gpio7@ff7e0000 {
1212                         compatible = "rockchip,gpio-bank";
1213                         reg = <0xff7e0000 0x100>;
1214                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1215                         clocks = <&cru PCLK_GPIO7>;
1216
1217                         gpio-controller;
1218                         #gpio-cells = <2>;
1219
1220                         interrupt-controller;
1221                         #interrupt-cells = <2>;
1222                 };
1223
1224                 gpio8: gpio8@ff7f0000 {
1225                         compatible = "rockchip,gpio-bank";
1226                         reg = <0xff7f0000 0x100>;
1227                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1228                         clocks = <&cru PCLK_GPIO8>;
1229
1230                         gpio-controller;
1231                         #gpio-cells = <2>;
1232
1233                         interrupt-controller;
1234                         #interrupt-cells = <2>;
1235                 };
1236
1237                 hdmi {
1238                         hdmi_ddc: hdmi-ddc {
1239                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1240                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1241                         };
1242                 };
1243
1244                 pcfg_pull_up: pcfg-pull-up {
1245                         bias-pull-up;
1246                 };
1247
1248                 pcfg_pull_down: pcfg-pull-down {
1249                         bias-pull-down;
1250                 };
1251
1252                 pcfg_pull_none: pcfg-pull-none {
1253                         bias-disable;
1254                 };
1255
1256                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1257                         bias-disable;
1258                         drive-strength = <12>;
1259                 };
1260
1261                 sleep {
1262                         global_pwroff: global-pwroff {
1263                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1264                         };
1265
1266                         ddrio_pwroff: ddrio-pwroff {
1267                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1268                         };
1269
1270                         ddr0_retention: ddr0-retention {
1271                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1272                         };
1273
1274                         ddr1_retention: ddr1-retention {
1275                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1276                         };
1277                 };
1278
1279                 edp {
1280                         edp_hpd: edp-hpd {
1281                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1282                         };
1283                 };
1284
1285                 i2c0 {
1286                         i2c0_xfer: i2c0-xfer {
1287                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1288                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1289                         };
1290                 };
1291
1292                 i2c1 {
1293                         i2c1_xfer: i2c1-xfer {
1294                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1295                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1296                         };
1297                 };
1298
1299                 i2c2 {
1300                         i2c2_xfer: i2c2-xfer {
1301                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1302                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1303                         };
1304                 };
1305
1306                 i2c3 {
1307                         i2c3_xfer: i2c3-xfer {
1308                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1309                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1310                         };
1311                 };
1312
1313                 i2c4 {
1314                         i2c4_xfer: i2c4-xfer {
1315                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1316                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1317                         };
1318                 };
1319
1320                 i2c5 {
1321                         i2c5_xfer: i2c5-xfer {
1322                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1323                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1324                         };
1325                 };
1326
1327                 i2s0 {
1328                         i2s0_bus: i2s0-bus {
1329                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1330                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1331                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1332                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1333                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1334                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1335                         };
1336                 };
1337
1338                 lcdc0 {
1339                         lcdc0_ctl: lcdc0-ctl {
1340                                 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1341                                                 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1342                                                 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1343                                                 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1344                         };
1345                 };
1346
1347                 sdmmc {
1348                         sdmmc_clk: sdmmc-clk {
1349                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1350                         };
1351
1352                         sdmmc_cmd: sdmmc-cmd {
1353                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1354                         };
1355
1356                         sdmmc_cd: sdmcc-cd {
1357                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1358                         };
1359
1360                         sdmmc_bus1: sdmmc-bus1 {
1361                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1362                         };
1363
1364                         sdmmc_bus4: sdmmc-bus4 {
1365                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1366                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1367                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1368                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1369                         };
1370                 };
1371
1372                 sdio0 {
1373                         sdio0_bus1: sdio0-bus1 {
1374                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1375                         };
1376
1377                         sdio0_bus4: sdio0-bus4 {
1378                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1379                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1380                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1381                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1382                         };
1383
1384                         sdio0_cmd: sdio0-cmd {
1385                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1386                         };
1387
1388                         sdio0_clk: sdio0-clk {
1389                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1390                         };
1391
1392                         sdio0_cd: sdio0-cd {
1393                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1394                         };
1395
1396                         sdio0_wp: sdio0-wp {
1397                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1398                         };
1399
1400                         sdio0_pwr: sdio0-pwr {
1401                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1402                         };
1403
1404                         sdio0_bkpwr: sdio0-bkpwr {
1405                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1406                         };
1407
1408                         sdio0_int: sdio0-int {
1409                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1410                         };
1411                 };
1412
1413                 sdio1 {
1414                         sdio1_bus1: sdio1-bus1 {
1415                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1416                         };
1417
1418                         sdio1_bus4: sdio1-bus4 {
1419                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1420                                                 <3 25 4 &pcfg_pull_up>,
1421                                                 <3 26 4 &pcfg_pull_up>,
1422                                                 <3 27 4 &pcfg_pull_up>;
1423                         };
1424
1425                         sdio1_cd: sdio1-cd {
1426                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1427                         };
1428
1429                         sdio1_wp: sdio1-wp {
1430                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1431                         };
1432
1433                         sdio1_bkpwr: sdio1-bkpwr {
1434                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1435                         };
1436
1437                         sdio1_int: sdio1-int {
1438                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1439                         };
1440
1441                         sdio1_cmd: sdio1-cmd {
1442                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1443                         };
1444
1445                         sdio1_clk: sdio1-clk {
1446                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1447                         };
1448
1449                         sdio1_pwr: sdio1-pwr {
1450                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1451                         };
1452                 };
1453
1454                 emmc {
1455                         emmc_clk: emmc-clk {
1456                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1457                         };
1458
1459                         emmc_cmd: emmc-cmd {
1460                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1461                         };
1462
1463                         emmc_pwr: emmc-pwr {
1464                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1465                         };
1466
1467                         emmc_bus1: emmc-bus1 {
1468                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1469                         };
1470
1471                         emmc_bus4: emmc-bus4 {
1472                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1473                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1474                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1475                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1476                         };
1477
1478                         emmc_bus8: emmc-bus8 {
1479                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1480                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1481                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1482                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1483                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1484                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1485                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1486                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1487                         };
1488                 };
1489
1490                 spi0 {
1491                         spi0_clk: spi0-clk {
1492                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1493                         };
1494                         spi0_cs0: spi0-cs0 {
1495                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1496                         };
1497                         spi0_tx: spi0-tx {
1498                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1499                         };
1500                         spi0_rx: spi0-rx {
1501                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1502                         };
1503                         spi0_cs1: spi0-cs1 {
1504                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1505                         };
1506                 };
1507                 spi1 {
1508                         spi1_clk: spi1-clk {
1509                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1510                         };
1511                         spi1_cs0: spi1-cs0 {
1512                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1513                         };
1514                         spi1_rx: spi1-rx {
1515                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1516                         };
1517                         spi1_tx: spi1-tx {
1518                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1519                         };
1520                 };
1521
1522                 spi2 {
1523                         spi2_cs1: spi2-cs1 {
1524                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1525                         };
1526                         spi2_clk: spi2-clk {
1527                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1528                         };
1529                         spi2_cs0: spi2-cs0 {
1530                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1531                         };
1532                         spi2_rx: spi2-rx {
1533                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1534                         };
1535                         spi2_tx: spi2-tx {
1536                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1537                         };
1538                 };
1539
1540                 uart0 {
1541                         uart0_xfer: uart0-xfer {
1542                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1543                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1544                         };
1545
1546                         uart0_cts: uart0-cts {
1547                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1548                         };
1549
1550                         uart0_rts: uart0-rts {
1551                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1552                         };
1553                 };
1554
1555                 uart1 {
1556                         uart1_xfer: uart1-xfer {
1557                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1558                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1559                         };
1560
1561                         uart1_cts: uart1-cts {
1562                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1563                         };
1564
1565                         uart1_rts: uart1-rts {
1566                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1567                         };
1568                 };
1569
1570                 uart2 {
1571                         uart2_xfer: uart2-xfer {
1572                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1573                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1574                         };
1575                         /* no rts / cts for uart2 */
1576                 };
1577
1578                 uart3 {
1579                         uart3_xfer: uart3-xfer {
1580                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1581                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1582                         };
1583
1584                         uart3_cts: uart3-cts {
1585                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1586                         };
1587
1588                         uart3_rts: uart3-rts {
1589                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1590                         };
1591                 };
1592
1593                 uart4 {
1594                         uart4_xfer: uart4-xfer {
1595                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1596                                                 <5 13 3 &pcfg_pull_none>;
1597                         };
1598
1599                         uart4_cts: uart4-cts {
1600                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1601                         };
1602
1603                         uart4_rts: uart4-rts {
1604                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1605                         };
1606                 };
1607
1608                 tsadc {
1609                         otp_gpio: otp-gpio {
1610                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1611                         };
1612
1613                         otp_out: otp-out {
1614                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1615                         };
1616                 };
1617
1618                 pwm0 {
1619                         pwm0_pin: pwm0-pin {
1620                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1621                         };
1622                 };
1623
1624                 pwm1 {
1625                         pwm1_pin: pwm1-pin {
1626                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1627                         };
1628                 };
1629
1630                 pwm2 {
1631                         pwm2_pin: pwm2-pin {
1632                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1633                         };
1634                 };
1635
1636                 pwm3 {
1637                         pwm3_pin: pwm3-pin {
1638                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1639                         };
1640                 };
1641
1642                 gmac {
1643                         rgmii_pins: rgmii-pins {
1644                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1645                                                 <3 31 3 &pcfg_pull_none>,
1646                                                 <3 26 3 &pcfg_pull_none>,
1647                                                 <3 27 3 &pcfg_pull_none>,
1648                                                 <3 28 3 &pcfg_pull_none_12ma>,
1649                                                 <3 29 3 &pcfg_pull_none_12ma>,
1650                                                 <3 24 3 &pcfg_pull_none_12ma>,
1651                                                 <3 25 3 &pcfg_pull_none_12ma>,
1652                                                 <4 0 3 &pcfg_pull_none>,
1653                                                 <4 5 3 &pcfg_pull_none>,
1654                                                 <4 6 3 &pcfg_pull_none>,
1655                                                 <4 9 3 &pcfg_pull_none_12ma>,
1656                                                 <4 4 3 &pcfg_pull_none_12ma>,
1657                                                 <4 1 3 &pcfg_pull_none>,
1658                                                 <4 3 3 &pcfg_pull_none>;
1659                         };
1660
1661                         rmii_pins: rmii-pins {
1662                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1663                                                 <3 31 3 &pcfg_pull_none>,
1664                                                 <3 28 3 &pcfg_pull_none>,
1665                                                 <3 29 3 &pcfg_pull_none>,
1666                                                 <4 0 3 &pcfg_pull_none>,
1667                                                 <4 5 3 &pcfg_pull_none>,
1668                                                 <4 4 3 &pcfg_pull_none>,
1669                                                 <4 1 3 &pcfg_pull_none>,
1670                                                 <4 2 3 &pcfg_pull_none>,
1671                                                 <4 3 3 &pcfg_pull_none>;
1672                         };
1673                 };
1674
1675                 spdif {
1676                         spdif_tx: spdif-tx {
1677                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1678                         };
1679                 };
1680         };
1681 };