arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include "skeleton.dtsi"
  49
  50 / {
  51         compatible = "rockchip,rk3288";
  52
  53         interrupt-parent = <&gic>;
  54
  55         aliases {
  56                 i2c0 = &i2c0;
  57                 i2c1 = &i2c1;
  58                 i2c2 = &i2c2;
  59                 i2c3 = &i2c3;
  60                 i2c4 = &i2c4;
  61                 i2c5 = &i2c5;
  62                 mshc0 = &emmc;
  63                 mshc1 = &sdmmc;
  64                 mshc2 = &sdio0;
  65                 mshc3 = &sdio1;
  66                 serial0 = &uart0;
  67                 serial1 = &uart1;
  68                 serial2 = &uart2;
  69                 serial3 = &uart3;
  70                 serial4 = &uart4;
  71                 spi0 = &spi0;
  72                 spi1 = &spi1;
  73                 spi2 = &spi2;
  74         };
  75
  76         arm-pmu {
  77                 compatible = "arm,cortex-a12-pmu";
  78                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  79                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  80                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  82                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  83         };
  84
  85         cpus {
  86                 #address-cells = <1>;
  87                 #size-cells = <0>;
  88                 enable-method = "rockchip,rk3066-smp";
  89                 rockchip,pmu = <&pmu>;
  90
  91                 cpu0: cpu@500 {
  92                         device_type = "cpu";
  93                         compatible = "arm,cortex-a12";
  94                         reg = <0x500>;
  95                         resets = <&cru SRST_CORE0>;
  96                         operating-points = <
  97                                 /* KHz    uV */
  98                                 1608000 1350000
  99                                 1512000 1300000
 100                                 1416000 1200000
 101                                 1200000 1100000
 102                                 1008000 1050000
 103                                  816000 1000000
 104                                  696000  950000
 105                                  600000  900000
 106                                  408000  900000
 107                                  312000  900000
 108                                  216000  900000
 109                                  126000  900000
 110                         >;
 111                         #cooling-cells = <2>; /* min followed by max */
 112                         clock-latency = <40000>;
 113                         clocks = <&cru ARMCLK>;
 114                 };
 115                 cpu1: cpu@501 {
 116                         device_type = "cpu";
 117                         compatible = "arm,cortex-a12";
 118                         reg = <0x501>;
 119                         resets = <&cru SRST_CORE1>;
 120                 };
 121                 cpu2: cpu@502 {
 122                         device_type = "cpu";
 123                         compatible = "arm,cortex-a12";
 124                         reg = <0x502>;
 125                         resets = <&cru SRST_CORE2>;
 126                 };
 127                 cpu3: cpu@503 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a12";
 130                         reg = <0x503>;
 131                         resets = <&cru SRST_CORE3>;
 132                 };
 133         };
 134
 135         amba {
 136                 compatible = "arm,amba-bus";
 137                 #address-cells = <1>;
 138                 #size-cells = <1>;
 139                 ranges;
 140
 141                 dmac_peri: dma-controller@ff250000 {
 142                         compatible = "arm,pl330", "arm,primecell";
 143                         reg = <0xff250000 0x4000>;
 144                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 145                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 146                         #dma-cells = <1>;
 147                         arm,pl330-broken-no-flushp;
 148                         peripherals-req-type-burst;
 149                         clocks = <&cru ACLK_DMAC2>;
 150                         clock-names = "apb_pclk";
 151                 };
 152
 153                 dmac_bus_ns: dma-controller@ff600000 {
 154                         compatible = "arm,pl330", "arm,primecell";
 155                         reg = <0xff600000 0x4000>;
 156                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 157                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 158                         #dma-cells = <1>;
 159                         arm,pl330-broken-no-flushp;
 160                         peripherals-req-type-burst;
 161                         clocks = <&cru ACLK_DMAC1>;
 162                         clock-names = "apb_pclk";
 163                         status = "disabled";
 164                 };
 165
 166                 dmac_bus_s: dma-controller@ffb20000 {
 167                         compatible = "arm,pl330", "arm,primecell";
 168                         reg = <0xffb20000 0x4000>;
 169                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 170                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 171                         #dma-cells = <1>;
 172                         arm,pl330-broken-no-flushp;
 173                         peripherals-req-type-burst;
 174                         clocks = <&cru ACLK_DMAC1>;
 175                         clock-names = "apb_pclk";
 176                 };
 177         };
 178
 179         reserved-memory {
 180                 #address-cells = <1>;
 181                 #size-cells = <1>;
 182                 ranges;
 183
 184                 /*
 185                  * The rk3288 cannot use the memory area above 0xfe000000
 186                  * for dma operations for some reason. While there is
 187                  * probably a better solution available somewhere, we
 188                  * haven't found it yet and while devices with 2GB of ram
 189                  * are not affected, this issue prevents 4GB from booting.
 190                  * So to make these devices at least bootable, block
 191                  * this area for the time being until the real solution
 192                  * is found.
 193                  */
 194                 dma-unusable@fe000000 {
 195                         reg = <0xfe000000 0x1000000>;
 196                 };
 197         };
 198
 199         xin24m: oscillator {
 200                 compatible = "fixed-clock";
 201                 clock-frequency = <24000000>;
 202                 clock-output-names = "xin24m";
 203                 #clock-cells = <0>;
 204         };
 205
 206         edp_phy: edp-phy {
 207                 compatible = "rockchip,rk3288-dp-phy";
 208                 clocks = <&cru SCLK_EDP_24M>;
 209                 clock-names = "24m";
 210                 rockchip,grf = <&grf>;
 211                 #phy-cells = <0>;
 212                 status = "disabled";
 213         };
 214
 215         timer {
 216                 compatible = "arm,armv7-timer";
 217                 arm,cpu-registers-not-fw-configured;
 218                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 219                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 220                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 221                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 222                 clock-frequency = <24000000>;
 223         };
 224
 225         timer: timer@ff810000 {
 226                 compatible = "rockchip,rk3288-timer";
 227                 reg = <0xff810000 0x20>;
 228                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 229                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 230                 clock-names = "timer", "pclk";
 231         };
 232
 233         display-subsystem {
 234                 compatible = "rockchip,display-subsystem";
 235                 ports = <&vopl_out>, <&vopb_out>;
 236         };
 237
 238         sdmmc: dwmmc@ff0c0000 {
 239                 compatible = "rockchip,rk3288-dw-mshc";
 240                 clock-freq-min-max = <400000 150000000>;
 241                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 242                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 243                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 244                 fifo-depth = <0x100>;
 245                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 246                 reg = <0xff0c0000 0x4000>;
 247                 status = "disabled";
 248         };
 249
 250         sdio0: dwmmc@ff0d0000 {
 251                 compatible = "rockchip,rk3288-dw-mshc";
 252                 clock-freq-min-max = <400000 150000000>;
 253                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 254                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 255                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 256                 fifo-depth = <0x100>;
 257                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 258                 reg = <0xff0d0000 0x4000>;
 259                 status = "disabled";
 260         };
 261
 262         sdio1: dwmmc@ff0e0000 {
 263                 compatible = "rockchip,rk3288-dw-mshc";
 264                 clock-freq-min-max = <400000 150000000>;
 265                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 266                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 267                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 268                 fifo-depth = <0x100>;
 269                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 270                 reg = <0xff0e0000 0x4000>;
 271                 status = "disabled";
 272         };
 273
 274         emmc: dwmmc@ff0f0000 {
 275                 compatible = "rockchip,rk3288-dw-mshc";
 276                 clock-freq-min-max = <400000 150000000>;
 277                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 278                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 279                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 280                 fifo-depth = <0x100>;
 281                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 282                 reg = <0xff0f0000 0x4000>;
 283                 status = "disabled";
 284                 supports-emmc;
 285         };
 286
 287         saradc: saradc@ff100000 {
 288                 compatible = "rockchip,saradc";
 289                 reg = <0xff100000 0x100>;
 290                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 291                 #io-channel-cells = <1>;
 292                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 293                 clock-names = "saradc", "apb_pclk";
 294                 status = "disabled";
 295         };
 296
 297         spi0: spi@ff110000 {
 298                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 299                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 300                 clock-names = "spiclk", "apb_pclk";
 301                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 302                 dma-names = "tx", "rx";
 303                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 304                 pinctrl-names = "default";
 305                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 306                 reg = <0xff110000 0x1000>;
 307                 #address-cells = <1>;
 308                 #size-cells = <0>;
 309                 status = "disabled";
 310         };
 311
 312         spi1: spi@ff120000 {
 313                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 314                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 315                 clock-names = "spiclk", "apb_pclk";
 316                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 317                 dma-names = "tx", "rx";
 318                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 319                 pinctrl-names = "default";
 320                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 321                 reg = <0xff120000 0x1000>;
 322                 #address-cells = <1>;
 323                 #size-cells = <0>;
 324                 status = "disabled";
 325         };
 326
 327         spi2: spi@ff130000 {
 328                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 329                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 330                 clock-names = "spiclk", "apb_pclk";
 331                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 332                 dma-names = "tx", "rx";
 333                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 334                 pinctrl-names = "default";
 335                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 336                 reg = <0xff130000 0x1000>;
 337                 #address-cells = <1>;
 338                 #size-cells = <0>;
 339                 status = "disabled";
 340         };
 341
 342         i2c1: i2c@ff140000 {
 343                 compatible = "rockchip,rk3288-i2c";
 344                 reg = <0xff140000 0x1000>;
 345                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 346                 #address-cells = <1>;
 347                 #size-cells = <0>;
 348                 clock-names = "i2c";
 349                 clocks = <&cru PCLK_I2C1>;
 350                 pinctrl-names = "default";
 351                 pinctrl-0 = <&i2c1_xfer>;
 352                 status = "disabled";
 353         };
 354
 355         i2c3: i2c@ff150000 {
 356                 compatible = "rockchip,rk3288-i2c";
 357                 reg = <0xff150000 0x1000>;
 358                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 359                 #address-cells = <1>;
 360                 #size-cells = <0>;
 361                 clock-names = "i2c";
 362                 clocks = <&cru PCLK_I2C3>;
 363                 pinctrl-names = "default";
 364                 pinctrl-0 = <&i2c3_xfer>;
 365                 status = "disabled";
 366         };
 367
 368         i2c4: i2c@ff160000 {
 369                 compatible = "rockchip,rk3288-i2c";
 370                 reg = <0xff160000 0x1000>;
 371                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 372                 #address-cells = <1>;
 373                 #size-cells = <0>;
 374                 clock-names = "i2c";
 375                 clocks = <&cru PCLK_I2C4>;
 376                 pinctrl-names = "default";
 377                 pinctrl-0 = <&i2c4_xfer>;
 378                 status = "disabled";
 379         };
 380
 381         i2c5: i2c@ff170000 {
 382                 compatible = "rockchip,rk3288-i2c";
 383                 reg = <0xff170000 0x1000>;
 384                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 385                 #address-cells = <1>;
 386                 #size-cells = <0>;
 387                 clock-names = "i2c";
 388                 clocks = <&cru PCLK_I2C5>;
 389                 pinctrl-names = "default";
 390                 pinctrl-0 = <&i2c5_xfer>;
 391                 status = "disabled";
 392         };
 393
 394         uart0: serial@ff180000 {
 395                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 396                 reg = <0xff180000 0x100>;
 397                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 398                 reg-shift = <2>;
 399                 reg-io-width = <4>;
 400                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 401                 clock-names = "baudclk", "apb_pclk";
 402                 pinctrl-names = "default";
 403                 pinctrl-0 = <&uart0_xfer>;
 404                 status = "disabled";
 405         };
 406
 407         uart1: serial@ff190000 {
 408                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 409                 reg = <0xff190000 0x100>;
 410                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 411                 reg-shift = <2>;
 412                 reg-io-width = <4>;
 413                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 414                 clock-names = "baudclk", "apb_pclk";
 415                 pinctrl-names = "default";
 416                 pinctrl-0 = <&uart1_xfer>;
 417                 status = "disabled";
 418         };
 419
 420         uart2: serial@ff690000 {
 421                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 422                 reg = <0xff690000 0x100>;
 423                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 424                 reg-shift = <2>;
 425                 reg-io-width = <4>;
 426                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 427                 clock-names = "baudclk", "apb_pclk";
 428                 pinctrl-names = "default";
 429                 pinctrl-0 = <&uart2_xfer>;
 430                 status = "disabled";
 431         };
 432
 433         uart3: serial@ff1b0000 {
 434                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 435                 reg = <0xff1b0000 0x100>;
 436                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 437                 reg-shift = <2>;
 438                 reg-io-width = <4>;
 439                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 440                 clock-names = "baudclk", "apb_pclk";
 441                 pinctrl-names = "default";
 442                 pinctrl-0 = <&uart3_xfer>;
 443                 status = "disabled";
 444         };
 445
 446         uart4: serial@ff1c0000 {
 447                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 448                 reg = <0xff1c0000 0x100>;
 449                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 450                 reg-shift = <2>;
 451                 reg-io-width = <4>;
 452                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 453                 clock-names = "baudclk", "apb_pclk";
 454                 pinctrl-names = "default";
 455                 pinctrl-0 = <&uart4_xfer>;
 456                 status = "disabled";
 457         };
 458
 459         thermal-zones {
 460                 #include "rk3288-thermal.dtsi"
 461         };
 462
 463         tsadc: tsadc@ff280000 {
 464                 compatible = "rockchip,rk3288-tsadc";
 465                 reg = <0xff280000 0x100>;
 466                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 467                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 468                 clock-names = "tsadc", "apb_pclk";
 469                 resets = <&cru SRST_TSADC>;
 470                 reset-names = "tsadc-apb";
 471                 pinctrl-names = "init", "default", "sleep";
 472                 pinctrl-0 = <&otp_gpio>;
 473                 pinctrl-1 = <&otp_out>;
 474                 pinctrl-2 = <&otp_gpio>;
 475                 #thermal-sensor-cells = <1>;
 476                 rockchip,hw-tshut-temp = <95000>;
 477                 status = "disabled";
 478         };
 479
 480         gmac: ethernet@ff290000 {
 481                 compatible = "rockchip,rk3288-gmac";
 482                 reg = <0xff290000 0x10000>;
 483                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 484                 interrupt-names = "macirq";
 485                 rockchip,grf = <&grf>;
 486                 clocks = <&cru SCLK_MAC>,
 487                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 488                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 489                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 490                 clock-names = "stmmaceth",
 491                         "mac_clk_rx", "mac_clk_tx",
 492                         "clk_mac_ref", "clk_mac_refout",
 493                         "aclk_mac", "pclk_mac";
 494                 resets = <&cru SRST_MAC>;
 495                 reset-names = "stmmaceth";
 496                 status = "disabled";
 497         };
 498
 499         usb_host0_ehci: usb@ff500000 {
 500                 compatible = "generic-ehci";
 501                 reg = <0xff500000 0x100>;
 502                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 503                 clocks = <&cru HCLK_USBHOST0>;
 504                 clock-names = "usbhost";
 505                 phys = <&usbphy1>;
 506                 phy-names = "usb";
 507                 status = "disabled";
 508         };
 509
 510         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 511
 512         usb_host1: usb@ff540000 {
 513                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 514                                 "snps,dwc2";
 515                 reg = <0xff540000 0x40000>;
 516                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 517                 clocks = <&cru HCLK_USBHOST1>;
 518                 clock-names = "otg";
 519                 dr_mode = "host";
 520                 phys = <&usbphy2>;
 521                 phy-names = "usb2-phy";
 522                 status = "disabled";
 523         };
 524
 525         usb_otg: usb@ff580000 {
 526                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 527                                 "snps,dwc2";
 528                 reg = <0xff580000 0x40000>;
 529                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 530                 clocks = <&cru HCLK_OTG0>;
 531                 clock-names = "otg";
 532                 dr_mode = "otg";
 533                 g-np-tx-fifo-size = <16>;
 534                 g-rx-fifo-size = <275>;
 535                 g-tx-fifo-size = <256 128 128 64 64 32>;
 536                 g-use-dma;
 537                 phys = <&usbphy0>;
 538                 phy-names = "usb2-phy";
 539                 status = "disabled";
 540         };
 541
 542         usb_hsic: usb@ff5c0000 {
 543                 compatible = "generic-ehci";
 544                 reg = <0xff5c0000 0x100>;
 545                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 546                 clocks = <&cru HCLK_HSIC>;
 547                 clock-names = "usbhost";
 548                 status = "disabled";
 549         };
 550
 551         i2c0: i2c@ff650000 {
 552                 compatible = "rockchip,rk3288-i2c";
 553                 reg = <0xff650000 0x1000>;
 554                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 555                 #address-cells = <1>;
 556                 #size-cells = <0>;
 557                 clock-names = "i2c";
 558                 clocks = <&cru PCLK_I2C0>;
 559                 pinctrl-names = "default";
 560                 pinctrl-0 = <&i2c0_xfer>;
 561                 status = "disabled";
 562         };
 563
 564         i2c2: i2c@ff660000 {
 565                 compatible = "rockchip,rk3288-i2c";
 566                 reg = <0xff660000 0x1000>;
 567                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 568                 #address-cells = <1>;
 569                 #size-cells = <0>;
 570                 clock-names = "i2c";
 571                 clocks = <&cru PCLK_I2C2>;
 572                 pinctrl-names = "default";
 573                 pinctrl-0 = <&i2c2_xfer>;
 574                 status = "disabled";
 575         };
 576
 577         pwm0: pwm@ff680000 {
 578                 compatible = "rockchip,rk3288-pwm";
 579                 reg = <0xff680000 0x10>;
 580                 #pwm-cells = <3>;
 581                 pinctrl-names = "default";
 582                 pinctrl-0 = <&pwm0_pin>;
 583                 clocks = <&cru PCLK_PWM>;
 584                 clock-names = "pwm";
 585                 status = "disabled";
 586         };
 587
 588         pwm1: pwm@ff680010 {
 589                 compatible = "rockchip,rk3288-pwm";
 590                 reg = <0xff680010 0x10>;
 591                 #pwm-cells = <3>;
 592                 pinctrl-names = "default";
 593                 pinctrl-0 = <&pwm1_pin>;
 594                 clocks = <&cru PCLK_PWM>;
 595                 clock-names = "pwm";
 596                 status = "disabled";
 597         };
 598
 599         pwm2: pwm@ff680020 {
 600                 compatible = "rockchip,rk3288-pwm";
 601                 reg = <0xff680020 0x10>;
 602                 #pwm-cells = <3>;
 603                 pinctrl-names = "default";
 604                 pinctrl-0 = <&pwm2_pin>;
 605                 clocks = <&cru PCLK_PWM>;
 606                 clock-names = "pwm";
 607                 status = "disabled";
 608         };
 609
 610         pwm3: pwm@ff680030 {
 611                 compatible = "rockchip,rk3288-pwm";
 612                 reg = <0xff680030 0x10>;
 613                 #pwm-cells = <2>;
 614                 pinctrl-names = "default";
 615                 pinctrl-0 = <&pwm3_pin>;
 616                 clocks = <&cru PCLK_PWM>;
 617                 clock-names = "pwm";
 618                 status = "disabled";
 619         };
 620
 621         bus_intmem@ff700000 {
 622                 compatible = "mmio-sram";
 623                 reg = <0xff700000 0x18000>;
 624                 #address-cells = <1>;
 625                 #size-cells = <1>;
 626                 ranges = <0 0xff700000 0x18000>;
 627                 smp-sram@0 {
 628                         compatible = "rockchip,rk3066-smp-sram";
 629                         reg = <0x00 0x10>;
 630                 };
 631         };
 632
 633         sram@ff720000 {
 634                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 635                 reg = <0xff720000 0x1000>;
 636         };
 637
 638         pmu: power-management@ff730000 {
 639                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 640                 reg = <0xff730000 0x100>;
 641
 642                 power: power-controller {
 643                         compatible = "rockchip,rk3288-power-controller";
 644                         #power-domain-cells = <1>;
 645                         #address-cells = <1>;
 646                         #size-cells = <0>;
 647
 648                         /*
 649                          * Note: Although SCLK_* are the working clocks
 650                          * of device without including on the NOC, needed for
 651                          * synchronous reset.
 652                          *
 653                          * The clocks on the which NOC:
 654                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 655                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 656                          * ACLK_RGA is on ACLK_RGA_NIU.
 657                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 658                          *
 659                          * Which clock are device clocks:
 660                          *      clocks          devices
 661                          *      *_IEP           IEP:Image Enhancement Processor
 662                          *      *_ISP           ISP:Image Signal Processing
 663                          *      *_VIP           VIP:Video Input Processor
 664                          *      *_VOP*          VOP:Visual Output Processor
 665                          *      *_RGA           RGA
 666                          *      *_EDP*          EDP
 667                          *      *_LVDS_*        LVDS
 668                          *      *_HDMI          HDMI
 669                          *      *_MIPI_*        MIPI
 670                          */
 671                         pd_vio {
 672                                 reg = <RK3288_PD_VIO>;
 673                                 clocks = <&cru ACLK_IEP>,
 674                                          <&cru ACLK_ISP>,
 675                                          <&cru ACLK_RGA>,
 676                                          <&cru ACLK_VIP>,
 677                                          <&cru ACLK_VOP0>,
 678                                          <&cru ACLK_VOP1>,
 679                                          <&cru DCLK_VOP0>,
 680                                          <&cru DCLK_VOP1>,
 681                                          <&cru HCLK_IEP>,
 682                                          <&cru HCLK_ISP>,
 683                                          <&cru HCLK_RGA>,
 684                                          <&cru HCLK_VIP>,
 685                                          <&cru HCLK_VOP0>,
 686                                          <&cru HCLK_VOP1>,
 687                                          <&cru PCLK_EDP_CTRL>,
 688                                          <&cru PCLK_HDMI_CTRL>,
 689                                          <&cru PCLK_LVDS_PHY>,
 690                                          <&cru PCLK_MIPI_CSI>,
 691                                          <&cru PCLK_MIPI_DSI0>,
 692                                          <&cru PCLK_MIPI_DSI1>,
 693                                          <&cru SCLK_EDP_24M>,
 694                                          <&cru SCLK_EDP>,
 695                                          <&cru SCLK_ISP_JPE>,
 696                                          <&cru SCLK_ISP>,
 697                                          <&cru SCLK_RGA>;
 698                         };
 699
 700                         /*
 701                          * Note: The following 3 are HEVC(H.265) clocks,
 702                          * and on the ACLK_HEVC_NIU (NOC).
 703                          */
 704                         pd_hevc {
 705                                 reg = <RK3288_PD_HEVC>;
 706                                 clocks = <&cru ACLK_HEVC>,
 707                                          <&cru SCLK_HEVC_CABAC>,
 708                                          <&cru SCLK_HEVC_CORE>;
 709                         };
 710
 711                         /*
 712                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 713                          * (video endecoder & decoder) clocks that on the
 714                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 715                          */
 716                         pd_video {
 717                                 reg = <RK3288_PD_VIDEO>;
 718                                 clocks = <&cru ACLK_VCODEC>,
 719                                          <&cru HCLK_VCODEC>;
 720                         };
 721
 722                         /*
 723                          * Note: ACLK_GPU is the GPU clock,
 724                          * and on the ACLK_GPU_NIU (NOC).
 725                          */
 726                         pd_gpu {
 727                                 reg = <RK3288_PD_GPU>;
 728                                 clocks = <&cru ACLK_GPU>;
 729                         };
 730                 };
 731         };
 732
 733         sgrf: syscon@ff740000 {
 734                 compatible = "rockchip,rk3288-sgrf", "syscon";
 735                 reg = <0xff740000 0x1000>;
 736         };
 737
 738         cru: clock-controller@ff760000 {
 739                 compatible = "rockchip,rk3288-cru";
 740                 reg = <0xff760000 0x1000>;
 741                 rockchip,grf = <&grf>;
 742                 #clock-cells = <1>;
 743                 #reset-cells = <1>;
 744                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 745                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 746                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 747                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 748                                   <&cru PCLK_PERI>;
 749                 assigned-clock-rates = <594000000>, <400000000>,
 750                                        <500000000>, <300000000>,
 751                                        <150000000>, <75000000>,
 752                                        <300000000>, <150000000>,
 753                                        <75000000>;
 754         };
 755
 756         grf: syscon@ff770000 {
 757                 compatible = "rockchip,rk3288-grf", "syscon";
 758                 reg = <0xff770000 0x1000>;
 759         };
 760
 761         wdt: watchdog@ff800000 {
 762                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 763                 reg = <0xff800000 0x100>;
 764                 clocks = <&cru PCLK_WDT>;
 765                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 766                 status = "disabled";
 767         };
 768
 769         spdif: sound@ff88b0000 {
 770                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 771                 reg = <0xff8b0000 0x10000>;
 772                 #sound-dai-cells = <0>;
 773                 clock-names = "hclk", "mclk";
 774                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 775                 dmas = <&dmac_bus_s 3>;
 776                 dma-names = "tx";
 777                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 778                 pinctrl-names = "default";
 779                 pinctrl-0 = <&spdif_tx>;
 780                 rockchip,grf = <&grf>;
 781                 status = "disabled";
 782         };
 783
 784         i2s: i2s@ff890000 {
 785                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 786                 reg = <0xff890000 0x10000>;
 787                 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
 788                 #address-cells = <1>;
 789                 #size-cells = <0>;
 790                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 791                 dma-names = "tx", "rx";
 792                 clock-names = "i2s_hclk", "i2s_clk";
 793                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 794                 pinctrl-names = "default";
 795                 pinctrl-0 = <&i2s0_bus>;
 796                 status = "disabled";
 797         };
 798
 799         vopb: vop@ff930000 {
 800                 compatible = "rockchip,rk3288-vop";
 801                 reg = <0xff930000 0x19c>;
 802                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 803                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 804                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 805                 power-domains = <&power RK3288_PD_VIO>;
 806                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 807                 reset-names = "axi", "ahb", "dclk";
 808                 iommus = <&vopb_mmu>;
 809                 status = "disabled";
 810
 811                 vopb_out: port {
 812                         #address-cells = <1>;
 813                         #size-cells = <0>;
 814
 815                         vopb_out_hdmi: endpoint@0 {
 816                                 reg = <0>;
 817                                 remote-endpoint = <&hdmi_in_vopb>;
 818                         };
 819
 820                         vopb_out_edp: endpoint@1 {
 821                                 reg = <1>;
 822                                 remote-endpoint = <&edp_in_vopb>;
 823                         };
 824
 825                         vopb_out_mipi: endpoint@2 {
 826                                 reg = <2>;
 827                                 remote-endpoint = <&mipi_in_vopb>;
 828                         };
 829                 };
 830         };
 831
 832         vopb_mmu: iommu@ff930300 {
 833                 compatible = "rockchip,iommu";
 834                 reg = <0xff930300 0x100>;
 835                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 836                 interrupt-names = "vopb_mmu";
 837                 power-domains = <&power RK3288_PD_VIO>;
 838                 #iommu-cells = <0>;
 839                 status = "disabled";
 840         };
 841
 842         vopl: vop@ff940000 {
 843                 compatible = "rockchip,rk3288-vop";
 844                 reg = <0xff940000 0x19c>;
 845                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 846                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 847                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 848                 power-domains = <&power RK3288_PD_VIO>;
 849                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 850                 reset-names = "axi", "ahb", "dclk";
 851                 iommus = <&vopl_mmu>;
 852                 status = "disabled";
 853
 854                 vopl_out: port {
 855                         #address-cells = <1>;
 856                         #size-cells = <0>;
 857
 858                         vopl_out_hdmi: endpoint@0 {
 859                                 reg = <0>;
 860                                 remote-endpoint = <&hdmi_in_vopl>;
 861                         };
 862
 863                         vopl_out_edp: endpoint@1 {
 864                                 reg = <1>;
 865                                 remote-endpoint = <&edp_in_vopl>;
 866                         };
 867
 868                         vopl_out_mipi: endpoint@2 {
 869                                 reg = <2>;
 870                                 remote-endpoint = <&mipi_in_vopl>;
 871                         };
 872                 };
 873         };
 874
 875         vopl_mmu: iommu@ff940300 {
 876                 compatible = "rockchip,iommu";
 877                 reg = <0xff940300 0x100>;
 878                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 879                 interrupt-names = "vopl_mmu";
 880                 power-domains = <&power RK3288_PD_VIO>;
 881                 #iommu-cells = <0>;
 882                 status = "disabled";
 883         };
 884
 885         mipi_dsi: mipi@ff960000 {
 886                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
 887                 reg = <0xff960000 0x4000>;
 888                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 889                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
 890                 clock-names = "ref", "pclk";
 891                 rockchip,grf = <&grf>;
 892                 #address-cells = <1>;
 893                 #size-cells = <0>;
 894                 status = "disabled";
 895
 896                 ports {
 897                         #address-cells = <1>;
 898                         #size-cells = <0>;
 899                         reg = <1>;
 900
 901                         mipi_in: port {
 902                                 #address-cells = <1>;
 903                                 #size-cells = <0>;
 904                                 mipi_in_vopb: endpoint@0 {
 905                                         reg = <0>;
 906                                         remote-endpoint = <&vopb_out_mipi>;
 907                                 };
 908                                 mipi_in_vopl: endpoint@1 {
 909                                         reg = <1>;
 910                                         remote-endpoint = <&vopl_out_mipi>;
 911                                 };
 912                         };
 913                 };
 914         };
 915
 916         edp: dp@ff970000 {
 917                 compatible = "rockchip,rk3288-dp";
 918                 reg = <0xff970000 0x4000>;
 919                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 920                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
 921                 clock-names = "dp", "pclk";
 922                 phys = <&edp_phy>;
 923                 phy-names = "dp";
 924                 resets = <&cru SRST_EDP>;
 925                 reset-names = "dp";
 926                 rockchip,grf = <&grf>;
 927                 status = "disabled";
 928
 929                 ports {
 930                         #address-cells = <1>;
 931                         #size-cells = <0>;
 932                         edp_in: port@0 {
 933                                 reg = <0>;
 934                                 #address-cells = <1>;
 935                                 #size-cells = <0>;
 936                                 edp_in_vopb: endpoint@0 {
 937                                         reg = <0>;
 938                                         remote-endpoint = <&vopb_out_edp>;
 939                                 };
 940                                 edp_in_vopl: endpoint@1 {
 941                                         reg = <1>;
 942                                         remote-endpoint = <&vopl_out_edp>;
 943                                 };
 944                         };
 945                 };
 946         };
 947
 948         hdmi: hdmi@ff980000 {
 949                 compatible = "rockchip,rk3288-dw-hdmi";
 950                 reg = <0xff980000 0x20000>;
 951                 reg-io-width = <4>;
 952                 rockchip,grf = <&grf>;
 953                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 954                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
 955                 clock-names = "iahb", "isfr";
 956                 power-domains = <&power RK3288_PD_VIO>;
 957                 status = "disabled";
 958
 959                 ports {
 960                         hdmi_in: port {
 961                                 #address-cells = <1>;
 962                                 #size-cells = <0>;
 963                                 hdmi_in_vopb: endpoint@0 {
 964                                         reg = <0>;
 965                                         remote-endpoint = <&vopb_out_hdmi>;
 966                                 };
 967                                 hdmi_in_vopl: endpoint@1 {
 968                                         reg = <1>;
 969                                         remote-endpoint = <&vopl_out_hdmi>;
 970                                 };
 971                         };
 972                 };
 973         };
 974
 975         gic: interrupt-controller@ffc01000 {
 976                 compatible = "arm,gic-400";
 977                 interrupt-controller;
 978                 #interrupt-cells = <3>;
 979                 #address-cells = <0>;
 980
 981                 reg = <0xffc01000 0x1000>,
 982                       <0xffc02000 0x1000>,
 983                       <0xffc04000 0x2000>,
 984                       <0xffc06000 0x2000>;
 985                 interrupts = <GIC_PPI 9 0xf04>;
 986         };
 987
 988         usbphy: phy {
 989                 compatible = "rockchip,rk3288-usb-phy";
 990                 rockchip,grf = <&grf>;
 991                 #address-cells = <1>;
 992                 #size-cells = <0>;
 993                 status = "disabled";
 994
 995                 usbphy0: usb-phy0 {
 996                         #phy-cells = <0>;
 997                         reg = <0x320>;
 998                         clocks = <&cru SCLK_OTGPHY0>;
 999                         clock-names = "phyclk";
1000                 };
1001
1002                 usbphy1: usb-phy1 {
1003                         #phy-cells = <0>;
1004                         reg = <0x334>;
1005                         clocks = <&cru SCLK_OTGPHY1>;
1006                         clock-names = "phyclk";
1007                 };
1008
1009                 usbphy2: usb-phy2 {
1010                         #phy-cells = <0>;
1011                         reg = <0x348>;
1012                         clocks = <&cru SCLK_OTGPHY2>;
1013                         clock-names = "phyclk";
1014                 };
1015         };
1016
1017         pinctrl: pinctrl {
1018                 compatible = "rockchip,rk3288-pinctrl";
1019                 rockchip,grf = <&grf>;
1020                 rockchip,pmu = <&pmu>;
1021                 #address-cells = <1>;
1022                 #size-cells = <1>;
1023                 ranges;
1024
1025                 gpio0: gpio0@ff750000 {
1026                         compatible = "rockchip,gpio-bank";
1027                         reg =   <0xff750000 0x100>;
1028                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1029                         clocks = <&cru PCLK_GPIO0>;
1030
1031                         gpio-controller;
1032                         #gpio-cells = <2>;
1033
1034                         interrupt-controller;
1035                         #interrupt-cells = <2>;
1036                 };
1037
1038                 gpio1: gpio1@ff780000 {
1039                         compatible = "rockchip,gpio-bank";
1040                         reg = <0xff780000 0x100>;
1041                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1042                         clocks = <&cru PCLK_GPIO1>;
1043
1044                         gpio-controller;
1045                         #gpio-cells = <2>;
1046
1047                         interrupt-controller;
1048                         #interrupt-cells = <2>;
1049                 };
1050
1051                 gpio2: gpio2@ff790000 {
1052                         compatible = "rockchip,gpio-bank";
1053                         reg = <0xff790000 0x100>;
1054                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1055                         clocks = <&cru PCLK_GPIO2>;
1056
1057                         gpio-controller;
1058                         #gpio-cells = <2>;
1059
1060                         interrupt-controller;
1061                         #interrupt-cells = <2>;
1062                 };
1063
1064                 gpio3: gpio3@ff7a0000 {
1065                         compatible = "rockchip,gpio-bank";
1066                         reg = <0xff7a0000 0x100>;
1067                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1068                         clocks = <&cru PCLK_GPIO3>;
1069
1070                         gpio-controller;
1071                         #gpio-cells = <2>;
1072
1073                         interrupt-controller;
1074                         #interrupt-cells = <2>;
1075                 };
1076
1077                 gpio4: gpio4@ff7b0000 {
1078                         compatible = "rockchip,gpio-bank";
1079                         reg = <0xff7b0000 0x100>;
1080                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1081                         clocks = <&cru PCLK_GPIO4>;
1082
1083                         gpio-controller;
1084                         #gpio-cells = <2>;
1085
1086                         interrupt-controller;
1087                         #interrupt-cells = <2>;
1088                 };
1089
1090                 gpio5: gpio5@ff7c0000 {
1091                         compatible = "rockchip,gpio-bank";
1092                         reg = <0xff7c0000 0x100>;
1093                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1094                         clocks = <&cru PCLK_GPIO5>;
1095
1096                         gpio-controller;
1097                         #gpio-cells = <2>;
1098
1099                         interrupt-controller;
1100                         #interrupt-cells = <2>;
1101                 };
1102
1103                 gpio6: gpio6@ff7d0000 {
1104                         compatible = "rockchip,gpio-bank";
1105                         reg = <0xff7d0000 0x100>;
1106                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1107                         clocks = <&cru PCLK_GPIO6>;
1108
1109                         gpio-controller;
1110                         #gpio-cells = <2>;
1111
1112                         interrupt-controller;
1113                         #interrupt-cells = <2>;
1114                 };
1115
1116                 gpio7: gpio7@ff7e0000 {
1117                         compatible = "rockchip,gpio-bank";
1118                         reg = <0xff7e0000 0x100>;
1119                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1120                         clocks = <&cru PCLK_GPIO7>;
1121
1122                         gpio-controller;
1123                         #gpio-cells = <2>;
1124
1125                         interrupt-controller;
1126                         #interrupt-cells = <2>;
1127                 };
1128
1129                 gpio8: gpio8@ff7f0000 {
1130                         compatible = "rockchip,gpio-bank";
1131                         reg = <0xff7f0000 0x100>;
1132                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1133                         clocks = <&cru PCLK_GPIO8>;
1134
1135                         gpio-controller;
1136                         #gpio-cells = <2>;
1137
1138                         interrupt-controller;
1139                         #interrupt-cells = <2>;
1140                 };
1141
1142                 hdmi {
1143                         hdmi_ddc: hdmi-ddc {
1144                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1145                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1146                         };
1147                 };
1148
1149                 pcfg_pull_up: pcfg-pull-up {
1150                         bias-pull-up;
1151                 };
1152
1153                 pcfg_pull_down: pcfg-pull-down {
1154                         bias-pull-down;
1155                 };
1156
1157                 pcfg_pull_none: pcfg-pull-none {
1158                         bias-disable;
1159                 };
1160
1161                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1162                         bias-disable;
1163                         drive-strength = <12>;
1164                 };
1165
1166                 sleep {
1167                         global_pwroff: global-pwroff {
1168                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1169                         };
1170
1171                         ddrio_pwroff: ddrio-pwroff {
1172                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1173                         };
1174
1175                         ddr0_retention: ddr0-retention {
1176                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1177                         };
1178
1179                         ddr1_retention: ddr1-retention {
1180                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1181                         };
1182                 };
1183
1184                 edp {
1185                         edp_hpd: edp-hpd {
1186                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1187                         };
1188                 };
1189
1190                 i2c0 {
1191                         i2c0_xfer: i2c0-xfer {
1192                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1193                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1194                         };
1195                 };
1196
1197                 i2c1 {
1198                         i2c1_xfer: i2c1-xfer {
1199                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1200                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1201                         };
1202                 };
1203
1204                 i2c2 {
1205                         i2c2_xfer: i2c2-xfer {
1206                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1207                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1208                         };
1209                 };
1210
1211                 i2c3 {
1212                         i2c3_xfer: i2c3-xfer {
1213                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1214                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1215                         };
1216                 };
1217
1218                 i2c4 {
1219                         i2c4_xfer: i2c4-xfer {
1220                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1221                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1222                         };
1223                 };
1224
1225                 i2c5 {
1226                         i2c5_xfer: i2c5-xfer {
1227                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1228                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1229                         };
1230                 };
1231
1232                 i2s0 {
1233                         i2s0_bus: i2s0-bus {
1234                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1235                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1236                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1237                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1238                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1239                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1240                         };
1241                 };
1242
1243                 sdmmc {
1244                         sdmmc_clk: sdmmc-clk {
1245                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1246                         };
1247
1248                         sdmmc_cmd: sdmmc-cmd {
1249                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1250                         };
1251
1252                         sdmmc_cd: sdmcc-cd {
1253                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1254                         };
1255
1256                         sdmmc_bus1: sdmmc-bus1 {
1257                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1258                         };
1259
1260                         sdmmc_bus4: sdmmc-bus4 {
1261                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1262                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1263                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1264                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1265                         };
1266                 };
1267
1268                 sdio0 {
1269                         sdio0_bus1: sdio0-bus1 {
1270                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1271                         };
1272
1273                         sdio0_bus4: sdio0-bus4 {
1274                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1275                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1276                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1277                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1278                         };
1279
1280                         sdio0_cmd: sdio0-cmd {
1281                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1282                         };
1283
1284                         sdio0_clk: sdio0-clk {
1285                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1286                         };
1287
1288                         sdio0_cd: sdio0-cd {
1289                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1290                         };
1291
1292                         sdio0_wp: sdio0-wp {
1293                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1294                         };
1295
1296                         sdio0_pwr: sdio0-pwr {
1297                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1298                         };
1299
1300                         sdio0_bkpwr: sdio0-bkpwr {
1301                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1302                         };
1303
1304                         sdio0_int: sdio0-int {
1305                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1306                         };
1307                 };
1308
1309                 sdio1 {
1310                         sdio1_bus1: sdio1-bus1 {
1311                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1312                         };
1313
1314                         sdio1_bus4: sdio1-bus4 {
1315                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1316                                                 <3 25 4 &pcfg_pull_up>,
1317                                                 <3 26 4 &pcfg_pull_up>,
1318                                                 <3 27 4 &pcfg_pull_up>;
1319                         };
1320
1321                         sdio1_cd: sdio1-cd {
1322                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1323                         };
1324
1325                         sdio1_wp: sdio1-wp {
1326                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1327                         };
1328
1329                         sdio1_bkpwr: sdio1-bkpwr {
1330                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1331                         };
1332
1333                         sdio1_int: sdio1-int {
1334                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1335                         };
1336
1337                         sdio1_cmd: sdio1-cmd {
1338                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1339                         };
1340
1341                         sdio1_clk: sdio1-clk {
1342                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1343                         };
1344
1345                         sdio1_pwr: sdio1-pwr {
1346                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1347                         };
1348                 };
1349
1350                 emmc {
1351                         emmc_clk: emmc-clk {
1352                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1353                         };
1354
1355                         emmc_cmd: emmc-cmd {
1356                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1357                         };
1358
1359                         emmc_pwr: emmc-pwr {
1360                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1361                         };
1362
1363                         emmc_bus1: emmc-bus1 {
1364                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1365                         };
1366
1367                         emmc_bus4: emmc-bus4 {
1368                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1369                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1370                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1371                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1372                         };
1373
1374                         emmc_bus8: emmc-bus8 {
1375                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1376                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1377                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1378                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1379                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1380                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1381                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1382                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1383                         };
1384                 };
1385
1386                 spi0 {
1387                         spi0_clk: spi0-clk {
1388                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1389                         };
1390                         spi0_cs0: spi0-cs0 {
1391                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1392                         };
1393                         spi0_tx: spi0-tx {
1394                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1395                         };
1396                         spi0_rx: spi0-rx {
1397                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1398                         };
1399                         spi0_cs1: spi0-cs1 {
1400                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1401                         };
1402                 };
1403                 spi1 {
1404                         spi1_clk: spi1-clk {
1405                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1406                         };
1407                         spi1_cs0: spi1-cs0 {
1408                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1409                         };
1410                         spi1_rx: spi1-rx {
1411                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1412                         };
1413                         spi1_tx: spi1-tx {
1414                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1415                         };
1416                 };
1417
1418                 spi2 {
1419                         spi2_cs1: spi2-cs1 {
1420                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1421                         };
1422                         spi2_clk: spi2-clk {
1423                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1424                         };
1425                         spi2_cs0: spi2-cs0 {
1426                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1427                         };
1428                         spi2_rx: spi2-rx {
1429                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1430                         };
1431                         spi2_tx: spi2-tx {
1432                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1433                         };
1434                 };
1435
1436                 uart0 {
1437                         uart0_xfer: uart0-xfer {
1438                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1439                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1440                         };
1441
1442                         uart0_cts: uart0-cts {
1443                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1444                         };
1445
1446                         uart0_rts: uart0-rts {
1447                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1448                         };
1449                 };
1450
1451                 uart1 {
1452                         uart1_xfer: uart1-xfer {
1453                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1454                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1455                         };
1456
1457                         uart1_cts: uart1-cts {
1458                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1459                         };
1460
1461                         uart1_rts: uart1-rts {
1462                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1463                         };
1464                 };
1465
1466                 uart2 {
1467                         uart2_xfer: uart2-xfer {
1468                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1469                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1470                         };
1471                         /* no rts / cts for uart2 */
1472                 };
1473
1474                 uart3 {
1475                         uart3_xfer: uart3-xfer {
1476                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1477                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1478                         };
1479
1480                         uart3_cts: uart3-cts {
1481                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1482                         };
1483
1484                         uart3_rts: uart3-rts {
1485                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1486                         };
1487                 };
1488
1489                 uart4 {
1490                         uart4_xfer: uart4-xfer {
1491                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1492                                                 <5 13 3 &pcfg_pull_none>;
1493                         };
1494
1495                         uart4_cts: uart4-cts {
1496                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1497                         };
1498
1499                         uart4_rts: uart4-rts {
1500                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1501                         };
1502                 };
1503
1504                 tsadc {
1505                         otp_gpio: otp-gpio {
1506                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1507                         };
1508
1509                         otp_out: otp-out {
1510                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1511                         };
1512                 };
1513
1514                 pwm0 {
1515                         pwm0_pin: pwm0-pin {
1516                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1517                         };
1518                 };
1519
1520                 pwm1 {
1521                         pwm1_pin: pwm1-pin {
1522                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1523                         };
1524                 };
1525
1526                 pwm2 {
1527                         pwm2_pin: pwm2-pin {
1528                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1529                         };
1530                 };
1531
1532                 pwm3 {
1533                         pwm3_pin: pwm3-pin {
1534                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1535                         };
1536                 };
1537
1538                 gmac {
1539                         rgmii_pins: rgmii-pins {
1540                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1541                                                 <3 31 3 &pcfg_pull_none>,
1542                                                 <3 26 3 &pcfg_pull_none>,
1543                                                 <3 27 3 &pcfg_pull_none>,
1544                                                 <3 28 3 &pcfg_pull_none_12ma>,
1545                                                 <3 29 3 &pcfg_pull_none_12ma>,
1546                                                 <3 24 3 &pcfg_pull_none_12ma>,
1547                                                 <3 25 3 &pcfg_pull_none_12ma>,
1548                                                 <4 0 3 &pcfg_pull_none>,
1549                                                 <4 5 3 &pcfg_pull_none>,
1550                                                 <4 6 3 &pcfg_pull_none>,
1551                                                 <4 9 3 &pcfg_pull_none_12ma>,
1552                                                 <4 4 3 &pcfg_pull_none_12ma>,
1553                                                 <4 1 3 &pcfg_pull_none>,
1554                                                 <4 3 3 &pcfg_pull_none>;
1555                         };
1556
1557                         rmii_pins: rmii-pins {
1558                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1559                                                 <3 31 3 &pcfg_pull_none>,
1560                                                 <3 28 3 &pcfg_pull_none>,
1561                                                 <3 29 3 &pcfg_pull_none>,
1562                                                 <4 0 3 &pcfg_pull_none>,
1563                                                 <4 5 3 &pcfg_pull_none>,
1564                                                 <4 4 3 &pcfg_pull_none>,
1565                                                 <4 1 3 &pcfg_pull_none>,
1566                                                 <4 2 3 &pcfg_pull_none>,
1567                                                 <4 3 3 &pcfg_pull_none>;
1568                         };
1569                 };
1570
1571                 spdif {
1572                         spdif_tx: spdif-tx {
1573                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1574                         };
1575                 };
1576         };
1577 };