2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3288-cru.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/power/rk3288-power.h>
48 #include <dt-bindings/soc/rockchip_boot-mode.h>
49 #include "skeleton.dtsi"
52 compatible = "rockchip,rk3288";
54 interrupt-parent = <&gic>;
78 compatible = "arm,cortex-a12-pmu";
79 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
83 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
89 enable-method = "rockchip,rk3066-smp";
90 rockchip,pmu = <&pmu>;
94 compatible = "arm,cortex-a12";
96 resets = <&cru SRST_CORE0>;
112 #cooling-cells = <2>; /* min followed by max */
113 clock-latency = <40000>;
114 clocks = <&cru ARMCLK>;
118 compatible = "arm,cortex-a12";
120 resets = <&cru SRST_CORE1>;
124 compatible = "arm,cortex-a12";
126 resets = <&cru SRST_CORE2>;
130 compatible = "arm,cortex-a12";
132 resets = <&cru SRST_CORE3>;
137 compatible = "arm,amba-bus";
138 #address-cells = <1>;
142 dmac_peri: dma-controller@ff250000 {
143 compatible = "arm,pl330", "arm,primecell";
144 reg = <0xff250000 0x4000>;
145 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
148 arm,pl330-broken-no-flushp;
149 peripherals-req-type-burst;
150 clocks = <&cru ACLK_DMAC2>;
151 clock-names = "apb_pclk";
154 dmac_bus_ns: dma-controller@ff600000 {
155 compatible = "arm,pl330", "arm,primecell";
156 reg = <0xff600000 0x4000>;
157 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
160 arm,pl330-broken-no-flushp;
161 peripherals-req-type-burst;
162 clocks = <&cru ACLK_DMAC1>;
163 clock-names = "apb_pclk";
167 dmac_bus_s: dma-controller@ffb20000 {
168 compatible = "arm,pl330", "arm,primecell";
169 reg = <0xffb20000 0x4000>;
170 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
171 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
173 arm,pl330-broken-no-flushp;
174 peripherals-req-type-burst;
175 clocks = <&cru ACLK_DMAC1>;
176 clock-names = "apb_pclk";
181 #address-cells = <1>;
186 * The rk3288 cannot use the memory area above 0xfe000000
187 * for dma operations for some reason. While there is
188 * probably a better solution available somewhere, we
189 * haven't found it yet and while devices with 2GB of ram
190 * are not affected, this issue prevents 4GB from booting.
191 * So to make these devices at least bootable, block
192 * this area for the time being until the real solution
195 dma-unusable@fe000000 {
196 reg = <0xfe000000 0x1000000>;
201 compatible = "fixed-clock";
202 clock-frequency = <24000000>;
203 clock-output-names = "xin24m";
208 compatible = "arm,armv7-timer";
209 arm,cpu-registers-not-fw-configured;
210 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
211 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
212 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
213 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
214 clock-frequency = <24000000>;
217 timer: timer@ff810000 {
218 compatible = "rockchip,rk3288-timer";
219 reg = <0xff810000 0x20>;
220 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&xin24m>, <&cru PCLK_TIMER>;
222 clock-names = "timer", "pclk";
226 compatible = "rockchip,display-subsystem";
227 ports = <&vopl_out>, <&vopb_out>;
230 sdmmc: dwmmc@ff0c0000 {
231 compatible = "rockchip,rk3288-dw-mshc";
232 clock-freq-min-max = <400000 150000000>;
233 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
234 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
235 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
236 fifo-depth = <0x100>;
237 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
238 reg = <0xff0c0000 0x4000>;
242 sdio0: dwmmc@ff0d0000 {
243 compatible = "rockchip,rk3288-dw-mshc";
244 clock-freq-min-max = <400000 150000000>;
245 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
246 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
247 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
248 fifo-depth = <0x100>;
249 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
250 reg = <0xff0d0000 0x4000>;
254 sdio1: dwmmc@ff0e0000 {
255 compatible = "rockchip,rk3288-dw-mshc";
256 clock-freq-min-max = <400000 150000000>;
257 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
258 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
259 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
260 fifo-depth = <0x100>;
261 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
262 reg = <0xff0e0000 0x4000>;
266 emmc: dwmmc@ff0f0000 {
267 compatible = "rockchip,rk3288-dw-mshc";
268 clock-freq-min-max = <400000 150000000>;
269 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
270 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
271 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
272 fifo-depth = <0x100>;
273 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
274 reg = <0xff0f0000 0x4000>;
279 saradc: saradc@ff100000 {
280 compatible = "rockchip,saradc";
281 reg = <0xff100000 0x100>;
282 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
283 #io-channel-cells = <1>;
284 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
285 clock-names = "saradc", "apb_pclk";
286 resets = <&cru SRST_SARADC>;
287 reset-names = "saradc-apb";
292 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
293 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
294 clock-names = "spiclk", "apb_pclk";
295 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
296 dma-names = "tx", "rx";
297 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
300 reg = <0xff110000 0x1000>;
301 #address-cells = <1>;
307 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
308 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
309 clock-names = "spiclk", "apb_pclk";
310 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
311 dma-names = "tx", "rx";
312 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
313 pinctrl-names = "default";
314 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
315 reg = <0xff120000 0x1000>;
316 #address-cells = <1>;
322 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
323 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
324 clock-names = "spiclk", "apb_pclk";
325 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
326 dma-names = "tx", "rx";
327 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
328 pinctrl-names = "default";
329 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
330 reg = <0xff130000 0x1000>;
331 #address-cells = <1>;
337 compatible = "rockchip,rk3288-i2c";
338 reg = <0xff140000 0x1000>;
339 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
340 #address-cells = <1>;
343 clocks = <&cru PCLK_I2C1>;
344 pinctrl-names = "default";
345 pinctrl-0 = <&i2c1_xfer>;
350 compatible = "rockchip,rk3288-i2c";
351 reg = <0xff150000 0x1000>;
352 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
353 #address-cells = <1>;
356 clocks = <&cru PCLK_I2C3>;
357 pinctrl-names = "default";
358 pinctrl-0 = <&i2c3_xfer>;
363 compatible = "rockchip,rk3288-i2c";
364 reg = <0xff160000 0x1000>;
365 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
366 #address-cells = <1>;
369 clocks = <&cru PCLK_I2C4>;
370 pinctrl-names = "default";
371 pinctrl-0 = <&i2c4_xfer>;
376 compatible = "rockchip,rk3288-i2c";
377 reg = <0xff170000 0x1000>;
378 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
379 #address-cells = <1>;
382 clocks = <&cru PCLK_I2C5>;
383 pinctrl-names = "default";
384 pinctrl-0 = <&i2c5_xfer>;
388 uart0: serial@ff180000 {
389 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
390 reg = <0xff180000 0x100>;
391 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
395 clock-names = "baudclk", "apb_pclk";
396 pinctrl-names = "default";
397 pinctrl-0 = <&uart0_xfer>;
401 uart1: serial@ff190000 {
402 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
403 reg = <0xff190000 0x100>;
404 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
407 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
408 clock-names = "baudclk", "apb_pclk";
409 pinctrl-names = "default";
410 pinctrl-0 = <&uart1_xfer>;
414 uart2: serial@ff690000 {
415 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
416 reg = <0xff690000 0x100>;
417 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
421 clock-names = "baudclk", "apb_pclk";
422 pinctrl-names = "default";
423 pinctrl-0 = <&uart2_xfer>;
427 uart3: serial@ff1b0000 {
428 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
429 reg = <0xff1b0000 0x100>;
430 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
434 clock-names = "baudclk", "apb_pclk";
435 pinctrl-names = "default";
436 pinctrl-0 = <&uart3_xfer>;
440 uart4: serial@ff1c0000 {
441 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
442 reg = <0xff1c0000 0x100>;
443 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
447 clock-names = "baudclk", "apb_pclk";
448 pinctrl-names = "default";
449 pinctrl-0 = <&uart4_xfer>;
454 reserve_thermal: reserve_thermal {
455 polling-delay-passive = <1000>; /* milliseconds */
456 polling-delay = <5000>; /* milliseconds */
458 thermal-sensors = <&tsadc 0>;
461 cpu_thermal: cpu_thermal {
462 polling-delay-passive = <100>; /* milliseconds */
463 polling-delay = <5000>; /* milliseconds */
465 thermal-sensors = <&tsadc 1>;
468 cpu_alert0: cpu_alert0 {
469 temperature = <70000>; /* millicelsius */
470 hysteresis = <2000>; /* millicelsius */
473 cpu_alert1: cpu_alert1 {
474 temperature = <75000>; /* millicelsius */
475 hysteresis = <2000>; /* millicelsius */
479 temperature = <90000>; /* millicelsius */
480 hysteresis = <2000>; /* millicelsius */
487 trip = <&cpu_alert0>;
489 <&cpu0 THERMAL_NO_LIMIT 6>;
492 trip = <&cpu_alert1>;
494 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
499 gpu_thermal: gpu_thermal {
500 polling-delay-passive = <100>; /* milliseconds */
501 polling-delay = <5000>; /* milliseconds */
503 thermal-sensors = <&tsadc 2>;
506 gpu_alert0: gpu_alert0 {
507 temperature = <70000>; /* millicelsius */
508 hysteresis = <2000>; /* millicelsius */
512 temperature = <90000>; /* millicelsius */
513 hysteresis = <2000>; /* millicelsius */
520 trip = <&gpu_alert0>;
522 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
528 tsadc: tsadc@ff280000 {
529 compatible = "rockchip,rk3288-tsadc";
530 reg = <0xff280000 0x100>;
531 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
532 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
533 clock-names = "tsadc", "apb_pclk";
534 resets = <&cru SRST_TSADC>;
535 reset-names = "tsadc-apb";
536 pinctrl-names = "init", "default", "sleep";
537 pinctrl-0 = <&otp_gpio>;
538 pinctrl-1 = <&otp_out>;
539 pinctrl-2 = <&otp_gpio>;
540 #thermal-sensor-cells = <1>;
541 rockchip,hw-tshut-temp = <95000>;
545 gmac: ethernet@ff290000 {
546 compatible = "rockchip,rk3288-gmac";
547 reg = <0xff290000 0x10000>;
548 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
549 interrupt-names = "macirq";
550 rockchip,grf = <&grf>;
551 clocks = <&cru SCLK_MAC>,
552 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
553 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
554 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
555 clock-names = "stmmaceth",
556 "mac_clk_rx", "mac_clk_tx",
557 "clk_mac_ref", "clk_mac_refout",
558 "aclk_mac", "pclk_mac";
559 resets = <&cru SRST_MAC>;
560 reset-names = "stmmaceth";
565 usb_host0_ehci: usb@ff500000 {
566 compatible = "generic-ehci";
567 reg = <0xff500000 0x100>;
568 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
569 clocks = <&cru HCLK_USBHOST0>;
570 clock-names = "usbhost";
576 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
578 usb_host1: usb@ff540000 {
579 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
581 reg = <0xff540000 0x40000>;
582 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&cru HCLK_USBHOST1>;
587 phy-names = "usb2-phy";
591 usb_otg: usb@ff580000 {
592 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
594 reg = <0xff580000 0x40000>;
595 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&cru HCLK_OTG0>;
599 g-np-tx-fifo-size = <16>;
600 g-rx-fifo-size = <275>;
601 g-tx-fifo-size = <256 128 128 64 64 32>;
604 phy-names = "usb2-phy";
608 usb_hsic: usb@ff5c0000 {
609 compatible = "generic-ehci";
610 reg = <0xff5c0000 0x100>;
611 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
612 clocks = <&cru HCLK_HSIC>;
613 clock-names = "usbhost";
618 compatible = "rockchip,rk3288-i2c";
619 reg = <0xff650000 0x1000>;
620 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
621 #address-cells = <1>;
624 clocks = <&cru PCLK_I2C0>;
625 pinctrl-names = "default";
626 pinctrl-0 = <&i2c0_xfer>;
631 compatible = "rockchip,rk3288-i2c";
632 reg = <0xff660000 0x1000>;
633 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
634 #address-cells = <1>;
637 clocks = <&cru PCLK_I2C2>;
638 pinctrl-names = "default";
639 pinctrl-0 = <&i2c2_xfer>;
644 compatible = "rockchip,rk3288-pwm";
645 reg = <0xff680000 0x10>;
647 pinctrl-names = "default";
648 pinctrl-0 = <&pwm0_pin>;
649 clocks = <&cru PCLK_PWM>;
655 compatible = "rockchip,rk3288-pwm";
656 reg = <0xff680010 0x10>;
658 pinctrl-names = "default";
659 pinctrl-0 = <&pwm1_pin>;
660 clocks = <&cru PCLK_PWM>;
666 compatible = "rockchip,rk3288-pwm";
667 reg = <0xff680020 0x10>;
669 pinctrl-names = "default";
670 pinctrl-0 = <&pwm2_pin>;
671 clocks = <&cru PCLK_PWM>;
677 compatible = "rockchip,rk3288-pwm";
678 reg = <0xff680030 0x10>;
680 pinctrl-names = "default";
681 pinctrl-0 = <&pwm3_pin>;
682 clocks = <&cru PCLK_PWM>;
687 bus_intmem@ff700000 {
688 compatible = "mmio-sram";
689 reg = <0xff700000 0x18000>;
690 #address-cells = <1>;
692 ranges = <0 0xff700000 0x18000>;
694 compatible = "rockchip,rk3066-smp-sram";
700 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
701 reg = <0xff720000 0x1000>;
704 qos_gpu_r: qos@ffaa0000 {
705 compatible = "syscon";
706 reg = <0xffaa0000 0x20>;
709 qos_gpu_w: qos@ffaa0080 {
710 compatible = "syscon";
711 reg = <0xffaa0080 0x20>;
714 qos_vio1_vop: qos@ffad0000 {
715 compatible = "syscon";
716 reg = <0xffad0000 0x20>;
719 qos_vio1_isp_w0: qos@ffad0100 {
720 compatible = "syscon";
721 reg = <0xffad0100 0x20>;
724 qos_vio1_isp_w1: qos@ffad0180 {
725 compatible = "syscon";
726 reg = <0xffad0180 0x20>;
729 qos_vio0_vop: qos@ffad0400 {
730 compatible = "syscon";
731 reg = <0xffad0400 0x20>;
734 qos_vio0_vip: qos@ffad0480 {
735 compatible = "syscon";
736 reg = <0xffad0480 0x20>;
739 qos_vio0_iep: qos@ffad0500 {
740 compatible = "syscon";
741 reg = <0xffad0500 0x20>;
744 qos_vio2_rga_r: qos@ffad0800 {
745 compatible = "syscon";
746 reg = <0xffad0800 0x20>;
749 qos_vio2_rga_w: qos@ffad0880 {
750 compatible = "syscon";
751 reg = <0xffad0880 0x20>;
754 qos_vio1_isp_r: qos@ffad0900 {
755 compatible = "syscon";
756 reg = <0xffad0900 0x20>;
759 qos_video: qos@ffae0000 {
760 compatible = "syscon";
761 reg = <0xffae0000 0x20>;
764 qos_hevc_r: qos@ffaf0000 {
765 compatible = "syscon";
766 reg = <0xffaf0000 0x20>;
769 qos_hevc_w: qos@ffaf0080 {
770 compatible = "syscon";
771 reg = <0xffaf0080 0x20>;
774 pmu: power-management@ff730000 {
775 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
776 reg = <0xff730000 0x100>;
778 power: power-controller {
779 compatible = "rockchip,rk3288-power-controller";
780 #power-domain-cells = <1>;
781 #address-cells = <1>;
785 * Note: Although SCLK_* are the working clocks
786 * of device without including on the NOC, needed for
789 * The clocks on the which NOC:
790 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
791 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
792 * ACLK_RGA is on ACLK_RGA_NIU.
793 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
795 * Which clock are device clocks:
797 * *_IEP IEP:Image Enhancement Processor
798 * *_ISP ISP:Image Signal Processing
799 * *_VIP VIP:Video Input Processor
800 * *_VOP* VOP:Visual Output Processor
807 pd_vio@RK3288_PD_VIO {
808 reg = <RK3288_PD_VIO>;
809 clocks = <&cru ACLK_IEP>,
823 <&cru PCLK_EDP_CTRL>,
824 <&cru PCLK_HDMI_CTRL>,
825 <&cru PCLK_LVDS_PHY>,
826 <&cru PCLK_MIPI_CSI>,
827 <&cru PCLK_MIPI_DSI0>,
828 <&cru PCLK_MIPI_DSI1>,
834 pm_qos = <&qos_vio0_iep>,
846 * Note: The following 3 are HEVC(H.265) clocks,
847 * and on the ACLK_HEVC_NIU (NOC).
849 pd_hevc@RK3288_PD_HEVC {
850 reg = <RK3288_PD_HEVC>;
851 clocks = <&cru ACLK_HEVC>,
852 <&cru SCLK_HEVC_CABAC>,
853 <&cru SCLK_HEVC_CORE>;
854 pm_qos = <&qos_hevc_r>,
859 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
860 * (video endecoder & decoder) clocks that on the
861 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
863 pd_video@RK3288_PD_VIDEO {
864 reg = <RK3288_PD_VIDEO>;
865 clocks = <&cru ACLK_VCODEC>,
867 pm_qos = <&qos_video>;
871 * Note: ACLK_GPU is the GPU clock,
872 * and on the ACLK_GPU_NIU (NOC).
874 pd_gpu@RK3288_PD_GPU {
875 reg = <RK3288_PD_GPU>;
876 clocks = <&cru ACLK_GPU>;
877 pm_qos = <&qos_gpu_r>,
883 compatible = "syscon-reboot-mode";
885 mode-normal = <BOOT_NORMAL>;
886 mode-recovery = <BOOT_RECOVERY>;
887 mode-bootloader = <BOOT_FASTBOOT>;
888 mode-loader = <BOOT_LOADER>;
889 mode-ums = <BOOT_UMS>;
893 sgrf: syscon@ff740000 {
894 compatible = "rockchip,rk3288-sgrf", "syscon";
895 reg = <0xff740000 0x1000>;
898 cru: clock-controller@ff760000 {
899 compatible = "rockchip,rk3288-cru";
900 reg = <0xff760000 0x1000>;
901 rockchip,grf = <&grf>;
904 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
905 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
906 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
907 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
908 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
910 assigned-clock-rates = <0>, <0>,
911 <594000000>, <400000000>,
912 <500000000>, <300000000>,
913 <150000000>, <75000000>,
914 <300000000>, <150000000>,
916 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
919 grf: syscon@ff770000 {
920 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
921 reg = <0xff770000 0x1000>;
924 compatible = "rockchip,rk3288-dp-phy";
925 clocks = <&cru SCLK_EDP_24M>;
931 io_domains: io-domains {
932 compatible = "rockchip,rk3288-io-voltage-domain";
937 compatible = "rockchip,rk3288-usb-phy";
938 #address-cells = <1>;
942 usbphy0: usb-phy@320 {
945 clocks = <&cru SCLK_OTGPHY0>;
946 clock-names = "phyclk";
948 resets = <&cru SRST_USBOTG_PHY>;
949 reset-names = "phy-reset";
952 usbphy1: usb-phy@334 {
955 clocks = <&cru SCLK_OTGPHY1>;
956 clock-names = "phyclk";
960 usbphy2: usb-phy@348 {
963 clocks = <&cru SCLK_OTGPHY2>;
964 clock-names = "phyclk";
966 resets = <&cru SRST_USBHOST1_PHY>;
967 reset-names = "phy-reset";
972 wdt: watchdog@ff800000 {
973 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
974 reg = <0xff800000 0x100>;
975 clocks = <&cru PCLK_WDT>;
976 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
980 spdif: sound@ff88b0000 {
981 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
982 reg = <0xff8b0000 0x10000>;
983 #sound-dai-cells = <0>;
984 clock-names = "hclk", "mclk";
985 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
986 dmas = <&dmac_bus_s 3>;
988 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
989 pinctrl-names = "default";
990 pinctrl-0 = <&spdif_tx>;
991 rockchip,grf = <&grf>;
996 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
997 reg = <0xff890000 0x10000>;
998 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
999 #address-cells = <1>;
1001 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
1002 dma-names = "tx", "rx";
1003 clock-names = "i2s_hclk", "i2s_clk";
1004 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
1005 pinctrl-names = "default";
1006 pinctrl-0 = <&i2s0_bus>;
1007 rockchip,playback-channels = <8>;
1008 rockchip,capture-channels = <2>;
1009 status = "disabled";
1012 vopb: vop@ff930000 {
1013 compatible = "rockchip,rk3288-vop";
1014 reg = <0xff930000 0x19c>;
1015 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1016 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1017 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1018 power-domains = <&power RK3288_PD_VIO>;
1019 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1020 reset-names = "axi", "ahb", "dclk";
1021 iommus = <&vopb_mmu>;
1022 status = "disabled";
1025 #address-cells = <1>;
1028 vopb_out_hdmi: endpoint@0 {
1030 remote-endpoint = <&hdmi_in_vopb>;
1033 vopb_out_edp: endpoint@1 {
1035 remote-endpoint = <&edp_in_vopb>;
1038 vopb_out_mipi: endpoint@2 {
1040 remote-endpoint = <&mipi_in_vopb>;
1043 vopb_out_lvds: endpoint@3 {
1045 remote-endpoint = <&lvds_in_vopb>;
1050 vopb_mmu: iommu@ff930300 {
1051 compatible = "rockchip,iommu";
1052 reg = <0xff930300 0x100>;
1053 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1054 interrupt-names = "vopb_mmu";
1055 power-domains = <&power RK3288_PD_VIO>;
1057 status = "disabled";
1060 vopl: vop@ff940000 {
1061 compatible = "rockchip,rk3288-vop";
1062 reg = <0xff940000 0x19c>;
1063 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1064 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1065 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1066 power-domains = <&power RK3288_PD_VIO>;
1067 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1068 reset-names = "axi", "ahb", "dclk";
1069 iommus = <&vopl_mmu>;
1070 status = "disabled";
1073 #address-cells = <1>;
1076 vopl_out_hdmi: endpoint@0 {
1078 remote-endpoint = <&hdmi_in_vopl>;
1081 vopl_out_edp: endpoint@1 {
1083 remote-endpoint = <&edp_in_vopl>;
1086 vopl_out_mipi: endpoint@2 {
1088 remote-endpoint = <&mipi_in_vopl>;
1091 vopl_out_lvds: endpoint@3 {
1093 remote-endpoint = <&lvds_in_vopl>;
1099 vopl_mmu: iommu@ff940300 {
1100 compatible = "rockchip,iommu";
1101 reg = <0xff940300 0x100>;
1102 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1103 interrupt-names = "vopl_mmu";
1104 power-domains = <&power RK3288_PD_VIO>;
1106 status = "disabled";
1109 mipi_dsi: mipi@ff960000 {
1110 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1111 reg = <0xff960000 0x4000>;
1112 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1113 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1114 clock-names = "ref", "pclk";
1115 power-domains = <&power RK3288_PD_VIO>;
1116 rockchip,grf = <&grf>;
1117 #address-cells = <1>;
1119 status = "disabled";
1123 #address-cells = <1>;
1125 mipi_in_vopb: endpoint@0 {
1127 remote-endpoint = <&vopb_out_mipi>;
1129 mipi_in_vopl: endpoint@1 {
1131 remote-endpoint = <&vopl_out_mipi>;
1138 compatible = "rockchip,rk3288-dp";
1139 reg = <0xff970000 0x4000>;
1140 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1141 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1142 clock-names = "dp", "pclk";
1145 resets = <&cru SRST_EDP>;
1147 rockchip,grf = <&grf>;
1148 status = "disabled";
1151 #address-cells = <1>;
1155 #address-cells = <1>;
1157 edp_in_vopb: endpoint@0 {
1159 remote-endpoint = <&vopb_out_edp>;
1161 edp_in_vopl: endpoint@1 {
1163 remote-endpoint = <&vopl_out_edp>;
1169 lvds: lvds@ff96c000 {
1170 compatible = "rockchip,rk3288-lvds";
1171 reg = <0xff96c000 0x4000>;
1172 clocks = <&cru PCLK_LVDS_PHY>;
1173 clock-names = "pclk_lvds";
1174 pinctrl-names = "default";
1175 pinctrl-0 = <&lcdc0_ctl>;
1176 power-domains = <&power RK3288_PD_VIO>;
1177 rockchip,grf = <&grf>;
1178 status = "disabled";
1181 #address-cells = <1>;
1187 #address-cells = <1>;
1190 lvds_in_vopb: endpoint@0 {
1192 remote-endpoint = <&vopb_out_lvds>;
1194 lvds_in_vopl: endpoint@1 {
1196 remote-endpoint = <&vopl_out_lvds>;
1202 hdmi: hdmi@ff980000 {
1203 compatible = "rockchip,rk3288-dw-hdmi";
1204 reg = <0xff980000 0x20000>;
1206 rockchip,grf = <&grf>;
1207 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1208 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1209 clock-names = "iahb", "isfr";
1210 power-domains = <&power RK3288_PD_VIO>;
1211 status = "disabled";
1215 #address-cells = <1>;
1217 hdmi_in_vopb: endpoint@0 {
1219 remote-endpoint = <&vopb_out_hdmi>;
1221 hdmi_in_vopl: endpoint@1 {
1223 remote-endpoint = <&vopl_out_hdmi>;
1230 compatible = "arm,malit764",
1234 reg = <0xffa30000 0x10000>;
1235 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1236 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1237 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1238 interrupt-names = "JOB", "MMU", "GPU";
1239 clocks = <&cru ACLK_GPU>;
1240 clock-names = "clk_mali";
1241 operating-points = <
1244 /* 500000 1200000 - See crosbug.com/p/33857 */
1250 #cooling-cells = <2>; /* min followed by max */
1251 power-domains = <&power RK3288_PD_GPU>;
1252 status = "disabled";
1255 vpu: video-codec@ff9a0000 {
1256 compatible = "rockchip,rk3288-vpu";
1257 reg = <0xff9a0000 0x800>;
1258 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1259 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1260 interrupt-names = "vepu", "vdpu";
1261 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1262 clock-names = "aclk", "hclk";
1263 power-domains = <&power RK3288_PD_VIDEO>;
1264 iommus = <&vpu_mmu>;
1265 assigned-clocks = <&cru ACLK_VCODEC>;
1266 assigned-clock-rates = <400000000>;
1267 status = "disabled";
1270 vpu_service: vpu-service@ff9a0000 {
1271 compatible = "rockchip,vpu_service";
1272 reg = <0xff9a0000 0x800>;
1273 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1275 interrupt-names = "irq_enc", "irq_dec";
1276 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1277 clock-names = "aclk_vcodec", "hclk_vcodec";
1278 power-domains = <&power RK3288_PD_VIDEO>;
1279 rockchip,grf = <&grf>;
1280 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
1281 reset-names = "video_a", "video_h";
1282 iommus = <&vpu_mmu>;
1283 iommu_enabled = <1>;
1285 status = "disabled";
1288 vpu_mmu: iommu@ff9a0800 {
1289 compatible = "rockchip,iommu";
1290 reg = <0xff9a0800 0x100>;
1291 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1292 interrupt-names = "vpu_mmu";
1293 power-domains = <&power RK3288_PD_VIDEO>;
1297 hevc_service: hevc-service@ff9c0000 {
1298 compatible = "rockchip,hevc_service";
1299 reg = <0xff9c0000 0x400>;
1300 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1301 interrupt-names = "irq_dec";
1302 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1303 <&cru SCLK_HEVC_CORE>,
1304 <&cru SCLK_HEVC_CABAC>;
1305 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
1308 * The 4K hevc would also work well with 500/125/300/300,
1309 * no more err irq and reset request.
1311 assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1312 <&cru SCLK_HEVC_CORE>,
1313 <&cru SCLK_HEVC_CABAC>;
1314 assigned-clock-rates = <400000000>, <100000000>,
1315 <300000000>, <300000000>;
1317 resets = <&cru SRST_HEVC>;
1318 reset-names = "video";
1319 power-domains = <&power RK3288_PD_HEVC>;
1320 rockchip,grf = <&grf>;
1322 iommus = <&hevc_mmu>;
1323 iommu_enabled = <1>;
1324 status = "disabled";
1327 hevc_mmu: iommu@ff9c0440 {
1328 compatible = "rockchip,iommu";
1329 reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
1330 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1331 interrupt-names = "hevc_mmu";
1332 power-domains = <&power RK3288_PD_HEVC>;
1336 gic: interrupt-controller@ffc01000 {
1337 compatible = "arm,gic-400";
1338 interrupt-controller;
1339 #interrupt-cells = <3>;
1340 #address-cells = <0>;
1342 reg = <0xffc01000 0x1000>,
1343 <0xffc02000 0x1000>,
1344 <0xffc04000 0x2000>,
1345 <0xffc06000 0x2000>;
1346 interrupts = <GIC_PPI 9 0xf04>;
1349 efuse: efuse@ffb40000 {
1350 compatible = "rockchip,rockchip-efuse";
1351 reg = <0xffb40000 0x20>;
1352 #address-cells = <1>;
1354 clocks = <&cru PCLK_EFUSE256>;
1355 clock-names = "pclk_efuse";
1357 cpu_leakage: cpu_leakage@17 {
1362 cif_isp0: cif_isp@ff910000 {
1363 compatible = "rockchip,rk3288-cif-isp";
1364 rockchip,grf = <&grf>;
1365 reg = <0xff910000 0x10000>, <0xff968000 0x4000>;
1366 reg-names = "register", "csihost-register";
1367 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1368 <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
1369 <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
1370 <&cru SCLK_MIPIDSI_24M>;
1371 clock-names = "aclk_isp", "hclk_isp",
1372 "sclk_isp", "sclk_isp_jpe",
1373 "pclk_mipi_csi", "pclk_isp_in",
1375 resets = <&cru SRST_ISP>;
1376 reset-names = "rst_isp";
1377 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1378 interrupt-names = "cif_isp10_irq";
1379 status = "disabled";
1383 compatible = "rockchip,rk3288-pinctrl";
1384 rockchip,grf = <&grf>;
1385 rockchip,pmu = <&pmu>;
1386 #address-cells = <1>;
1390 gpio0: gpio0@ff750000 {
1391 compatible = "rockchip,gpio-bank";
1392 reg = <0xff750000 0x100>;
1393 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1394 clocks = <&cru PCLK_GPIO0>;
1399 interrupt-controller;
1400 #interrupt-cells = <2>;
1403 gpio1: gpio1@ff780000 {
1404 compatible = "rockchip,gpio-bank";
1405 reg = <0xff780000 0x100>;
1406 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1407 clocks = <&cru PCLK_GPIO1>;
1412 interrupt-controller;
1413 #interrupt-cells = <2>;
1416 gpio2: gpio2@ff790000 {
1417 compatible = "rockchip,gpio-bank";
1418 reg = <0xff790000 0x100>;
1419 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1420 clocks = <&cru PCLK_GPIO2>;
1425 interrupt-controller;
1426 #interrupt-cells = <2>;
1429 gpio3: gpio3@ff7a0000 {
1430 compatible = "rockchip,gpio-bank";
1431 reg = <0xff7a0000 0x100>;
1432 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1433 clocks = <&cru PCLK_GPIO3>;
1438 interrupt-controller;
1439 #interrupt-cells = <2>;
1442 gpio4: gpio4@ff7b0000 {
1443 compatible = "rockchip,gpio-bank";
1444 reg = <0xff7b0000 0x100>;
1445 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1446 clocks = <&cru PCLK_GPIO4>;
1451 interrupt-controller;
1452 #interrupt-cells = <2>;
1455 gpio5: gpio5@ff7c0000 {
1456 compatible = "rockchip,gpio-bank";
1457 reg = <0xff7c0000 0x100>;
1458 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1459 clocks = <&cru PCLK_GPIO5>;
1464 interrupt-controller;
1465 #interrupt-cells = <2>;
1468 gpio6: gpio6@ff7d0000 {
1469 compatible = "rockchip,gpio-bank";
1470 reg = <0xff7d0000 0x100>;
1471 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1472 clocks = <&cru PCLK_GPIO6>;
1477 interrupt-controller;
1478 #interrupt-cells = <2>;
1481 gpio7: gpio7@ff7e0000 {
1482 compatible = "rockchip,gpio-bank";
1483 reg = <0xff7e0000 0x100>;
1484 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1485 clocks = <&cru PCLK_GPIO7>;
1490 interrupt-controller;
1491 #interrupt-cells = <2>;
1494 gpio8: gpio8@ff7f0000 {
1495 compatible = "rockchip,gpio-bank";
1496 reg = <0xff7f0000 0x100>;
1497 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1498 clocks = <&cru PCLK_GPIO8>;
1503 interrupt-controller;
1504 #interrupt-cells = <2>;
1508 hdmi_ddc: hdmi-ddc {
1509 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1510 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1514 pcfg_pull_up: pcfg-pull-up {
1518 pcfg_pull_down: pcfg-pull-down {
1522 pcfg_pull_none: pcfg-pull-none {
1526 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1528 drive-strength = <12>;
1532 global_pwroff: global-pwroff {
1533 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1536 ddrio_pwroff: ddrio-pwroff {
1537 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1540 ddr0_retention: ddr0-retention {
1541 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1544 ddr1_retention: ddr1-retention {
1545 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1551 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1556 i2c0_xfer: i2c0-xfer {
1557 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1558 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1563 i2c1_xfer: i2c1-xfer {
1564 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1565 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1570 i2c2_xfer: i2c2-xfer {
1571 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1572 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1577 i2c3_xfer: i2c3-xfer {
1578 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1579 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1584 i2c4_xfer: i2c4-xfer {
1585 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1586 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1591 i2c5_xfer: i2c5-xfer {
1592 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1593 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1598 i2s0_bus: i2s0-bus {
1599 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1600 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1601 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1602 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1603 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1604 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1609 lcdc0_ctl: lcdc0-ctl {
1610 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1611 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1612 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1613 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1618 sdmmc_clk: sdmmc-clk {
1619 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1622 sdmmc_cmd: sdmmc-cmd {
1623 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1626 sdmmc_cd: sdmcc-cd {
1627 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1630 sdmmc_bus1: sdmmc-bus1 {
1631 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1634 sdmmc_bus4: sdmmc-bus4 {
1635 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1636 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1637 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1638 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1643 sdio0_bus1: sdio0-bus1 {
1644 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1647 sdio0_bus4: sdio0-bus4 {
1648 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1649 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1650 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1651 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1654 sdio0_cmd: sdio0-cmd {
1655 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1658 sdio0_clk: sdio0-clk {
1659 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1662 sdio0_cd: sdio0-cd {
1663 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1666 sdio0_wp: sdio0-wp {
1667 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1670 sdio0_pwr: sdio0-pwr {
1671 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1674 sdio0_bkpwr: sdio0-bkpwr {
1675 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1678 sdio0_int: sdio0-int {
1679 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1684 sdio1_bus1: sdio1-bus1 {
1685 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1688 sdio1_bus4: sdio1-bus4 {
1689 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1690 <3 25 4 &pcfg_pull_up>,
1691 <3 26 4 &pcfg_pull_up>,
1692 <3 27 4 &pcfg_pull_up>;
1695 sdio1_cd: sdio1-cd {
1696 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1699 sdio1_wp: sdio1-wp {
1700 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1703 sdio1_bkpwr: sdio1-bkpwr {
1704 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1707 sdio1_int: sdio1-int {
1708 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1711 sdio1_cmd: sdio1-cmd {
1712 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1715 sdio1_clk: sdio1-clk {
1716 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1719 sdio1_pwr: sdio1-pwr {
1720 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1725 emmc_clk: emmc-clk {
1726 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1729 emmc_cmd: emmc-cmd {
1730 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1733 emmc_pwr: emmc-pwr {
1734 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1737 emmc_bus1: emmc-bus1 {
1738 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1741 emmc_bus4: emmc-bus4 {
1742 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1743 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1744 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1745 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1748 emmc_bus8: emmc-bus8 {
1749 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1750 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1751 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1752 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1753 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1754 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1755 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1756 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1761 spi0_clk: spi0-clk {
1762 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1764 spi0_cs0: spi0-cs0 {
1765 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1768 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1771 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1773 spi0_cs1: spi0-cs1 {
1774 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1778 spi1_clk: spi1-clk {
1779 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1781 spi1_cs0: spi1-cs0 {
1782 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1785 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1788 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1793 spi2_cs1: spi2-cs1 {
1794 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1796 spi2_clk: spi2-clk {
1797 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1799 spi2_cs0: spi2-cs0 {
1800 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1803 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1806 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1811 uart0_xfer: uart0-xfer {
1812 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1813 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1816 uart0_cts: uart0-cts {
1817 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1820 uart0_rts: uart0-rts {
1821 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1826 uart1_xfer: uart1-xfer {
1827 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1828 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1831 uart1_cts: uart1-cts {
1832 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1835 uart1_rts: uart1-rts {
1836 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1841 uart2_xfer: uart2-xfer {
1842 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1843 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1845 /* no rts / cts for uart2 */
1849 uart3_xfer: uart3-xfer {
1850 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1851 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1854 uart3_cts: uart3-cts {
1855 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1858 uart3_rts: uart3-rts {
1859 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1864 uart4_xfer: uart4-xfer {
1865 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1866 <5 13 3 &pcfg_pull_none>;
1869 uart4_cts: uart4-cts {
1870 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1873 uart4_rts: uart4-rts {
1874 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1879 otp_gpio: otp-gpio {
1880 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1884 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1889 pwm0_pin: pwm0-pin {
1890 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1895 pwm1_pin: pwm1-pin {
1896 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1901 pwm2_pin: pwm2-pin {
1902 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1907 pwm3_pin: pwm3-pin {
1908 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1913 rgmii_pins: rgmii-pins {
1914 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1915 <3 31 3 &pcfg_pull_none>,
1916 <3 26 3 &pcfg_pull_none>,
1917 <3 27 3 &pcfg_pull_none>,
1918 <3 28 3 &pcfg_pull_none_12ma>,
1919 <3 29 3 &pcfg_pull_none_12ma>,
1920 <3 24 3 &pcfg_pull_none_12ma>,
1921 <3 25 3 &pcfg_pull_none_12ma>,
1922 <4 0 3 &pcfg_pull_none>,
1923 <4 5 3 &pcfg_pull_none>,
1924 <4 6 3 &pcfg_pull_none>,
1925 <4 9 3 &pcfg_pull_none_12ma>,
1926 <4 4 3 &pcfg_pull_none_12ma>,
1927 <4 1 3 &pcfg_pull_none>,
1928 <4 3 3 &pcfg_pull_none>;
1931 rmii_pins: rmii-pins {
1932 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1933 <3 31 3 &pcfg_pull_none>,
1934 <3 28 3 &pcfg_pull_none>,
1935 <3 29 3 &pcfg_pull_none>,
1936 <4 0 3 &pcfg_pull_none>,
1937 <4 5 3 &pcfg_pull_none>,
1938 <4 4 3 &pcfg_pull_none>,
1939 <4 1 3 &pcfg_pull_none>,
1940 <4 2 3 &pcfg_pull_none>,
1941 <4 3 3 &pcfg_pull_none>;
1946 spdif_tx: spdif-tx {
1947 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1952 cif_dvp_d2d9: cif-dvp-d2d9 {
1953 rockchip,pins = <2 0 RK_FUNC_1 &pcfg_pull_none>,
1954 <2 1 RK_FUNC_1 &pcfg_pull_none>,
1955 <2 2 RK_FUNC_1 &pcfg_pull_none>,
1956 <2 3 RK_FUNC_1 &pcfg_pull_none>,
1957 <2 4 RK_FUNC_1 &pcfg_pull_none>,
1958 <2 5 RK_FUNC_1 &pcfg_pull_none>,
1959 <2 6 RK_FUNC_1 &pcfg_pull_none>,
1960 <2 7 RK_FUNC_1 &pcfg_pull_none>,
1961 <2 8 RK_FUNC_1 &pcfg_pull_none>,
1962 <2 9 RK_FUNC_1 &pcfg_pull_none>,
1963 <2 11 RK_FUNC_1 &pcfg_pull_none>;