2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3288-cru.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/power/rk3288-power.h>
48 #include "skeleton.dtsi"
51 compatible = "rockchip,rk3288";
53 interrupt-parent = <&gic>;
77 compatible = "arm,cortex-a12-pmu";
78 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
82 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
88 enable-method = "rockchip,rk3066-smp";
89 rockchip,pmu = <&pmu>;
93 compatible = "arm,cortex-a12";
95 resets = <&cru SRST_CORE0>;
111 #cooling-cells = <2>; /* min followed by max */
112 clock-latency = <40000>;
113 clocks = <&cru ARMCLK>;
117 compatible = "arm,cortex-a12";
119 resets = <&cru SRST_CORE1>;
123 compatible = "arm,cortex-a12";
125 resets = <&cru SRST_CORE2>;
129 compatible = "arm,cortex-a12";
131 resets = <&cru SRST_CORE3>;
136 compatible = "arm,amba-bus";
137 #address-cells = <1>;
141 dmac_peri: dma-controller@ff250000 {
142 compatible = "arm,pl330", "arm,primecell";
143 reg = <0xff250000 0x4000>;
144 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
147 arm,pl330-broken-no-flushp;
148 peripherals-req-type-burst;
149 clocks = <&cru ACLK_DMAC2>;
150 clock-names = "apb_pclk";
153 dmac_bus_ns: dma-controller@ff600000 {
154 compatible = "arm,pl330", "arm,primecell";
155 reg = <0xff600000 0x4000>;
156 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
159 arm,pl330-broken-no-flushp;
160 peripherals-req-type-burst;
161 clocks = <&cru ACLK_DMAC1>;
162 clock-names = "apb_pclk";
166 dmac_bus_s: dma-controller@ffb20000 {
167 compatible = "arm,pl330", "arm,primecell";
168 reg = <0xffb20000 0x4000>;
169 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
170 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
172 arm,pl330-broken-no-flushp;
173 peripherals-req-type-burst;
174 clocks = <&cru ACLK_DMAC1>;
175 clock-names = "apb_pclk";
180 #address-cells = <1>;
185 * The rk3288 cannot use the memory area above 0xfe000000
186 * for dma operations for some reason. While there is
187 * probably a better solution available somewhere, we
188 * haven't found it yet and while devices with 2GB of ram
189 * are not affected, this issue prevents 4GB from booting.
190 * So to make these devices at least bootable, block
191 * this area for the time being until the real solution
194 dma-unusable@fe000000 {
195 reg = <0xfe000000 0x1000000>;
200 compatible = "fixed-clock";
201 clock-frequency = <24000000>;
202 clock-output-names = "xin24m";
207 compatible = "rockchip,rk3288-dp-phy";
208 clocks = <&cru SCLK_EDP_24M>;
210 rockchip,grf = <&grf>;
216 compatible = "arm,armv7-timer";
217 arm,cpu-registers-not-fw-configured;
218 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
219 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
220 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
221 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
222 clock-frequency = <24000000>;
225 timer: timer@ff810000 {
226 compatible = "rockchip,rk3288-timer";
227 reg = <0xff810000 0x20>;
228 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&xin24m>, <&cru PCLK_TIMER>;
230 clock-names = "timer", "pclk";
234 compatible = "rockchip,display-subsystem";
235 ports = <&vopl_out>, <&vopb_out>;
238 sdmmc: dwmmc@ff0c0000 {
239 compatible = "rockchip,rk3288-dw-mshc";
240 clock-freq-min-max = <400000 150000000>;
241 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
242 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
243 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
244 fifo-depth = <0x100>;
245 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
246 reg = <0xff0c0000 0x4000>;
250 sdio0: dwmmc@ff0d0000 {
251 compatible = "rockchip,rk3288-dw-mshc";
252 clock-freq-min-max = <400000 150000000>;
253 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
254 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
255 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
256 fifo-depth = <0x100>;
257 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
258 reg = <0xff0d0000 0x4000>;
262 sdio1: dwmmc@ff0e0000 {
263 compatible = "rockchip,rk3288-dw-mshc";
264 clock-freq-min-max = <400000 150000000>;
265 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
266 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
267 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
268 fifo-depth = <0x100>;
269 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
270 reg = <0xff0e0000 0x4000>;
274 emmc: dwmmc@ff0f0000 {
275 compatible = "rockchip,rk3288-dw-mshc";
276 clock-freq-min-max = <400000 150000000>;
277 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
278 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
279 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
280 fifo-depth = <0x100>;
281 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
282 reg = <0xff0f0000 0x4000>;
287 saradc: saradc@ff100000 {
288 compatible = "rockchip,saradc";
289 reg = <0xff100000 0x100>;
290 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
291 #io-channel-cells = <1>;
292 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
293 clock-names = "saradc", "apb_pclk";
298 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
299 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
300 clock-names = "spiclk", "apb_pclk";
301 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
302 dma-names = "tx", "rx";
303 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
304 pinctrl-names = "default";
305 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
306 reg = <0xff110000 0x1000>;
307 #address-cells = <1>;
313 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
314 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
315 clock-names = "spiclk", "apb_pclk";
316 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
317 dma-names = "tx", "rx";
318 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
321 reg = <0xff120000 0x1000>;
322 #address-cells = <1>;
328 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
329 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
330 clock-names = "spiclk", "apb_pclk";
331 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
332 dma-names = "tx", "rx";
333 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
334 pinctrl-names = "default";
335 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
336 reg = <0xff130000 0x1000>;
337 #address-cells = <1>;
343 compatible = "rockchip,rk3288-i2c";
344 reg = <0xff140000 0x1000>;
345 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
346 #address-cells = <1>;
349 clocks = <&cru PCLK_I2C1>;
350 pinctrl-names = "default";
351 pinctrl-0 = <&i2c1_xfer>;
356 compatible = "rockchip,rk3288-i2c";
357 reg = <0xff150000 0x1000>;
358 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
359 #address-cells = <1>;
362 clocks = <&cru PCLK_I2C3>;
363 pinctrl-names = "default";
364 pinctrl-0 = <&i2c3_xfer>;
369 compatible = "rockchip,rk3288-i2c";
370 reg = <0xff160000 0x1000>;
371 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
372 #address-cells = <1>;
375 clocks = <&cru PCLK_I2C4>;
376 pinctrl-names = "default";
377 pinctrl-0 = <&i2c4_xfer>;
382 compatible = "rockchip,rk3288-i2c";
383 reg = <0xff170000 0x1000>;
384 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
385 #address-cells = <1>;
388 clocks = <&cru PCLK_I2C5>;
389 pinctrl-names = "default";
390 pinctrl-0 = <&i2c5_xfer>;
394 uart0: serial@ff180000 {
395 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
396 reg = <0xff180000 0x100>;
397 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
401 clock-names = "baudclk", "apb_pclk";
402 pinctrl-names = "default";
403 pinctrl-0 = <&uart0_xfer>;
407 uart1: serial@ff190000 {
408 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
409 reg = <0xff190000 0x100>;
410 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
413 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
414 clock-names = "baudclk", "apb_pclk";
415 pinctrl-names = "default";
416 pinctrl-0 = <&uart1_xfer>;
420 uart2: serial@ff690000 {
421 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
422 reg = <0xff690000 0x100>;
423 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
426 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
427 clock-names = "baudclk", "apb_pclk";
428 pinctrl-names = "default";
429 pinctrl-0 = <&uart2_xfer>;
433 uart3: serial@ff1b0000 {
434 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
435 reg = <0xff1b0000 0x100>;
436 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
439 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
440 clock-names = "baudclk", "apb_pclk";
441 pinctrl-names = "default";
442 pinctrl-0 = <&uart3_xfer>;
446 uart4: serial@ff1c0000 {
447 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
448 reg = <0xff1c0000 0x100>;
449 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
452 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
453 clock-names = "baudclk", "apb_pclk";
454 pinctrl-names = "default";
455 pinctrl-0 = <&uart4_xfer>;
460 #include "rk3288-thermal.dtsi"
463 tsadc: tsadc@ff280000 {
464 compatible = "rockchip,rk3288-tsadc";
465 reg = <0xff280000 0x100>;
466 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
467 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
468 clock-names = "tsadc", "apb_pclk";
469 resets = <&cru SRST_TSADC>;
470 reset-names = "tsadc-apb";
471 pinctrl-names = "init", "default", "sleep";
472 pinctrl-0 = <&otp_gpio>;
473 pinctrl-1 = <&otp_out>;
474 pinctrl-2 = <&otp_gpio>;
475 #thermal-sensor-cells = <1>;
476 rockchip,hw-tshut-temp = <95000>;
480 gmac: ethernet@ff290000 {
481 compatible = "rockchip,rk3288-gmac";
482 reg = <0xff290000 0x10000>;
483 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
484 interrupt-names = "macirq";
485 rockchip,grf = <&grf>;
486 clocks = <&cru SCLK_MAC>,
487 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
488 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
489 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
490 clock-names = "stmmaceth",
491 "mac_clk_rx", "mac_clk_tx",
492 "clk_mac_ref", "clk_mac_refout",
493 "aclk_mac", "pclk_mac";
494 resets = <&cru SRST_MAC>;
495 reset-names = "stmmaceth";
499 usb_host0_ehci: usb@ff500000 {
500 compatible = "generic-ehci";
501 reg = <0xff500000 0x100>;
502 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
503 clocks = <&cru HCLK_USBHOST0>;
504 clock-names = "usbhost";
510 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
512 usb_host1: usb@ff540000 {
513 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
515 reg = <0xff540000 0x40000>;
516 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&cru HCLK_USBHOST1>;
521 phy-names = "usb2-phy";
525 usb_otg: usb@ff580000 {
526 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
528 reg = <0xff580000 0x40000>;
529 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&cru HCLK_OTG0>;
533 g-np-tx-fifo-size = <16>;
534 g-rx-fifo-size = <275>;
535 g-tx-fifo-size = <256 128 128 64 64 32>;
538 phy-names = "usb2-phy";
542 usb_hsic: usb@ff5c0000 {
543 compatible = "generic-ehci";
544 reg = <0xff5c0000 0x100>;
545 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
546 clocks = <&cru HCLK_HSIC>;
547 clock-names = "usbhost";
552 compatible = "rockchip,rk3288-i2c";
553 reg = <0xff650000 0x1000>;
554 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
555 #address-cells = <1>;
558 clocks = <&cru PCLK_I2C0>;
559 pinctrl-names = "default";
560 pinctrl-0 = <&i2c0_xfer>;
565 compatible = "rockchip,rk3288-i2c";
566 reg = <0xff660000 0x1000>;
567 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
568 #address-cells = <1>;
571 clocks = <&cru PCLK_I2C2>;
572 pinctrl-names = "default";
573 pinctrl-0 = <&i2c2_xfer>;
578 compatible = "rockchip,rk3288-pwm";
579 reg = <0xff680000 0x10>;
581 pinctrl-names = "default";
582 pinctrl-0 = <&pwm0_pin>;
583 clocks = <&cru PCLK_PWM>;
589 compatible = "rockchip,rk3288-pwm";
590 reg = <0xff680010 0x10>;
592 pinctrl-names = "default";
593 pinctrl-0 = <&pwm1_pin>;
594 clocks = <&cru PCLK_PWM>;
600 compatible = "rockchip,rk3288-pwm";
601 reg = <0xff680020 0x10>;
603 pinctrl-names = "default";
604 pinctrl-0 = <&pwm2_pin>;
605 clocks = <&cru PCLK_PWM>;
611 compatible = "rockchip,rk3288-pwm";
612 reg = <0xff680030 0x10>;
614 pinctrl-names = "default";
615 pinctrl-0 = <&pwm3_pin>;
616 clocks = <&cru PCLK_PWM>;
621 bus_intmem@ff700000 {
622 compatible = "mmio-sram";
623 reg = <0xff700000 0x18000>;
624 #address-cells = <1>;
626 ranges = <0 0xff700000 0x18000>;
628 compatible = "rockchip,rk3066-smp-sram";
634 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
635 reg = <0xff720000 0x1000>;
638 pmu: power-management@ff730000 {
639 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
640 reg = <0xff730000 0x100>;
642 power: power-controller {
643 compatible = "rockchip,rk3288-power-controller";
644 #power-domain-cells = <1>;
645 #address-cells = <1>;
649 * Note: Although SCLK_* are the working clocks
650 * of device without including on the NOC, needed for
653 * The clocks on the which NOC:
654 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
655 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
656 * ACLK_RGA is on ACLK_RGA_NIU.
657 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
659 * Which clock are device clocks:
661 * *_IEP IEP:Image Enhancement Processor
662 * *_ISP ISP:Image Signal Processing
663 * *_VIP VIP:Video Input Processor
664 * *_VOP* VOP:Visual Output Processor
672 reg = <RK3288_PD_VIO>;
673 clocks = <&cru ACLK_IEP>,
687 <&cru PCLK_EDP_CTRL>,
688 <&cru PCLK_HDMI_CTRL>,
689 <&cru PCLK_LVDS_PHY>,
690 <&cru PCLK_MIPI_CSI>,
691 <&cru PCLK_MIPI_DSI0>,
692 <&cru PCLK_MIPI_DSI1>,
701 * Note: The following 3 are HEVC(H.265) clocks,
702 * and on the ACLK_HEVC_NIU (NOC).
705 reg = <RK3288_PD_HEVC>;
706 clocks = <&cru ACLK_HEVC>,
707 <&cru SCLK_HEVC_CABAC>,
708 <&cru SCLK_HEVC_CORE>;
712 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
713 * (video endecoder & decoder) clocks that on the
714 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
717 reg = <RK3288_PD_VIDEO>;
718 clocks = <&cru ACLK_VCODEC>,
723 * Note: ACLK_GPU is the GPU clock,
724 * and on the ACLK_GPU_NIU (NOC).
727 reg = <RK3288_PD_GPU>;
728 clocks = <&cru ACLK_GPU>;
733 sgrf: syscon@ff740000 {
734 compatible = "rockchip,rk3288-sgrf", "syscon";
735 reg = <0xff740000 0x1000>;
738 cru: clock-controller@ff760000 {
739 compatible = "rockchip,rk3288-cru";
740 reg = <0xff760000 0x1000>;
741 rockchip,grf = <&grf>;
744 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
745 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
746 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
747 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
748 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
750 assigned-clock-rates = <0>, <0>,
751 <594000000>, <400000000>,
752 <500000000>, <300000000>,
753 <150000000>, <75000000>,
754 <300000000>, <150000000>,
756 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
759 grf: syscon@ff770000 {
760 compatible = "rockchip,rk3288-grf", "syscon";
761 reg = <0xff770000 0x1000>;
764 wdt: watchdog@ff800000 {
765 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
766 reg = <0xff800000 0x100>;
767 clocks = <&cru PCLK_WDT>;
768 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
772 spdif: sound@ff88b0000 {
773 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
774 reg = <0xff8b0000 0x10000>;
775 #sound-dai-cells = <0>;
776 clock-names = "hclk", "mclk";
777 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
778 dmas = <&dmac_bus_s 3>;
780 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
781 pinctrl-names = "default";
782 pinctrl-0 = <&spdif_tx>;
783 rockchip,grf = <&grf>;
788 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
789 reg = <0xff890000 0x10000>;
790 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
791 #address-cells = <1>;
793 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
794 dma-names = "tx", "rx";
795 clock-names = "i2s_hclk", "i2s_clk";
796 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
797 pinctrl-names = "default";
798 pinctrl-0 = <&i2s0_bus>;
803 compatible = "rockchip,rk3288-vop";
804 reg = <0xff930000 0x19c>;
805 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
806 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
807 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
808 power-domains = <&power RK3288_PD_VIO>;
809 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
810 reset-names = "axi", "ahb", "dclk";
811 iommus = <&vopb_mmu>;
815 #address-cells = <1>;
818 vopb_out_hdmi: endpoint@0 {
820 remote-endpoint = <&hdmi_in_vopb>;
823 vopb_out_edp: endpoint@1 {
825 remote-endpoint = <&edp_in_vopb>;
828 vopb_out_mipi: endpoint@2 {
830 remote-endpoint = <&mipi_in_vopb>;
833 vopb_out_lvds: endpoint@3 {
835 remote-endpoint = <&lvds_in_vopb>;
840 vopb_mmu: iommu@ff930300 {
841 compatible = "rockchip,iommu";
842 reg = <0xff930300 0x100>;
843 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
844 interrupt-names = "vopb_mmu";
845 power-domains = <&power RK3288_PD_VIO>;
851 compatible = "rockchip,rk3288-vop";
852 reg = <0xff940000 0x19c>;
853 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
854 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
855 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
856 power-domains = <&power RK3288_PD_VIO>;
857 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
858 reset-names = "axi", "ahb", "dclk";
859 iommus = <&vopl_mmu>;
863 #address-cells = <1>;
866 vopl_out_hdmi: endpoint@0 {
868 remote-endpoint = <&hdmi_in_vopl>;
871 vopl_out_edp: endpoint@1 {
873 remote-endpoint = <&edp_in_vopl>;
876 vopl_out_mipi: endpoint@2 {
878 remote-endpoint = <&mipi_in_vopl>;
881 vopl_out_lvds: endpoint@3 {
883 remote-endpoint = <&lvds_in_vopl>;
889 vopl_mmu: iommu@ff940300 {
890 compatible = "rockchip,iommu";
891 reg = <0xff940300 0x100>;
892 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
893 interrupt-names = "vopl_mmu";
894 power-domains = <&power RK3288_PD_VIO>;
899 mipi_dsi: mipi@ff960000 {
900 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
901 reg = <0xff960000 0x4000>;
902 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
903 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
904 clock-names = "ref", "pclk";
905 rockchip,grf = <&grf>;
906 #address-cells = <1>;
911 #address-cells = <1>;
916 #address-cells = <1>;
918 mipi_in_vopb: endpoint@0 {
920 remote-endpoint = <&vopb_out_mipi>;
922 mipi_in_vopl: endpoint@1 {
924 remote-endpoint = <&vopl_out_mipi>;
931 compatible = "rockchip,rk3288-dp";
932 reg = <0xff970000 0x4000>;
933 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
934 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
935 clock-names = "dp", "pclk";
938 resets = <&cru SRST_EDP>;
940 rockchip,grf = <&grf>;
944 #address-cells = <1>;
948 #address-cells = <1>;
950 edp_in_vopb: endpoint@0 {
952 remote-endpoint = <&vopb_out_edp>;
954 edp_in_vopl: endpoint@1 {
956 remote-endpoint = <&vopl_out_edp>;
962 lvds: lvds@ff96c000 {
963 compatible = "rockchip,rk3288-lvds";
964 reg = <0xff96c000 0x4000>;
965 clocks = <&cru PCLK_LVDS_PHY>;
966 clock-names = "pclk_lvds";
967 pinctrl-names = "default";
968 pinctrl-0 = <&lcdc0_ctl>;
969 power-domains = <&power RK3288_PD_VIO>;
970 rockchip,grf = <&grf>;
974 #address-cells = <1>;
980 #address-cells = <1>;
983 lvds_in_vopb: endpoint@0 {
985 remote-endpoint = <&vopb_out_lvds>;
987 lvds_in_vopl: endpoint@1 {
989 remote-endpoint = <&vopl_out_lvds>;
995 hdmi: hdmi@ff980000 {
996 compatible = "rockchip,rk3288-dw-hdmi";
997 reg = <0xff980000 0x20000>;
999 rockchip,grf = <&grf>;
1000 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1001 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1002 clock-names = "iahb", "isfr";
1003 power-domains = <&power RK3288_PD_VIO>;
1004 status = "disabled";
1008 #address-cells = <1>;
1010 hdmi_in_vopb: endpoint@0 {
1012 remote-endpoint = <&vopb_out_hdmi>;
1014 hdmi_in_vopl: endpoint@1 {
1016 remote-endpoint = <&vopl_out_hdmi>;
1023 compatible = "arm,malit764",
1027 reg = <0xffa30000 0x10000>;
1028 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1029 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1030 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1031 interrupt-names = "JOB", "MMU", "GPU";
1032 clocks = <&cru ACLK_GPU>;
1033 clock-names = "clk_mali";
1034 operating-points = <
1037 /* 500000 1200000 - See crosbug.com/p/33857 */
1043 #cooling-cells = <2>; /* min followed by max */
1044 power-domains = <&power RK3288_PD_GPU>;
1045 status = "disabled";
1048 vpu: video-codec@ff9a0000 {
1049 compatible = "rockchip,rk3288-vpu";
1050 reg = <0xff9a0000 0x800>;
1051 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1052 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1053 interrupt-names = "vepu", "vdpu";
1054 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1055 clock-names = "aclk", "hclk";
1056 power-domains = <&power RK3288_PD_VIDEO>;
1057 iommus = <&vpu_mmu>;
1058 assigned-clocks = <&cru ACLK_VCODEC>;
1059 assigned-clock-rates = <400000000>;
1060 status = "disabled";
1063 vpu_mmu: iommu@ff9a0800 {
1064 compatible = "rockchip,iommu";
1065 reg = <0xff9a0800 0x100>;
1066 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1067 interrupt-names = "vpu_mmu";
1068 power-domains = <&power RK3288_PD_VIDEO>;
1072 gic: interrupt-controller@ffc01000 {
1073 compatible = "arm,gic-400";
1074 interrupt-controller;
1075 #interrupt-cells = <3>;
1076 #address-cells = <0>;
1078 reg = <0xffc01000 0x1000>,
1079 <0xffc02000 0x1000>,
1080 <0xffc04000 0x2000>,
1081 <0xffc06000 0x2000>;
1082 interrupts = <GIC_PPI 9 0xf04>;
1086 compatible = "rockchip,rk3288-usb-phy";
1087 rockchip,grf = <&grf>;
1088 #address-cells = <1>;
1090 status = "disabled";
1095 clocks = <&cru SCLK_OTGPHY0>;
1096 clock-names = "phyclk";
1102 clocks = <&cru SCLK_OTGPHY1>;
1103 clock-names = "phyclk";
1109 clocks = <&cru SCLK_OTGPHY2>;
1110 clock-names = "phyclk";
1115 compatible = "rockchip,rk3288-pinctrl";
1116 rockchip,grf = <&grf>;
1117 rockchip,pmu = <&pmu>;
1118 #address-cells = <1>;
1122 gpio0: gpio0@ff750000 {
1123 compatible = "rockchip,gpio-bank";
1124 reg = <0xff750000 0x100>;
1125 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1126 clocks = <&cru PCLK_GPIO0>;
1131 interrupt-controller;
1132 #interrupt-cells = <2>;
1135 gpio1: gpio1@ff780000 {
1136 compatible = "rockchip,gpio-bank";
1137 reg = <0xff780000 0x100>;
1138 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1139 clocks = <&cru PCLK_GPIO1>;
1144 interrupt-controller;
1145 #interrupt-cells = <2>;
1148 gpio2: gpio2@ff790000 {
1149 compatible = "rockchip,gpio-bank";
1150 reg = <0xff790000 0x100>;
1151 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1152 clocks = <&cru PCLK_GPIO2>;
1157 interrupt-controller;
1158 #interrupt-cells = <2>;
1161 gpio3: gpio3@ff7a0000 {
1162 compatible = "rockchip,gpio-bank";
1163 reg = <0xff7a0000 0x100>;
1164 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1165 clocks = <&cru PCLK_GPIO3>;
1170 interrupt-controller;
1171 #interrupt-cells = <2>;
1174 gpio4: gpio4@ff7b0000 {
1175 compatible = "rockchip,gpio-bank";
1176 reg = <0xff7b0000 0x100>;
1177 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1178 clocks = <&cru PCLK_GPIO4>;
1183 interrupt-controller;
1184 #interrupt-cells = <2>;
1187 gpio5: gpio5@ff7c0000 {
1188 compatible = "rockchip,gpio-bank";
1189 reg = <0xff7c0000 0x100>;
1190 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1191 clocks = <&cru PCLK_GPIO5>;
1196 interrupt-controller;
1197 #interrupt-cells = <2>;
1200 gpio6: gpio6@ff7d0000 {
1201 compatible = "rockchip,gpio-bank";
1202 reg = <0xff7d0000 0x100>;
1203 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1204 clocks = <&cru PCLK_GPIO6>;
1209 interrupt-controller;
1210 #interrupt-cells = <2>;
1213 gpio7: gpio7@ff7e0000 {
1214 compatible = "rockchip,gpio-bank";
1215 reg = <0xff7e0000 0x100>;
1216 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1217 clocks = <&cru PCLK_GPIO7>;
1222 interrupt-controller;
1223 #interrupt-cells = <2>;
1226 gpio8: gpio8@ff7f0000 {
1227 compatible = "rockchip,gpio-bank";
1228 reg = <0xff7f0000 0x100>;
1229 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1230 clocks = <&cru PCLK_GPIO8>;
1235 interrupt-controller;
1236 #interrupt-cells = <2>;
1240 hdmi_ddc: hdmi-ddc {
1241 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1242 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1246 pcfg_pull_up: pcfg-pull-up {
1250 pcfg_pull_down: pcfg-pull-down {
1254 pcfg_pull_none: pcfg-pull-none {
1258 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1260 drive-strength = <12>;
1264 global_pwroff: global-pwroff {
1265 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1268 ddrio_pwroff: ddrio-pwroff {
1269 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1272 ddr0_retention: ddr0-retention {
1273 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1276 ddr1_retention: ddr1-retention {
1277 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1283 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1288 i2c0_xfer: i2c0-xfer {
1289 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1290 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1295 i2c1_xfer: i2c1-xfer {
1296 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1297 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1302 i2c2_xfer: i2c2-xfer {
1303 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1304 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1309 i2c3_xfer: i2c3-xfer {
1310 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1311 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1316 i2c4_xfer: i2c4-xfer {
1317 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1318 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1323 i2c5_xfer: i2c5-xfer {
1324 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1325 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1330 i2s0_bus: i2s0-bus {
1331 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1332 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1333 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1334 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1335 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1336 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1341 lcdc0_ctl: lcdc0-ctl {
1342 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1343 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1344 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1345 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1350 sdmmc_clk: sdmmc-clk {
1351 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1354 sdmmc_cmd: sdmmc-cmd {
1355 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1358 sdmmc_cd: sdmcc-cd {
1359 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1362 sdmmc_bus1: sdmmc-bus1 {
1363 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1366 sdmmc_bus4: sdmmc-bus4 {
1367 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1368 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1369 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1370 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1375 sdio0_bus1: sdio0-bus1 {
1376 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1379 sdio0_bus4: sdio0-bus4 {
1380 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1381 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1382 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1383 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1386 sdio0_cmd: sdio0-cmd {
1387 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1390 sdio0_clk: sdio0-clk {
1391 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1394 sdio0_cd: sdio0-cd {
1395 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1398 sdio0_wp: sdio0-wp {
1399 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1402 sdio0_pwr: sdio0-pwr {
1403 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1406 sdio0_bkpwr: sdio0-bkpwr {
1407 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1410 sdio0_int: sdio0-int {
1411 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1416 sdio1_bus1: sdio1-bus1 {
1417 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1420 sdio1_bus4: sdio1-bus4 {
1421 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1422 <3 25 4 &pcfg_pull_up>,
1423 <3 26 4 &pcfg_pull_up>,
1424 <3 27 4 &pcfg_pull_up>;
1427 sdio1_cd: sdio1-cd {
1428 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1431 sdio1_wp: sdio1-wp {
1432 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1435 sdio1_bkpwr: sdio1-bkpwr {
1436 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1439 sdio1_int: sdio1-int {
1440 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1443 sdio1_cmd: sdio1-cmd {
1444 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1447 sdio1_clk: sdio1-clk {
1448 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1451 sdio1_pwr: sdio1-pwr {
1452 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1457 emmc_clk: emmc-clk {
1458 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1461 emmc_cmd: emmc-cmd {
1462 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1465 emmc_pwr: emmc-pwr {
1466 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1469 emmc_bus1: emmc-bus1 {
1470 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1473 emmc_bus4: emmc-bus4 {
1474 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1475 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1476 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1477 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1480 emmc_bus8: emmc-bus8 {
1481 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1482 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1483 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1484 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1485 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1486 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1487 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1488 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1493 spi0_clk: spi0-clk {
1494 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1496 spi0_cs0: spi0-cs0 {
1497 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1500 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1503 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1505 spi0_cs1: spi0-cs1 {
1506 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1510 spi1_clk: spi1-clk {
1511 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1513 spi1_cs0: spi1-cs0 {
1514 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1517 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1520 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1525 spi2_cs1: spi2-cs1 {
1526 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1528 spi2_clk: spi2-clk {
1529 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1531 spi2_cs0: spi2-cs0 {
1532 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1535 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1538 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1543 uart0_xfer: uart0-xfer {
1544 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1545 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1548 uart0_cts: uart0-cts {
1549 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1552 uart0_rts: uart0-rts {
1553 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1558 uart1_xfer: uart1-xfer {
1559 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1560 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1563 uart1_cts: uart1-cts {
1564 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1567 uart1_rts: uart1-rts {
1568 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1573 uart2_xfer: uart2-xfer {
1574 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1575 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1577 /* no rts / cts for uart2 */
1581 uart3_xfer: uart3-xfer {
1582 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1583 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1586 uart3_cts: uart3-cts {
1587 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1590 uart3_rts: uart3-rts {
1591 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1596 uart4_xfer: uart4-xfer {
1597 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1598 <5 13 3 &pcfg_pull_none>;
1601 uart4_cts: uart4-cts {
1602 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1605 uart4_rts: uart4-rts {
1606 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1611 otp_gpio: otp-gpio {
1612 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1616 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1621 pwm0_pin: pwm0-pin {
1622 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1627 pwm1_pin: pwm1-pin {
1628 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1633 pwm2_pin: pwm2-pin {
1634 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1639 pwm3_pin: pwm3-pin {
1640 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1645 rgmii_pins: rgmii-pins {
1646 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1647 <3 31 3 &pcfg_pull_none>,
1648 <3 26 3 &pcfg_pull_none>,
1649 <3 27 3 &pcfg_pull_none>,
1650 <3 28 3 &pcfg_pull_none_12ma>,
1651 <3 29 3 &pcfg_pull_none_12ma>,
1652 <3 24 3 &pcfg_pull_none_12ma>,
1653 <3 25 3 &pcfg_pull_none_12ma>,
1654 <4 0 3 &pcfg_pull_none>,
1655 <4 5 3 &pcfg_pull_none>,
1656 <4 6 3 &pcfg_pull_none>,
1657 <4 9 3 &pcfg_pull_none_12ma>,
1658 <4 4 3 &pcfg_pull_none_12ma>,
1659 <4 1 3 &pcfg_pull_none>,
1660 <4 3 3 &pcfg_pull_none>;
1663 rmii_pins: rmii-pins {
1664 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1665 <3 31 3 &pcfg_pull_none>,
1666 <3 28 3 &pcfg_pull_none>,
1667 <3 29 3 &pcfg_pull_none>,
1668 <4 0 3 &pcfg_pull_none>,
1669 <4 5 3 &pcfg_pull_none>,
1670 <4 4 3 &pcfg_pull_none>,
1671 <4 1 3 &pcfg_pull_none>,
1672 <4 2 3 &pcfg_pull_none>,
1673 <4 3 3 &pcfg_pull_none>;
1678 spdif_tx: spdif-tx {
1679 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;