arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include <dt-bindings/soc/rockchip_boot-mode.h>
  49 #include "skeleton.dtsi"
  50
  51 / {
  52         compatible = "rockchip,rk3288";
  53
  54         interrupt-parent = <&gic>;
  55
  56         aliases {
  57                 i2c0 = &i2c0;
  58                 i2c1 = &i2c1;
  59                 i2c2 = &i2c2;
  60                 i2c3 = &i2c3;
  61                 i2c4 = &i2c4;
  62                 i2c5 = &i2c5;
  63                 mshc0 = &emmc;
  64                 mshc1 = &sdmmc;
  65                 mshc2 = &sdio0;
  66                 mshc3 = &sdio1;
  67                 serial0 = &uart0;
  68                 serial1 = &uart1;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71                 serial4 = &uart4;
  72                 spi0 = &spi0;
  73                 spi1 = &spi1;
  74                 spi2 = &spi2;
  75         };
  76
  77         arm-pmu {
  78                 compatible = "arm,cortex-a12-pmu";
  79                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  80                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  82                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  83                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  84         };
  85
  86         cpus {
  87                 #address-cells = <1>;
  88                 #size-cells = <0>;
  89                 enable-method = "rockchip,rk3066-smp";
  90                 rockchip,pmu = <&pmu>;
  91
  92                 cpu0: cpu@500 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a12";
  95                         reg = <0x500>;
  96                         resets = <&cru SRST_CORE0>;
  97                         operating-points = <
  98                                 /* KHz    uV */
  99                                 1608000 1350000
 100                                 1512000 1300000
 101                                 1416000 1200000
 102                                 1200000 1100000
 103                                 1008000 1050000
 104                                  816000 1000000
 105                                  696000  950000
 106                                  600000  900000
 107                                  408000  900000
 108                                  312000  900000
 109                                  216000  900000
 110                                  126000  900000
 111                         >;
 112                         #cooling-cells = <2>; /* min followed by max */
 113                         clock-latency = <40000>;
 114                         clocks = <&cru ARMCLK>;
 115                 };
 116                 cpu1: cpu@501 {
 117                         device_type = "cpu";
 118                         compatible = "arm,cortex-a12";
 119                         reg = <0x501>;
 120                         resets = <&cru SRST_CORE1>;
 121                 };
 122                 cpu2: cpu@502 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a12";
 125                         reg = <0x502>;
 126                         resets = <&cru SRST_CORE2>;
 127                 };
 128                 cpu3: cpu@503 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a12";
 131                         reg = <0x503>;
 132                         resets = <&cru SRST_CORE3>;
 133                 };
 134         };
 135
 136         amba {
 137                 compatible = "arm,amba-bus";
 138                 #address-cells = <1>;
 139                 #size-cells = <1>;
 140                 ranges;
 141
 142                 dmac_peri: dma-controller@ff250000 {
 143                         compatible = "arm,pl330", "arm,primecell";
 144                         reg = <0xff250000 0x4000>;
 145                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 146                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 147                         #dma-cells = <1>;
 148                         arm,pl330-broken-no-flushp;
 149                         peripherals-req-type-burst;
 150                         clocks = <&cru ACLK_DMAC2>;
 151                         clock-names = "apb_pclk";
 152                 };
 153
 154                 dmac_bus_ns: dma-controller@ff600000 {
 155                         compatible = "arm,pl330", "arm,primecell";
 156                         reg = <0xff600000 0x4000>;
 157                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 158                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 159                         #dma-cells = <1>;
 160                         arm,pl330-broken-no-flushp;
 161                         peripherals-req-type-burst;
 162                         clocks = <&cru ACLK_DMAC1>;
 163                         clock-names = "apb_pclk";
 164                         status = "disabled";
 165                 };
 166
 167                 dmac_bus_s: dma-controller@ffb20000 {
 168                         compatible = "arm,pl330", "arm,primecell";
 169                         reg = <0xffb20000 0x4000>;
 170                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 171                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 172                         #dma-cells = <1>;
 173                         arm,pl330-broken-no-flushp;
 174                         peripherals-req-type-burst;
 175                         clocks = <&cru ACLK_DMAC1>;
 176                         clock-names = "apb_pclk";
 177                 };
 178         };
 179
 180         reserved-memory {
 181                 #address-cells = <1>;
 182                 #size-cells = <1>;
 183                 ranges;
 184
 185                 /*
 186                  * The rk3288 cannot use the memory area above 0xfe000000
 187                  * for dma operations for some reason. While there is
 188                  * probably a better solution available somewhere, we
 189                  * haven't found it yet and while devices with 2GB of ram
 190                  * are not affected, this issue prevents 4GB from booting.
 191                  * So to make these devices at least bootable, block
 192                  * this area for the time being until the real solution
 193                  * is found.
 194                  */
 195                 dma-unusable@fe000000 {
 196                         reg = <0xfe000000 0x1000000>;
 197                 };
 198         };
 199
 200         xin24m: oscillator {
 201                 compatible = "fixed-clock";
 202                 clock-frequency = <24000000>;
 203                 clock-output-names = "xin24m";
 204                 #clock-cells = <0>;
 205         };
 206
 207         edp_phy: edp-phy {
 208                 compatible = "rockchip,rk3288-dp-phy";
 209                 clocks = <&cru SCLK_EDP_24M>;
 210                 clock-names = "24m";
 211                 rockchip,grf = <&grf>;
 212                 #phy-cells = <0>;
 213                 status = "disabled";
 214         };
 215
 216         timer {
 217                 compatible = "arm,armv7-timer";
 218                 arm,cpu-registers-not-fw-configured;
 219                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 220                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 221                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 222                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 223                 clock-frequency = <24000000>;
 224         };
 225
 226         timer: timer@ff810000 {
 227                 compatible = "rockchip,rk3288-timer";
 228                 reg = <0xff810000 0x20>;
 229                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 230                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 231                 clock-names = "timer", "pclk";
 232         };
 233
 234         display-subsystem {
 235                 compatible = "rockchip,display-subsystem";
 236                 ports = <&vopl_out>, <&vopb_out>;
 237         };
 238
 239         sdmmc: dwmmc@ff0c0000 {
 240                 compatible = "rockchip,rk3288-dw-mshc";
 241                 clock-freq-min-max = <400000 150000000>;
 242                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 243                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 244                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 245                 fifo-depth = <0x100>;
 246                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 247                 reg = <0xff0c0000 0x4000>;
 248                 status = "disabled";
 249         };
 250
 251         sdio0: dwmmc@ff0d0000 {
 252                 compatible = "rockchip,rk3288-dw-mshc";
 253                 clock-freq-min-max = <400000 150000000>;
 254                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 255                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 256                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 257                 fifo-depth = <0x100>;
 258                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 259                 reg = <0xff0d0000 0x4000>;
 260                 status = "disabled";
 261         };
 262
 263         sdio1: dwmmc@ff0e0000 {
 264                 compatible = "rockchip,rk3288-dw-mshc";
 265                 clock-freq-min-max = <400000 150000000>;
 266                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 267                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 268                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 269                 fifo-depth = <0x100>;
 270                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 271                 reg = <0xff0e0000 0x4000>;
 272                 status = "disabled";
 273         };
 274
 275         emmc: dwmmc@ff0f0000 {
 276                 compatible = "rockchip,rk3288-dw-mshc";
 277                 clock-freq-min-max = <400000 150000000>;
 278                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 279                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 280                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 281                 fifo-depth = <0x100>;
 282                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 283                 reg = <0xff0f0000 0x4000>;
 284                 status = "disabled";
 285                 supports-emmc;
 286         };
 287
 288         saradc: saradc@ff100000 {
 289                 compatible = "rockchip,saradc";
 290                 reg = <0xff100000 0x100>;
 291                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 292                 #io-channel-cells = <1>;
 293                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 294                 clock-names = "saradc", "apb_pclk";
 295                 status = "disabled";
 296         };
 297
 298         spi0: spi@ff110000 {
 299                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 300                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 301                 clock-names = "spiclk", "apb_pclk";
 302                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 303                 dma-names = "tx", "rx";
 304                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 305                 pinctrl-names = "default";
 306                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 307                 reg = <0xff110000 0x1000>;
 308                 #address-cells = <1>;
 309                 #size-cells = <0>;
 310                 status = "disabled";
 311         };
 312
 313         spi1: spi@ff120000 {
 314                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 315                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 316                 clock-names = "spiclk", "apb_pclk";
 317                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 318                 dma-names = "tx", "rx";
 319                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 320                 pinctrl-names = "default";
 321                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 322                 reg = <0xff120000 0x1000>;
 323                 #address-cells = <1>;
 324                 #size-cells = <0>;
 325                 status = "disabled";
 326         };
 327
 328         spi2: spi@ff130000 {
 329                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 330                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 331                 clock-names = "spiclk", "apb_pclk";
 332                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 333                 dma-names = "tx", "rx";
 334                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 335                 pinctrl-names = "default";
 336                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 337                 reg = <0xff130000 0x1000>;
 338                 #address-cells = <1>;
 339                 #size-cells = <0>;
 340                 status = "disabled";
 341         };
 342
 343         i2c1: i2c@ff140000 {
 344                 compatible = "rockchip,rk3288-i2c";
 345                 reg = <0xff140000 0x1000>;
 346                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 347                 #address-cells = <1>;
 348                 #size-cells = <0>;
 349                 clock-names = "i2c";
 350                 clocks = <&cru PCLK_I2C1>;
 351                 pinctrl-names = "default";
 352                 pinctrl-0 = <&i2c1_xfer>;
 353                 status = "disabled";
 354         };
 355
 356         i2c3: i2c@ff150000 {
 357                 compatible = "rockchip,rk3288-i2c";
 358                 reg = <0xff150000 0x1000>;
 359                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 360                 #address-cells = <1>;
 361                 #size-cells = <0>;
 362                 clock-names = "i2c";
 363                 clocks = <&cru PCLK_I2C3>;
 364                 pinctrl-names = "default";
 365                 pinctrl-0 = <&i2c3_xfer>;
 366                 status = "disabled";
 367         };
 368
 369         i2c4: i2c@ff160000 {
 370                 compatible = "rockchip,rk3288-i2c";
 371                 reg = <0xff160000 0x1000>;
 372                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 373                 #address-cells = <1>;
 374                 #size-cells = <0>;
 375                 clock-names = "i2c";
 376                 clocks = <&cru PCLK_I2C4>;
 377                 pinctrl-names = "default";
 378                 pinctrl-0 = <&i2c4_xfer>;
 379                 status = "disabled";
 380         };
 381
 382         i2c5: i2c@ff170000 {
 383                 compatible = "rockchip,rk3288-i2c";
 384                 reg = <0xff170000 0x1000>;
 385                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 386                 #address-cells = <1>;
 387                 #size-cells = <0>;
 388                 clock-names = "i2c";
 389                 clocks = <&cru PCLK_I2C5>;
 390                 pinctrl-names = "default";
 391                 pinctrl-0 = <&i2c5_xfer>;
 392                 status = "disabled";
 393         };
 394
 395         uart0: serial@ff180000 {
 396                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 397                 reg = <0xff180000 0x100>;
 398                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 399                 reg-shift = <2>;
 400                 reg-io-width = <4>;
 401                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 402                 clock-names = "baudclk", "apb_pclk";
 403                 pinctrl-names = "default";
 404                 pinctrl-0 = <&uart0_xfer>;
 405                 status = "disabled";
 406         };
 407
 408         uart1: serial@ff190000 {
 409                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 410                 reg = <0xff190000 0x100>;
 411                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 412                 reg-shift = <2>;
 413                 reg-io-width = <4>;
 414                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 415                 clock-names = "baudclk", "apb_pclk";
 416                 pinctrl-names = "default";
 417                 pinctrl-0 = <&uart1_xfer>;
 418                 status = "disabled";
 419         };
 420
 421         uart2: serial@ff690000 {
 422                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 423                 reg = <0xff690000 0x100>;
 424                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 425                 reg-shift = <2>;
 426                 reg-io-width = <4>;
 427                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 428                 clock-names = "baudclk", "apb_pclk";
 429                 pinctrl-names = "default";
 430                 pinctrl-0 = <&uart2_xfer>;
 431                 status = "disabled";
 432         };
 433
 434         uart3: serial@ff1b0000 {
 435                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 436                 reg = <0xff1b0000 0x100>;
 437                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 438                 reg-shift = <2>;
 439                 reg-io-width = <4>;
 440                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 441                 clock-names = "baudclk", "apb_pclk";
 442                 pinctrl-names = "default";
 443                 pinctrl-0 = <&uart3_xfer>;
 444                 status = "disabled";
 445         };
 446
 447         uart4: serial@ff1c0000 {
 448                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 449                 reg = <0xff1c0000 0x100>;
 450                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 451                 reg-shift = <2>;
 452                 reg-io-width = <4>;
 453                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 454                 clock-names = "baudclk", "apb_pclk";
 455                 pinctrl-names = "default";
 456                 pinctrl-0 = <&uart4_xfer>;
 457                 status = "disabled";
 458         };
 459
 460         thermal-zones {
 461                 #include "rk3288-thermal.dtsi"
 462         };
 463
 464         tsadc: tsadc@ff280000 {
 465                 compatible = "rockchip,rk3288-tsadc";
 466                 reg = <0xff280000 0x100>;
 467                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 468                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 469                 clock-names = "tsadc", "apb_pclk";
 470                 resets = <&cru SRST_TSADC>;
 471                 reset-names = "tsadc-apb";
 472                 pinctrl-names = "init", "default", "sleep";
 473                 pinctrl-0 = <&otp_gpio>;
 474                 pinctrl-1 = <&otp_out>;
 475                 pinctrl-2 = <&otp_gpio>;
 476                 #thermal-sensor-cells = <1>;
 477                 rockchip,hw-tshut-temp = <95000>;
 478                 status = "disabled";
 479         };
 480
 481         gmac: ethernet@ff290000 {
 482                 compatible = "rockchip,rk3288-gmac";
 483                 reg = <0xff290000 0x10000>;
 484                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 485                 interrupt-names = "macirq";
 486                 rockchip,grf = <&grf>;
 487                 clocks = <&cru SCLK_MAC>,
 488                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 489                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 490                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 491                 clock-names = "stmmaceth",
 492                         "mac_clk_rx", "mac_clk_tx",
 493                         "clk_mac_ref", "clk_mac_refout",
 494                         "aclk_mac", "pclk_mac";
 495                 resets = <&cru SRST_MAC>;
 496                 reset-names = "stmmaceth";
 497                 status = "disabled";
 498         };
 499
 500         usb_host0_ehci: usb@ff500000 {
 501                 compatible = "generic-ehci";
 502                 reg = <0xff500000 0x100>;
 503                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 504                 clocks = <&cru HCLK_USBHOST0>;
 505                 clock-names = "usbhost";
 506                 phys = <&usbphy1>;
 507                 phy-names = "usb";
 508                 status = "disabled";
 509         };
 510
 511         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 512
 513         usb_host1: usb@ff540000 {
 514                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 515                                 "snps,dwc2";
 516                 reg = <0xff540000 0x40000>;
 517                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 518                 clocks = <&cru HCLK_USBHOST1>;
 519                 clock-names = "otg";
 520                 dr_mode = "host";
 521                 phys = <&usbphy2>;
 522                 phy-names = "usb2-phy";
 523                 status = "disabled";
 524         };
 525
 526         usb_otg: usb@ff580000 {
 527                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 528                                 "snps,dwc2";
 529                 reg = <0xff580000 0x40000>;
 530                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 531                 clocks = <&cru HCLK_OTG0>;
 532                 clock-names = "otg";
 533                 dr_mode = "otg";
 534                 g-np-tx-fifo-size = <16>;
 535                 g-rx-fifo-size = <275>;
 536                 g-tx-fifo-size = <256 128 128 64 64 32>;
 537                 g-use-dma;
 538                 phys = <&usbphy0>;
 539                 phy-names = "usb2-phy";
 540                 status = "disabled";
 541         };
 542
 543         usb_hsic: usb@ff5c0000 {
 544                 compatible = "generic-ehci";
 545                 reg = <0xff5c0000 0x100>;
 546                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 547                 clocks = <&cru HCLK_HSIC>;
 548                 clock-names = "usbhost";
 549                 status = "disabled";
 550         };
 551
 552         i2c0: i2c@ff650000 {
 553                 compatible = "rockchip,rk3288-i2c";
 554                 reg = <0xff650000 0x1000>;
 555                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 556                 #address-cells = <1>;
 557                 #size-cells = <0>;
 558                 clock-names = "i2c";
 559                 clocks = <&cru PCLK_I2C0>;
 560                 pinctrl-names = "default";
 561                 pinctrl-0 = <&i2c0_xfer>;
 562                 status = "disabled";
 563         };
 564
 565         i2c2: i2c@ff660000 {
 566                 compatible = "rockchip,rk3288-i2c";
 567                 reg = <0xff660000 0x1000>;
 568                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 569                 #address-cells = <1>;
 570                 #size-cells = <0>;
 571                 clock-names = "i2c";
 572                 clocks = <&cru PCLK_I2C2>;
 573                 pinctrl-names = "default";
 574                 pinctrl-0 = <&i2c2_xfer>;
 575                 status = "disabled";
 576         };
 577
 578         pwm0: pwm@ff680000 {
 579                 compatible = "rockchip,rk3288-pwm";
 580                 reg = <0xff680000 0x10>;
 581                 #pwm-cells = <3>;
 582                 pinctrl-names = "default";
 583                 pinctrl-0 = <&pwm0_pin>;
 584                 clocks = <&cru PCLK_PWM>;
 585                 clock-names = "pwm";
 586                 status = "disabled";
 587         };
 588
 589         pwm1: pwm@ff680010 {
 590                 compatible = "rockchip,rk3288-pwm";
 591                 reg = <0xff680010 0x10>;
 592                 #pwm-cells = <3>;
 593                 pinctrl-names = "default";
 594                 pinctrl-0 = <&pwm1_pin>;
 595                 clocks = <&cru PCLK_PWM>;
 596                 clock-names = "pwm";
 597                 status = "disabled";
 598         };
 599
 600         pwm2: pwm@ff680020 {
 601                 compatible = "rockchip,rk3288-pwm";
 602                 reg = <0xff680020 0x10>;
 603                 #pwm-cells = <3>;
 604                 pinctrl-names = "default";
 605                 pinctrl-0 = <&pwm2_pin>;
 606                 clocks = <&cru PCLK_PWM>;
 607                 clock-names = "pwm";
 608                 status = "disabled";
 609         };
 610
 611         pwm3: pwm@ff680030 {
 612                 compatible = "rockchip,rk3288-pwm";
 613                 reg = <0xff680030 0x10>;
 614                 #pwm-cells = <2>;
 615                 pinctrl-names = "default";
 616                 pinctrl-0 = <&pwm3_pin>;
 617                 clocks = <&cru PCLK_PWM>;
 618                 clock-names = "pwm";
 619                 status = "disabled";
 620         };
 621
 622         bus_intmem@ff700000 {
 623                 compatible = "mmio-sram";
 624                 reg = <0xff700000 0x18000>;
 625                 #address-cells = <1>;
 626                 #size-cells = <1>;
 627                 ranges = <0 0xff700000 0x18000>;
 628                 smp-sram@0 {
 629                         compatible = "rockchip,rk3066-smp-sram";
 630                         reg = <0x00 0x10>;
 631                 };
 632         };
 633
 634         sram@ff720000 {
 635                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 636                 reg = <0xff720000 0x1000>;
 637         };
 638
 639         pmu: power-management@ff730000 {
 640                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 641                 reg = <0xff730000 0x100>;
 642
 643                 power: power-controller {
 644                         compatible = "rockchip,rk3288-power-controller";
 645                         #power-domain-cells = <1>;
 646                         #address-cells = <1>;
 647                         #size-cells = <0>;
 648
 649                         /*
 650                          * Note: Although SCLK_* are the working clocks
 651                          * of device without including on the NOC, needed for
 652                          * synchronous reset.
 653                          *
 654                          * The clocks on the which NOC:
 655                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 656                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 657                          * ACLK_RGA is on ACLK_RGA_NIU.
 658                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 659                          *
 660                          * Which clock are device clocks:
 661                          *      clocks          devices
 662                          *      *_IEP           IEP:Image Enhancement Processor
 663                          *      *_ISP           ISP:Image Signal Processing
 664                          *      *_VIP           VIP:Video Input Processor
 665                          *      *_VOP*          VOP:Visual Output Processor
 666                          *      *_RGA           RGA
 667                          *      *_EDP*          EDP
 668                          *      *_LVDS_*        LVDS
 669                          *      *_HDMI          HDMI
 670                          *      *_MIPI_*        MIPI
 671                          */
 672                         pd_vio {
 673                                 reg = <RK3288_PD_VIO>;
 674                                 clocks = <&cru ACLK_IEP>,
 675                                          <&cru ACLK_ISP>,
 676                                          <&cru ACLK_RGA>,
 677                                          <&cru ACLK_VIP>,
 678                                          <&cru ACLK_VOP0>,
 679                                          <&cru ACLK_VOP1>,
 680                                          <&cru DCLK_VOP0>,
 681                                          <&cru DCLK_VOP1>,
 682                                          <&cru HCLK_IEP>,
 683                                          <&cru HCLK_ISP>,
 684                                          <&cru HCLK_RGA>,
 685                                          <&cru HCLK_VIP>,
 686                                          <&cru HCLK_VOP0>,
 687                                          <&cru HCLK_VOP1>,
 688                                          <&cru PCLK_EDP_CTRL>,
 689                                          <&cru PCLK_HDMI_CTRL>,
 690                                          <&cru PCLK_LVDS_PHY>,
 691                                          <&cru PCLK_MIPI_CSI>,
 692                                          <&cru PCLK_MIPI_DSI0>,
 693                                          <&cru PCLK_MIPI_DSI1>,
 694                                          <&cru SCLK_EDP_24M>,
 695                                          <&cru SCLK_EDP>,
 696                                          <&cru SCLK_ISP_JPE>,
 697                                          <&cru SCLK_ISP>,
 698                                          <&cru SCLK_RGA>;
 699                         };
 700
 701                         /*
 702                          * Note: The following 3 are HEVC(H.265) clocks,
 703                          * and on the ACLK_HEVC_NIU (NOC).
 704                          */
 705                         pd_hevc {
 706                                 reg = <RK3288_PD_HEVC>;
 707                                 clocks = <&cru ACLK_HEVC>,
 708                                          <&cru SCLK_HEVC_CABAC>,
 709                                          <&cru SCLK_HEVC_CORE>;
 710                         };
 711
 712                         /*
 713                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 714                          * (video endecoder & decoder) clocks that on the
 715                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 716                          */
 717                         pd_video {
 718                                 reg = <RK3288_PD_VIDEO>;
 719                                 clocks = <&cru ACLK_VCODEC>,
 720                                          <&cru HCLK_VCODEC>;
 721                         };
 722
 723                         /*
 724                          * Note: ACLK_GPU is the GPU clock,
 725                          * and on the ACLK_GPU_NIU (NOC).
 726                          */
 727                         pd_gpu {
 728                                 reg = <RK3288_PD_GPU>;
 729                                 clocks = <&cru ACLK_GPU>;
 730                         };
 731                 };
 732
 733                 reboot-mode {
 734                         compatible = "syscon-reboot-mode";
 735                         offset = <0x94>;
 736                         mode-normal = <BOOT_NORMAL>;
 737                         mode-recovery = <BOOT_RECOVERY>;
 738                         mode-bootloader = <BOOT_FASTBOOT>;
 739                         mode-loader = <BOOT_LOADER>;
 740                         mode-ums = <BOOT_UMS>;
 741                 };
 742         };
 743
 744         sgrf: syscon@ff740000 {
 745                 compatible = "rockchip,rk3288-sgrf", "syscon";
 746                 reg = <0xff740000 0x1000>;
 747         };
 748
 749         cru: clock-controller@ff760000 {
 750                 compatible = "rockchip,rk3288-cru";
 751                 reg = <0xff760000 0x1000>;
 752                 rockchip,grf = <&grf>;
 753                 #clock-cells = <1>;
 754                 #reset-cells = <1>;
 755                 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
 756                                   <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 757                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 758                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 759                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 760                                   <&cru PCLK_PERI>;
 761                 assigned-clock-rates = <0>, <0>,
 762                                        <594000000>, <400000000>,
 763                                        <500000000>, <300000000>,
 764                                        <150000000>, <75000000>,
 765                                        <300000000>, <150000000>,
 766                                        <75000000>;
 767                 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
 768         };
 769
 770         grf: syscon@ff770000 {
 771                 compatible = "rockchip,rk3288-grf", "syscon";
 772                 reg = <0xff770000 0x1000>;
 773         };
 774
 775         wdt: watchdog@ff800000 {
 776                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 777                 reg = <0xff800000 0x100>;
 778                 clocks = <&cru PCLK_WDT>;
 779                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 780                 status = "disabled";
 781         };
 782
 783         spdif: sound@ff88b0000 {
 784                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 785                 reg = <0xff8b0000 0x10000>;
 786                 #sound-dai-cells = <0>;
 787                 clock-names = "hclk", "mclk";
 788                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 789                 dmas = <&dmac_bus_s 3>;
 790                 dma-names = "tx";
 791                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 792                 pinctrl-names = "default";
 793                 pinctrl-0 = <&spdif_tx>;
 794                 rockchip,grf = <&grf>;
 795                 status = "disabled";
 796         };
 797
 798         i2s: i2s@ff890000 {
 799                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 800                 reg = <0xff890000 0x10000>;
 801                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 802                 #address-cells = <1>;
 803                 #size-cells = <0>;
 804                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 805                 dma-names = "tx", "rx";
 806                 clock-names = "i2s_hclk", "i2s_clk";
 807                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 808                 pinctrl-names = "default";
 809                 pinctrl-0 = <&i2s0_bus>;
 810                 status = "disabled";
 811         };
 812
 813         vopb: vop@ff930000 {
 814                 compatible = "rockchip,rk3288-vop";
 815                 reg = <0xff930000 0x19c>;
 816                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 817                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 818                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 819                 power-domains = <&power RK3288_PD_VIO>;
 820                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 821                 reset-names = "axi", "ahb", "dclk";
 822                 iommus = <&vopb_mmu>;
 823                 status = "disabled";
 824
 825                 vopb_out: port {
 826                         #address-cells = <1>;
 827                         #size-cells = <0>;
 828
 829                         vopb_out_hdmi: endpoint@0 {
 830                                 reg = <0>;
 831                                 remote-endpoint = <&hdmi_in_vopb>;
 832                         };
 833
 834                         vopb_out_edp: endpoint@1 {
 835                                 reg = <1>;
 836                                 remote-endpoint = <&edp_in_vopb>;
 837                         };
 838
 839                         vopb_out_mipi: endpoint@2 {
 840                                 reg = <2>;
 841                                 remote-endpoint = <&mipi_in_vopb>;
 842                         };
 843
 844                         vopb_out_lvds: endpoint@3 {
 845                                 reg = <3>;
 846                                 remote-endpoint = <&lvds_in_vopb>;
 847                         };
 848                 };
 849         };
 850
 851         vopb_mmu: iommu@ff930300 {
 852                 compatible = "rockchip,iommu";
 853                 reg = <0xff930300 0x100>;
 854                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 855                 interrupt-names = "vopb_mmu";
 856                 power-domains = <&power RK3288_PD_VIO>;
 857                 #iommu-cells = <0>;
 858                 status = "disabled";
 859         };
 860
 861         vopl: vop@ff940000 {
 862                 compatible = "rockchip,rk3288-vop";
 863                 reg = <0xff940000 0x19c>;
 864                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 865                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 866                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 867                 power-domains = <&power RK3288_PD_VIO>;
 868                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 869                 reset-names = "axi", "ahb", "dclk";
 870                 iommus = <&vopl_mmu>;
 871                 status = "disabled";
 872
 873                 vopl_out: port {
 874                         #address-cells = <1>;
 875                         #size-cells = <0>;
 876
 877                         vopl_out_hdmi: endpoint@0 {
 878                                 reg = <0>;
 879                                 remote-endpoint = <&hdmi_in_vopl>;
 880                         };
 881
 882                         vopl_out_edp: endpoint@1 {
 883                                 reg = <1>;
 884                                 remote-endpoint = <&edp_in_vopl>;
 885                         };
 886
 887                         vopl_out_mipi: endpoint@2 {
 888                                 reg = <2>;
 889                                 remote-endpoint = <&mipi_in_vopl>;
 890                         };
 891
 892                         vopl_out_lvds: endpoint@3 {
 893                                 reg = <3>;
 894                                 remote-endpoint = <&lvds_in_vopl>;
 895                         };
 896
 897                 };
 898         };
 899
 900         vopl_mmu: iommu@ff940300 {
 901                 compatible = "rockchip,iommu";
 902                 reg = <0xff940300 0x100>;
 903                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 904                 interrupt-names = "vopl_mmu";
 905                 power-domains = <&power RK3288_PD_VIO>;
 906                 #iommu-cells = <0>;
 907                 status = "disabled";
 908         };
 909
 910         mipi_dsi: mipi@ff960000 {
 911                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
 912                 reg = <0xff960000 0x4000>;
 913                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 914                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
 915                 clock-names = "ref", "pclk";
 916                 rockchip,grf = <&grf>;
 917                 #address-cells = <1>;
 918                 #size-cells = <0>;
 919                 status = "disabled";
 920
 921                 ports {
 922                         #address-cells = <1>;
 923                         #size-cells = <0>;
 924                         reg = <1>;
 925
 926                         mipi_in: port {
 927                                 #address-cells = <1>;
 928                                 #size-cells = <0>;
 929                                 mipi_in_vopb: endpoint@0 {
 930                                         reg = <0>;
 931                                         remote-endpoint = <&vopb_out_mipi>;
 932                                 };
 933                                 mipi_in_vopl: endpoint@1 {
 934                                         reg = <1>;
 935                                         remote-endpoint = <&vopl_out_mipi>;
 936                                 };
 937                         };
 938                 };
 939         };
 940
 941         edp: dp@ff970000 {
 942                 compatible = "rockchip,rk3288-dp";
 943                 reg = <0xff970000 0x4000>;
 944                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 945                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
 946                 clock-names = "dp", "pclk";
 947                 phys = <&edp_phy>;
 948                 phy-names = "dp";
 949                 resets = <&cru SRST_EDP>;
 950                 reset-names = "dp";
 951                 rockchip,grf = <&grf>;
 952                 status = "disabled";
 953
 954                 ports {
 955                         #address-cells = <1>;
 956                         #size-cells = <0>;
 957                         edp_in: port@0 {
 958                                 reg = <0>;
 959                                 #address-cells = <1>;
 960                                 #size-cells = <0>;
 961                                 edp_in_vopb: endpoint@0 {
 962                                         reg = <0>;
 963                                         remote-endpoint = <&vopb_out_edp>;
 964                                 };
 965                                 edp_in_vopl: endpoint@1 {
 966                                         reg = <1>;
 967                                         remote-endpoint = <&vopl_out_edp>;
 968                                 };
 969                         };
 970                 };
 971         };
 972
 973         lvds: lvds@ff96c000 {
 974                 compatible = "rockchip,rk3288-lvds";
 975                 reg = <0xff96c000 0x4000>;
 976                 clocks = <&cru PCLK_LVDS_PHY>;
 977                 clock-names = "pclk_lvds";
 978                 pinctrl-names = "default";
 979                 pinctrl-0 = <&lcdc0_ctl>;
 980                 power-domains = <&power RK3288_PD_VIO>;
 981                 rockchip,grf = <&grf>;
 982                 status = "disabled";
 983
 984                 ports {
 985                         #address-cells = <1>;
 986                         #size-cells = <0>;
 987
 988                         lvds_in: port@0 {
 989                                 reg = <0>;
 990
 991                                 #address-cells = <1>;
 992                                 #size-cells = <0>;
 993
 994                                 lvds_in_vopb: endpoint@0 {
 995                                         reg = <0>;
 996                                         remote-endpoint = <&vopb_out_lvds>;
 997                                 };
 998                                 lvds_in_vopl: endpoint@1 {
 999                                         reg = <1>;
1000                                         remote-endpoint = <&vopl_out_lvds>;
1001                                 };
1002                         };
1003                 };
1004         };
1005
1006         hdmi: hdmi@ff980000 {
1007                 compatible = "rockchip,rk3288-dw-hdmi";
1008                 reg = <0xff980000 0x20000>;
1009                 reg-io-width = <4>;
1010                 rockchip,grf = <&grf>;
1011                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1012                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1013                 clock-names = "iahb", "isfr";
1014                 power-domains = <&power RK3288_PD_VIO>;
1015                 status = "disabled";
1016
1017                 ports {
1018                         hdmi_in: port {
1019                                 #address-cells = <1>;
1020                                 #size-cells = <0>;
1021                                 hdmi_in_vopb: endpoint@0 {
1022                                         reg = <0>;
1023                                         remote-endpoint = <&vopb_out_hdmi>;
1024                                 };
1025                                 hdmi_in_vopl: endpoint@1 {
1026                                         reg = <1>;
1027                                         remote-endpoint = <&vopl_out_hdmi>;
1028                                 };
1029                         };
1030                 };
1031         };
1032
1033         gpu: gpu@ffa30000 {
1034                 compatible = "arm,malit764",
1035                              "arm,malit76x",
1036                              "arm,malit7xx",
1037                              "arm,mali-midgard";
1038                 reg = <0xffa30000 0x10000>;
1039                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1040                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1041                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1042                 interrupt-names = "JOB", "MMU", "GPU";
1043                 clocks = <&cru ACLK_GPU>;
1044                 clock-names = "clk_mali";
1045                 operating-points = <
1046                         /* KHz uV */
1047                         600000 1250000
1048                         /* 500000 1200000 - See crosbug.com/p/33857 */
1049                         400000 1100000
1050                         300000 1000000
1051                         200000 950000
1052                         100000 950000
1053                 >;
1054                 #cooling-cells = <2>; /* min followed by max */
1055                 power-domains = <&power RK3288_PD_GPU>;
1056                 status = "disabled";
1057         };
1058
1059         vpu: video-codec@ff9a0000 {
1060                 compatible = "rockchip,rk3288-vpu";
1061                 reg = <0xff9a0000 0x800>;
1062                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1063                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1064                 interrupt-names = "vepu", "vdpu";
1065                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1066                 clock-names = "aclk", "hclk";
1067                 power-domains = <&power RK3288_PD_VIDEO>;
1068                 iommus = <&vpu_mmu>;
1069                 assigned-clocks = <&cru ACLK_VCODEC>;
1070                 assigned-clock-rates = <400000000>;
1071                 status = "disabled";
1072         };
1073
1074         vpu_mmu: iommu@ff9a0800 {
1075                 compatible = "rockchip,iommu";
1076                 reg = <0xff9a0800 0x100>;
1077                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1078                 interrupt-names = "vpu_mmu";
1079                 power-domains = <&power RK3288_PD_VIDEO>;
1080                 #iommu-cells = <0>;
1081         };
1082
1083         gic: interrupt-controller@ffc01000 {
1084                 compatible = "arm,gic-400";
1085                 interrupt-controller;
1086                 #interrupt-cells = <3>;
1087                 #address-cells = <0>;
1088
1089                 reg = <0xffc01000 0x1000>,
1090                       <0xffc02000 0x1000>,
1091                       <0xffc04000 0x2000>,
1092                       <0xffc06000 0x2000>;
1093                 interrupts = <GIC_PPI 9 0xf04>;
1094         };
1095
1096         efuse: efuse@ffb40000 {
1097                 compatible = "rockchip,rockchip-efuse";
1098                 reg = <0xffb40000 0x20>;
1099                 #address-cells = <1>;
1100                 #size-cells = <1>;
1101                 clocks = <&cru PCLK_EFUSE256>;
1102                 clock-names = "pclk_efuse";
1103
1104                 cpu_leakage: cpu_leakage@17 {
1105                         reg = <0x17 0x1>;
1106                 };
1107         };
1108
1109         usbphy: phy {
1110                 compatible = "rockchip,rk3288-usb-phy";
1111                 rockchip,grf = <&grf>;
1112                 #address-cells = <1>;
1113                 #size-cells = <0>;
1114                 status = "disabled";
1115
1116                 usbphy0: usb-phy0 {
1117                         #phy-cells = <0>;
1118                         reg = <0x320>;
1119                         clocks = <&cru SCLK_OTGPHY0>;
1120                         clock-names = "phyclk";
1121                 };
1122
1123                 usbphy1: usb-phy1 {
1124                         #phy-cells = <0>;
1125                         reg = <0x334>;
1126                         clocks = <&cru SCLK_OTGPHY1>;
1127                         clock-names = "phyclk";
1128                 };
1129
1130                 usbphy2: usb-phy2 {
1131                         #phy-cells = <0>;
1132                         reg = <0x348>;
1133                         clocks = <&cru SCLK_OTGPHY2>;
1134                         clock-names = "phyclk";
1135                 };
1136         };
1137
1138         pinctrl: pinctrl {
1139                 compatible = "rockchip,rk3288-pinctrl";
1140                 rockchip,grf = <&grf>;
1141                 rockchip,pmu = <&pmu>;
1142                 #address-cells = <1>;
1143                 #size-cells = <1>;
1144                 ranges;
1145
1146                 gpio0: gpio0@ff750000 {
1147                         compatible = "rockchip,gpio-bank";
1148                         reg =   <0xff750000 0x100>;
1149                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1150                         clocks = <&cru PCLK_GPIO0>;
1151
1152                         gpio-controller;
1153                         #gpio-cells = <2>;
1154
1155                         interrupt-controller;
1156                         #interrupt-cells = <2>;
1157                 };
1158
1159                 gpio1: gpio1@ff780000 {
1160                         compatible = "rockchip,gpio-bank";
1161                         reg = <0xff780000 0x100>;
1162                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1163                         clocks = <&cru PCLK_GPIO1>;
1164
1165                         gpio-controller;
1166                         #gpio-cells = <2>;
1167
1168                         interrupt-controller;
1169                         #interrupt-cells = <2>;
1170                 };
1171
1172                 gpio2: gpio2@ff790000 {
1173                         compatible = "rockchip,gpio-bank";
1174                         reg = <0xff790000 0x100>;
1175                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1176                         clocks = <&cru PCLK_GPIO2>;
1177
1178                         gpio-controller;
1179                         #gpio-cells = <2>;
1180
1181                         interrupt-controller;
1182                         #interrupt-cells = <2>;
1183                 };
1184
1185                 gpio3: gpio3@ff7a0000 {
1186                         compatible = "rockchip,gpio-bank";
1187                         reg = <0xff7a0000 0x100>;
1188                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1189                         clocks = <&cru PCLK_GPIO3>;
1190
1191                         gpio-controller;
1192                         #gpio-cells = <2>;
1193
1194                         interrupt-controller;
1195                         #interrupt-cells = <2>;
1196                 };
1197
1198                 gpio4: gpio4@ff7b0000 {
1199                         compatible = "rockchip,gpio-bank";
1200                         reg = <0xff7b0000 0x100>;
1201                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1202                         clocks = <&cru PCLK_GPIO4>;
1203
1204                         gpio-controller;
1205                         #gpio-cells = <2>;
1206
1207                         interrupt-controller;
1208                         #interrupt-cells = <2>;
1209                 };
1210
1211                 gpio5: gpio5@ff7c0000 {
1212                         compatible = "rockchip,gpio-bank";
1213                         reg = <0xff7c0000 0x100>;
1214                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1215                         clocks = <&cru PCLK_GPIO5>;
1216
1217                         gpio-controller;
1218                         #gpio-cells = <2>;
1219
1220                         interrupt-controller;
1221                         #interrupt-cells = <2>;
1222                 };
1223
1224                 gpio6: gpio6@ff7d0000 {
1225                         compatible = "rockchip,gpio-bank";
1226                         reg = <0xff7d0000 0x100>;
1227                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1228                         clocks = <&cru PCLK_GPIO6>;
1229
1230                         gpio-controller;
1231                         #gpio-cells = <2>;
1232
1233                         interrupt-controller;
1234                         #interrupt-cells = <2>;
1235                 };
1236
1237                 gpio7: gpio7@ff7e0000 {
1238                         compatible = "rockchip,gpio-bank";
1239                         reg = <0xff7e0000 0x100>;
1240                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1241                         clocks = <&cru PCLK_GPIO7>;
1242
1243                         gpio-controller;
1244                         #gpio-cells = <2>;
1245
1246                         interrupt-controller;
1247                         #interrupt-cells = <2>;
1248                 };
1249
1250                 gpio8: gpio8@ff7f0000 {
1251                         compatible = "rockchip,gpio-bank";
1252                         reg = <0xff7f0000 0x100>;
1253                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1254                         clocks = <&cru PCLK_GPIO8>;
1255
1256                         gpio-controller;
1257                         #gpio-cells = <2>;
1258
1259                         interrupt-controller;
1260                         #interrupt-cells = <2>;
1261                 };
1262
1263                 hdmi {
1264                         hdmi_ddc: hdmi-ddc {
1265                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1266                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1267                         };
1268                 };
1269
1270                 pcfg_pull_up: pcfg-pull-up {
1271                         bias-pull-up;
1272                 };
1273
1274                 pcfg_pull_down: pcfg-pull-down {
1275                         bias-pull-down;
1276                 };
1277
1278                 pcfg_pull_none: pcfg-pull-none {
1279                         bias-disable;
1280                 };
1281
1282                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1283                         bias-disable;
1284                         drive-strength = <12>;
1285                 };
1286
1287                 sleep {
1288                         global_pwroff: global-pwroff {
1289                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1290                         };
1291
1292                         ddrio_pwroff: ddrio-pwroff {
1293                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1294                         };
1295
1296                         ddr0_retention: ddr0-retention {
1297                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1298                         };
1299
1300                         ddr1_retention: ddr1-retention {
1301                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1302                         };
1303                 };
1304
1305                 edp {
1306                         edp_hpd: edp-hpd {
1307                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1308                         };
1309                 };
1310
1311                 i2c0 {
1312                         i2c0_xfer: i2c0-xfer {
1313                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1314                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1315                         };
1316                 };
1317
1318                 i2c1 {
1319                         i2c1_xfer: i2c1-xfer {
1320                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1321                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1322                         };
1323                 };
1324
1325                 i2c2 {
1326                         i2c2_xfer: i2c2-xfer {
1327                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1328                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1329                         };
1330                 };
1331
1332                 i2c3 {
1333                         i2c3_xfer: i2c3-xfer {
1334                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1335                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1336                         };
1337                 };
1338
1339                 i2c4 {
1340                         i2c4_xfer: i2c4-xfer {
1341                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1342                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1343                         };
1344                 };
1345
1346                 i2c5 {
1347                         i2c5_xfer: i2c5-xfer {
1348                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1349                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1350                         };
1351                 };
1352
1353                 i2s0 {
1354                         i2s0_bus: i2s0-bus {
1355                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1356                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1357                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1358                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1359                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1360                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1361                         };
1362                 };
1363
1364                 lcdc0 {
1365                         lcdc0_ctl: lcdc0-ctl {
1366                                 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1367                                                 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1368                                                 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1369                                                 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1370                         };
1371                 };
1372
1373                 sdmmc {
1374                         sdmmc_clk: sdmmc-clk {
1375                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1376                         };
1377
1378                         sdmmc_cmd: sdmmc-cmd {
1379                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1380                         };
1381
1382                         sdmmc_cd: sdmcc-cd {
1383                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1384                         };
1385
1386                         sdmmc_bus1: sdmmc-bus1 {
1387                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1388                         };
1389
1390                         sdmmc_bus4: sdmmc-bus4 {
1391                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1392                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1393                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1394                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1395                         };
1396                 };
1397
1398                 sdio0 {
1399                         sdio0_bus1: sdio0-bus1 {
1400                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1401                         };
1402
1403                         sdio0_bus4: sdio0-bus4 {
1404                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1405                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1406                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1407                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1408                         };
1409
1410                         sdio0_cmd: sdio0-cmd {
1411                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1412                         };
1413
1414                         sdio0_clk: sdio0-clk {
1415                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1416                         };
1417
1418                         sdio0_cd: sdio0-cd {
1419                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1420                         };
1421
1422                         sdio0_wp: sdio0-wp {
1423                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1424                         };
1425
1426                         sdio0_pwr: sdio0-pwr {
1427                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1428                         };
1429
1430                         sdio0_bkpwr: sdio0-bkpwr {
1431                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1432                         };
1433
1434                         sdio0_int: sdio0-int {
1435                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1436                         };
1437                 };
1438
1439                 sdio1 {
1440                         sdio1_bus1: sdio1-bus1 {
1441                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1442                         };
1443
1444                         sdio1_bus4: sdio1-bus4 {
1445                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1446                                                 <3 25 4 &pcfg_pull_up>,
1447                                                 <3 26 4 &pcfg_pull_up>,
1448                                                 <3 27 4 &pcfg_pull_up>;
1449                         };
1450
1451                         sdio1_cd: sdio1-cd {
1452                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1453                         };
1454
1455                         sdio1_wp: sdio1-wp {
1456                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1457                         };
1458
1459                         sdio1_bkpwr: sdio1-bkpwr {
1460                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1461                         };
1462
1463                         sdio1_int: sdio1-int {
1464                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1465                         };
1466
1467                         sdio1_cmd: sdio1-cmd {
1468                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1469                         };
1470
1471                         sdio1_clk: sdio1-clk {
1472                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1473                         };
1474
1475                         sdio1_pwr: sdio1-pwr {
1476                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1477                         };
1478                 };
1479
1480                 emmc {
1481                         emmc_clk: emmc-clk {
1482                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1483                         };
1484
1485                         emmc_cmd: emmc-cmd {
1486                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1487                         };
1488
1489                         emmc_pwr: emmc-pwr {
1490                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1491                         };
1492
1493                         emmc_bus1: emmc-bus1 {
1494                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1495                         };
1496
1497                         emmc_bus4: emmc-bus4 {
1498                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1499                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1500                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1501                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1502                         };
1503
1504                         emmc_bus8: emmc-bus8 {
1505                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1506                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1507                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1508                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1509                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1510                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1511                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1512                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1513                         };
1514                 };
1515
1516                 spi0 {
1517                         spi0_clk: spi0-clk {
1518                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1519                         };
1520                         spi0_cs0: spi0-cs0 {
1521                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1522                         };
1523                         spi0_tx: spi0-tx {
1524                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1525                         };
1526                         spi0_rx: spi0-rx {
1527                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1528                         };
1529                         spi0_cs1: spi0-cs1 {
1530                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1531                         };
1532                 };
1533                 spi1 {
1534                         spi1_clk: spi1-clk {
1535                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1536                         };
1537                         spi1_cs0: spi1-cs0 {
1538                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1539                         };
1540                         spi1_rx: spi1-rx {
1541                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1542                         };
1543                         spi1_tx: spi1-tx {
1544                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1545                         };
1546                 };
1547
1548                 spi2 {
1549                         spi2_cs1: spi2-cs1 {
1550                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1551                         };
1552                         spi2_clk: spi2-clk {
1553                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1554                         };
1555                         spi2_cs0: spi2-cs0 {
1556                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1557                         };
1558                         spi2_rx: spi2-rx {
1559                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1560                         };
1561                         spi2_tx: spi2-tx {
1562                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1563                         };
1564                 };
1565
1566                 uart0 {
1567                         uart0_xfer: uart0-xfer {
1568                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1569                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1570                         };
1571
1572                         uart0_cts: uart0-cts {
1573                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1574                         };
1575
1576                         uart0_rts: uart0-rts {
1577                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1578                         };
1579                 };
1580
1581                 uart1 {
1582                         uart1_xfer: uart1-xfer {
1583                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1584                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1585                         };
1586
1587                         uart1_cts: uart1-cts {
1588                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1589                         };
1590
1591                         uart1_rts: uart1-rts {
1592                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1593                         };
1594                 };
1595
1596                 uart2 {
1597                         uart2_xfer: uart2-xfer {
1598                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1599                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1600                         };
1601                         /* no rts / cts for uart2 */
1602                 };
1603
1604                 uart3 {
1605                         uart3_xfer: uart3-xfer {
1606                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1607                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1608                         };
1609
1610                         uart3_cts: uart3-cts {
1611                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1612                         };
1613
1614                         uart3_rts: uart3-rts {
1615                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1616                         };
1617                 };
1618
1619                 uart4 {
1620                         uart4_xfer: uart4-xfer {
1621                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1622                                                 <5 13 3 &pcfg_pull_none>;
1623                         };
1624
1625                         uart4_cts: uart4-cts {
1626                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1627                         };
1628
1629                         uart4_rts: uart4-rts {
1630                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1631                         };
1632                 };
1633
1634                 tsadc {
1635                         otp_gpio: otp-gpio {
1636                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1637                         };
1638
1639                         otp_out: otp-out {
1640                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1641                         };
1642                 };
1643
1644                 pwm0 {
1645                         pwm0_pin: pwm0-pin {
1646                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1647                         };
1648                 };
1649
1650                 pwm1 {
1651                         pwm1_pin: pwm1-pin {
1652                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1653                         };
1654                 };
1655
1656                 pwm2 {
1657                         pwm2_pin: pwm2-pin {
1658                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1659                         };
1660                 };
1661
1662                 pwm3 {
1663                         pwm3_pin: pwm3-pin {
1664                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1665                         };
1666                 };
1667
1668                 gmac {
1669                         rgmii_pins: rgmii-pins {
1670                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1671                                                 <3 31 3 &pcfg_pull_none>,
1672                                                 <3 26 3 &pcfg_pull_none>,
1673                                                 <3 27 3 &pcfg_pull_none>,
1674                                                 <3 28 3 &pcfg_pull_none_12ma>,
1675                                                 <3 29 3 &pcfg_pull_none_12ma>,
1676                                                 <3 24 3 &pcfg_pull_none_12ma>,
1677                                                 <3 25 3 &pcfg_pull_none_12ma>,
1678                                                 <4 0 3 &pcfg_pull_none>,
1679                                                 <4 5 3 &pcfg_pull_none>,
1680                                                 <4 6 3 &pcfg_pull_none>,
1681                                                 <4 9 3 &pcfg_pull_none_12ma>,
1682                                                 <4 4 3 &pcfg_pull_none_12ma>,
1683                                                 <4 1 3 &pcfg_pull_none>,
1684                                                 <4 3 3 &pcfg_pull_none>;
1685                         };
1686
1687                         rmii_pins: rmii-pins {
1688                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1689                                                 <3 31 3 &pcfg_pull_none>,
1690                                                 <3 28 3 &pcfg_pull_none>,
1691                                                 <3 29 3 &pcfg_pull_none>,
1692                                                 <4 0 3 &pcfg_pull_none>,
1693                                                 <4 5 3 &pcfg_pull_none>,
1694                                                 <4 4 3 &pcfg_pull_none>,
1695                                                 <4 1 3 &pcfg_pull_none>,
1696                                                 <4 2 3 &pcfg_pull_none>,
1697                                                 <4 3 3 &pcfg_pull_none>;
1698                         };
1699                 };
1700
1701                 spdif {
1702                         spdif_tx: spdif-tx {
1703                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1704                         };
1705                 };
1706         };
1707 };