2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3288-cru.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/power/rk3288-power.h>
48 #include <dt-bindings/soc/rockchip,boot-mode.h>
49 #include <dt-bindings/suspend/rockchip-rk3288.h>
50 #include <dt-bindings/display/drm_mipi_dsi.h>
51 #include "skeleton64.dtsi"
54 compatible = "rockchip,rk3288";
56 interrupt-parent = <&gic>;
81 compatible = "arm,cortex-a12-pmu";
82 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
86 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
92 enable-method = "rockchip,rk3066-smp";
93 rockchip,pmu = <&pmu>;
97 compatible = "arm,cortex-a12";
99 resets = <&cru SRST_CORE0>;
100 operating-points-v2 = <&cpu0_opp_table>;
101 #cooling-cells = <2>; /* min followed by max */
102 dynamic-power-coefficient = <322>;
103 clocks = <&cru ARMCLK>;
107 compatible = "arm,cortex-a12";
109 resets = <&cru SRST_CORE1>;
110 operating-points-v2 = <&cpu0_opp_table>;
114 compatible = "arm,cortex-a12";
116 resets = <&cru SRST_CORE2>;
117 operating-points-v2 = <&cpu0_opp_table>;
121 compatible = "arm,cortex-a12";
123 resets = <&cru SRST_CORE3>;
124 operating-points-v2 = <&cpu0_opp_table>;
128 cpu0_opp_table: opp_table0 {
129 compatible = "operating-points-v2";
132 nvmem-cells = <&cpu_leakage>;
133 nvmem-cell-names = "cpu_leakage";
136 opp-hz = /bits/ 64 <126000000>;
137 opp-microvolt = <900000>;
138 clock-latency-ns = <40000>;
141 opp-hz = /bits/ 64 <216000000>;
142 opp-microvolt = <900000>;
143 clock-latency-ns = <40000>;
146 opp-hz = /bits/ 64 <408000000>;
147 opp-microvolt = <900000>;
148 clock-latency-ns = <40000>;
151 opp-hz = /bits/ 64 <600000000>;
152 opp-microvolt = <900000>;
153 clock-latency-ns = <40000>;
156 opp-hz = /bits/ 64 <696000000>;
157 opp-microvolt = <950000>;
158 clock-latency-ns = <40000>;
161 opp-hz = /bits/ 64 <816000000>;
162 opp-microvolt = <1000000>;
163 clock-latency-ns = <40000>;
167 opp-hz = /bits/ 64 <1008000000>;
168 opp-microvolt = <1050000>;
169 clock-latency-ns = <40000>;
172 opp-hz = /bits/ 64 <1200000000>;
173 opp-microvolt = <1100000>;
174 clock-latency-ns = <40000>;
177 opp-hz = /bits/ 64 <1416000000>;
178 opp-microvolt = <1200000>;
179 clock-latency-ns = <40000>;
182 opp-hz = /bits/ 64 <1512000000>;
183 opp-microvolt = <1300000>;
184 clock-latency-ns = <40000>;
187 opp-hz = /bits/ 64 <1608000000>;
188 opp-microvolt = <1350000>;
189 clock-latency-ns = <40000>;
194 compatible = "arm,amba-bus";
195 #address-cells = <2>;
199 dmac_peri: dma-controller@ff250000 {
200 compatible = "arm,pl330", "arm,primecell";
201 reg = <0x0 0xff250000 0x0 0x4000>;
202 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
205 arm,pl330-broken-no-flushp;
206 peripherals-req-type-burst;
207 clocks = <&cru ACLK_DMAC2>;
208 clock-names = "apb_pclk";
211 dmac_bus_ns: dma-controller@ff600000 {
212 compatible = "arm,pl330", "arm,primecell";
213 reg = <0x0 0xff600000 0x0 0x4000>;
214 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
215 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
217 arm,pl330-broken-no-flushp;
218 peripherals-req-type-burst;
219 clocks = <&cru ACLK_DMAC1>;
220 clock-names = "apb_pclk";
224 dmac_bus_s: dma-controller@ffb20000 {
225 compatible = "arm,pl330", "arm,primecell";
226 reg = <0x0 0xffb20000 0x0 0x4000>;
227 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
230 arm,pl330-broken-no-flushp;
231 peripherals-req-type-burst;
232 clocks = <&cru ACLK_DMAC1>;
233 clock-names = "apb_pclk";
238 #address-cells = <2>;
243 * The rk3288 cannot use the memory area above 0xfe000000
244 * for dma operations for some reason. While there is
245 * probably a better solution available somewhere, we
246 * haven't found it yet and while devices with 2GB of ram
247 * are not affected, this issue prevents 4GB from booting.
248 * So to make these devices at least bootable, block
249 * this area for the time being until the real solution
252 dma-unusable@fe000000 {
253 reg = <0x0 0xfe000000 0x0 0x1000000>;
258 compatible = "fixed-clock";
259 clock-frequency = <24000000>;
260 clock-output-names = "xin24m";
265 compatible = "arm,armv7-timer";
266 arm,cpu-registers-not-fw-configured;
267 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
268 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
269 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
270 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
271 clock-frequency = <24000000>;
275 compatible = "rockchip,display-subsystem";
276 ports = <&vopl_out>, <&vopb_out>;
279 sdmmc: dwmmc@ff0c0000 {
280 compatible = "rockchip,rk3288-dw-mshc";
281 clock-freq-min-max = <400000 150000000>;
282 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
283 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
284 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
285 fifo-depth = <0x100>;
286 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
287 reg = <0x0 0xff0c0000 0x0 0x4000>;
291 sdio0: dwmmc@ff0d0000 {
292 compatible = "rockchip,rk3288-dw-mshc";
293 clock-freq-min-max = <400000 150000000>;
294 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
295 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
296 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
297 fifo-depth = <0x100>;
298 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
299 reg = <0x0 0xff0d0000 0x0 0x4000>;
303 sdio1: dwmmc@ff0e0000 {
304 compatible = "rockchip,rk3288-dw-mshc";
305 clock-freq-min-max = <400000 150000000>;
306 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
307 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
308 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
309 fifo-depth = <0x100>;
310 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
311 reg = <0x0 0xff0e0000 0x0 0x4000>;
315 emmc: dwmmc@ff0f0000 {
316 compatible = "rockchip,rk3288-dw-mshc";
317 clock-freq-min-max = <400000 150000000>;
318 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
319 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
320 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
321 fifo-depth = <0x100>;
322 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
323 reg = <0x0 0xff0f0000 0x0 0x4000>;
328 saradc: saradc@ff100000 {
329 compatible = "rockchip,saradc";
330 reg = <0x0 0xff100000 0x0 0x100>;
331 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
332 #io-channel-cells = <1>;
333 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
334 clock-names = "saradc", "apb_pclk";
335 resets = <&cru SRST_SARADC>;
336 reset-names = "saradc-apb";
341 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
342 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
343 clock-names = "spiclk", "apb_pclk";
344 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
345 dma-names = "tx", "rx";
346 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
347 pinctrl-names = "default";
348 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
349 reg = <0x0 0xff110000 0x0 0x1000>;
350 #address-cells = <1>;
356 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
357 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
358 clock-names = "spiclk", "apb_pclk";
359 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
360 dma-names = "tx", "rx";
361 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
362 pinctrl-names = "default";
363 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
364 reg = <0x0 0xff120000 0x0 0x1000>;
365 #address-cells = <1>;
371 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
372 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
373 clock-names = "spiclk", "apb_pclk";
374 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
375 dma-names = "tx", "rx";
376 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
377 pinctrl-names = "default";
378 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
379 reg = <0x0 0xff130000 0x0 0x1000>;
380 #address-cells = <1>;
386 compatible = "rockchip,rk3288-i2c";
387 reg = <0x0 0xff650000 0x0 0x1000>;
388 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
389 #address-cells = <1>;
392 clocks = <&cru PCLK_I2C0>;
393 pinctrl-names = "default";
394 pinctrl-0 = <&i2c0_xfer>;
399 compatible = "rockchip,rk3288-i2c";
400 reg = <0x0 0xff140000 0x0 0x1000>;
401 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
402 #address-cells = <1>;
405 clocks = <&cru PCLK_I2C1>;
406 pinctrl-names = "default";
407 pinctrl-0 = <&i2c1_xfer>;
412 compatible = "rockchip,rk3288-i2c";
413 reg = <0x0 0xff150000 0x0 0x1000>;
414 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
415 #address-cells = <1>;
418 clocks = <&cru PCLK_I2C3>;
419 pinctrl-names = "default";
420 pinctrl-0 = <&i2c3_xfer>;
425 compatible = "rockchip,rk3288-i2c";
426 reg = <0x0 0xff160000 0x0 0x1000>;
427 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
428 #address-cells = <1>;
431 clocks = <&cru PCLK_I2C4>;
432 pinctrl-names = "default";
433 pinctrl-0 = <&i2c4_xfer>;
438 compatible = "rockchip,rk3288-i2c";
439 reg = <0x0 0xff170000 0x0 0x1000>;
440 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
441 #address-cells = <1>;
444 clocks = <&cru PCLK_I2C5>;
445 pinctrl-names = "default";
446 pinctrl-0 = <&i2c5_xfer>;
450 uart0: serial@ff180000 {
451 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
452 reg = <0x0 0xff180000 0x0 0x100>;
453 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
456 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
457 clock-names = "baudclk", "apb_pclk";
458 pinctrl-names = "default";
459 pinctrl-0 = <&uart0_xfer>;
463 uart1: serial@ff190000 {
464 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
465 reg = <0x0 0xff190000 0x0 0x100>;
466 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
470 clock-names = "baudclk", "apb_pclk";
471 pinctrl-names = "default";
472 pinctrl-0 = <&uart1_xfer>;
476 uart2: serial@ff690000 {
477 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
478 reg = <0x0 0xff690000 0x0 0x100>;
479 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
483 clock-names = "baudclk", "apb_pclk";
484 pinctrl-names = "default";
485 pinctrl-0 = <&uart2_xfer>;
489 uart3: serial@ff1b0000 {
490 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
491 reg = <0x0 0xff1b0000 0x0 0x100>;
492 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
496 clock-names = "baudclk", "apb_pclk";
497 pinctrl-names = "default";
498 pinctrl-0 = <&uart3_xfer>;
502 uart4: serial@ff1c0000 {
503 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
504 reg = <0x0 0xff1c0000 0x0 0x100>;
505 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
509 clock-names = "baudclk", "apb_pclk";
510 pinctrl-names = "default";
511 pinctrl-0 = <&uart4_xfer>;
515 thermal_zones: thermal-zones {
516 soc_thermal: soc-thermal {
517 polling-delay-passive = <200>; /* milliseconds */
518 polling-delay = <1000>; /* milliseconds */
519 sustainable-power = <1200>; /* milliwatts */
521 thermal-sensors = <&tsadc 1>;
523 threshold: trip-point@0 {
524 temperature = <75000>; /* millicelsius */
525 hysteresis = <2000>; /* millicelsius */
528 target: trip-point@1 {
529 temperature = <85000>; /* millicelsius */
530 hysteresis = <2000>; /* millicelsius */
534 temperature = <90000>; /* millicelsius */
535 hysteresis = <2000>; /* millicelsius */
544 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
545 contribution = <1024>;
550 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
551 contribution = <1024>;
556 gpu_thermal: gpu-thermal {
557 polling-delay-passive = <200>; /* milliseconds */
558 polling-delay = <1000>; /* milliseconds */
559 thermal-sensors = <&tsadc 2>;
563 tsadc: tsadc@ff280000 {
564 compatible = "rockchip,rk3288-tsadc";
565 reg = <0x0 0xff280000 0x0 0x100>;
566 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
567 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
568 clock-names = "tsadc", "apb_pclk";
569 assigned-clocks = <&cru SCLK_TSADC>;
570 assigned-clock-rates = <5000>;
571 resets = <&cru SRST_TSADC>;
572 reset-names = "tsadc-apb";
573 pinctrl-names = "init", "default", "sleep";
574 pinctrl-0 = <&otp_gpio>;
575 pinctrl-1 = <&otp_out>;
576 pinctrl-2 = <&otp_gpio>;
577 #thermal-sensor-cells = <1>;
578 rockchip,hw-tshut-temp = <95000>;
582 gmac: ethernet@ff290000 {
583 compatible = "rockchip,rk3288-gmac";
584 reg = <0x0 0xff290000 0x0 0x10000>;
585 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
586 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
587 interrupt-names = "macirq", "eth_wake_irq";
588 rockchip,grf = <&grf>;
589 clocks = <&cru SCLK_MAC>,
590 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
591 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
592 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
593 clock-names = "stmmaceth",
594 "mac_clk_rx", "mac_clk_tx",
595 "clk_mac_ref", "clk_mac_refout",
596 "aclk_mac", "pclk_mac";
597 resets = <&cru SRST_MAC>;
598 reset-names = "stmmaceth";
602 usb_host0_ehci: usb@ff500000 {
603 compatible = "generic-ehci";
604 reg = <0x0 0xff500000 0x0 0x100>;
605 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&cru HCLK_USBHOST0>;
607 clock-names = "usbhost";
613 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
615 usb_host1: usb@ff540000 {
616 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
618 reg = <0x0 0xff540000 0x0 0x40000>;
619 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
620 clocks = <&cru HCLK_USBHOST1>;
624 phy-names = "usb2-phy";
628 usb_otg: usb@ff580000 {
629 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
631 reg = <0x0 0xff580000 0x0 0x40000>;
632 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
633 clocks = <&cru HCLK_OTG0>;
636 g-np-tx-fifo-size = <16>;
637 g-rx-fifo-size = <275>;
638 g-tx-fifo-size = <256 128 128 64 64 32>;
641 phy-names = "usb2-phy";
645 usb_hsic: usb@ff5c0000 {
646 compatible = "generic-ehci";
647 reg = <0x0 0xff5c0000 0x0 0x100>;
648 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&cru HCLK_HSIC>;
650 clock-names = "usbhost";
655 compatible = "rockchip,rk3288-dmc", "syscon";
656 rockchip,cru = <&cru>;
657 rockchip,grf = <&grf>;
658 rockchip,pmu = <&pmu>;
659 rockchip,sgrf = <&sgrf>;
660 rockchip,noc = <&noc>;
661 reg = <0x0 0xff610000 0x0 0x3fc
662 0x0 0xff620000 0x0 0x294
663 0x0 0xff630000 0x0 0x3fc
664 0x0 0xff640000 0x0 0x294>;
665 rockchip,sram = <&ddr_sram>;
666 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
667 <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
668 <&cru ARMCLK>, <&cru ACLK_DMAC1>;
669 clock-names = "pclk_ddrupctl0", "pclk_publ0",
670 "pclk_ddrupctl1", "pclk_publ1",
671 "arm_clk", "aclk_dmac1";
675 compatible = "rockchip,rk3288-i2c";
676 reg = <0x0 0xff660000 0x0 0x1000>;
677 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
678 #address-cells = <1>;
681 clocks = <&cru PCLK_I2C2>;
682 pinctrl-names = "default";
683 pinctrl-0 = <&i2c2_xfer>;
688 compatible = "rockchip,rk3288-pwm";
689 reg = <0x0 0xff680000 0x0 0x10>;
691 pinctrl-names = "default";
692 pinctrl-0 = <&pwm0_pin>;
693 clocks = <&cru PCLK_PWM>;
699 compatible = "rockchip,rk3288-pwm";
700 reg = <0x0 0xff680010 0x0 0x10>;
702 pinctrl-names = "default";
703 pinctrl-0 = <&pwm1_pin>;
704 clocks = <&cru PCLK_PWM>;
710 compatible = "rockchip,rk3288-pwm";
711 reg = <0x0 0xff680020 0x0 0x10>;
713 pinctrl-names = "default";
714 pinctrl-0 = <&pwm2_pin>;
715 clocks = <&cru PCLK_PWM>;
721 compatible = "rockchip,rk3288-pwm";
722 reg = <0x0 0xff680030 0x0 0x10>;
724 pinctrl-names = "default";
725 pinctrl-0 = <&pwm3_pin>;
726 clocks = <&cru PCLK_PWM>;
731 timer: timer@ff6b0000 {
732 compatible = "rockchip,rk3288-timer";
733 reg = <0x0 0xff6b0000 0x0 0x20>;
734 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
735 clocks = <&xin24m>, <&cru PCLK_TIMER>;
736 clock-names = "timer", "pclk";
739 bus_intmem@ff700000 {
740 compatible = "mmio-sram";
741 reg = <0x0 0xff700000 0x0 0x18000>;
742 #address-cells = <1>;
744 ranges = <0 0x0 0xff700000 0x18000>;
746 compatible = "rockchip,rk3066-smp-sram";
749 ddr_sram: ddr-sram@1000 {
750 compatible = "rockchip,rk3288-ddr-sram";
751 reg = <0x1000 0x4000>;
756 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
757 reg = <0x0 0xff720000 0x0 0x1000>;
760 qos_gpu_r: qos@ffaa0000 {
761 compatible = "syscon";
762 reg = <0x0 0xffaa0000 0x0 0x20>;
765 qos_gpu_w: qos@ffaa0080 {
766 compatible = "syscon";
767 reg = <0x0 0xffaa0080 0x0 0x20>;
770 qos_vio1_vop: qos@ffad0000 {
771 compatible = "syscon";
772 reg = <0x0 0xffad0000 0x0 0x20>;
775 qos_vio1_isp_w0: qos@ffad0100 {
776 compatible = "syscon";
777 reg = <0x0 0xffad0100 0x0 0x20>;
780 qos_vio1_isp_w1: qos@ffad0180 {
781 compatible = "syscon";
782 reg = <0x0 0xffad0180 0x0 0x20>;
785 qos_vio0_vop: qos@ffad0400 {
786 compatible = "syscon";
787 reg = <0x0 0xffad0400 0x0 0x20>;
790 qos_vio0_vip: qos@ffad0480 {
791 compatible = "syscon";
792 reg = <0x0 0xffad0480 0x0 0x20>;
795 qos_vio0_iep: qos@ffad0500 {
796 compatible = "syscon";
797 reg = <0x0 0xffad0500 0x0 0x20>;
800 qos_vio2_rga_r: qos@ffad0800 {
801 compatible = "syscon";
802 reg = <0x0 0xffad0800 0x0 0x20>;
805 qos_vio2_rga_w: qos@ffad0880 {
806 compatible = "syscon";
807 reg = <0x0 0xffad0880 0x0 0x20>;
810 qos_vio1_isp_r: qos@ffad0900 {
811 compatible = "syscon";
812 reg = <0x0 0xffad0900 0x0 0x20>;
815 qos_video: qos@ffae0000 {
816 compatible = "syscon";
817 reg = <0x0 0xffae0000 0x0 0x20>;
820 qos_hevc_r: qos@ffaf0000 {
821 compatible = "syscon";
822 reg = <0x0 0xffaf0000 0x0 0x20>;
825 qos_hevc_w: qos@ffaf0080 {
826 compatible = "syscon";
827 reg = <0x0 0xffaf0080 0x0 0x20>;
830 pmu: power-management@ff730000 {
831 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
832 reg = <0x0 0xff730000 0x0 0x100>;
834 power: power-controller {
835 compatible = "rockchip,rk3288-power-controller";
836 #power-domain-cells = <1>;
837 #address-cells = <1>;
841 * Note: Although SCLK_* are the working clocks
842 * of device without including on the NOC, needed for
845 * The clocks on the which NOC:
846 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
847 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
848 * ACLK_RGA is on ACLK_RGA_NIU.
849 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
851 * Which clock are device clocks:
853 * *_IEP IEP:Image Enhancement Processor
854 * *_ISP ISP:Image Signal Processing
855 * *_VIP VIP:Video Input Processor
856 * *_VOP* VOP:Visual Output Processor
863 pd_vio@RK3288_PD_VIO {
864 reg = <RK3288_PD_VIO>;
865 clocks = <&cru ACLK_IEP>,
879 <&cru PCLK_EDP_CTRL>,
880 <&cru PCLK_HDMI_CTRL>,
881 <&cru PCLK_LVDS_PHY>,
882 <&cru PCLK_MIPI_CSI>,
883 <&cru PCLK_MIPI_DSI0>,
884 <&cru PCLK_MIPI_DSI1>,
890 pm_qos = <&qos_vio0_iep>,
902 * Note: The following 3 are HEVC(H.265) clocks,
903 * and on the ACLK_HEVC_NIU (NOC).
905 pd_hevc@RK3288_PD_HEVC {
906 reg = <RK3288_PD_HEVC>;
907 clocks = <&cru ACLK_HEVC>,
908 <&cru SCLK_HEVC_CABAC>,
909 <&cru SCLK_HEVC_CORE>;
910 pm_qos = <&qos_hevc_r>,
915 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
916 * (video endecoder & decoder) clocks that on the
917 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
919 pd_video@RK3288_PD_VIDEO {
920 reg = <RK3288_PD_VIDEO>;
921 clocks = <&cru ACLK_VCODEC>,
923 pm_qos = <&qos_video>;
927 * Note: ACLK_GPU is the GPU clock,
928 * and on the ACLK_GPU_NIU (NOC).
930 pd_gpu@RK3288_PD_GPU {
931 reg = <RK3288_PD_GPU>;
932 clocks = <&cru ACLK_GPU>;
933 pm_qos = <&qos_gpu_r>,
939 compatible = "syscon-reboot-mode";
941 mode-normal = <BOOT_NORMAL>;
942 mode-recovery = <BOOT_RECOVERY>;
943 mode-bootloader = <BOOT_FASTBOOT>;
944 mode-loader = <BOOT_BL_DOWNLOAD>;
945 mode-ums = <BOOT_UMS>;
949 sgrf: syscon@ff740000 {
950 compatible = "rockchip,rk3288-sgrf", "syscon";
951 reg = <0x0 0xff740000 0x0 0x1000>;
954 cru: clock-controller@ff760000 {
955 compatible = "rockchip,rk3288-cru";
956 reg = <0x0 0xff760000 0x0 0x1000>;
957 rockchip,grf = <&grf>;
960 assigned-clocks = <&cru PLL_GPLL>,
961 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
962 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
963 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
965 assigned-clock-rates = <594000000>,
966 <500000000>, <300000000>,
967 <150000000>, <75000000>,
968 <300000000>, <150000000>,
972 grf: syscon@ff770000 {
973 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
974 reg = <0x0 0xff770000 0x0 0x1000>;
977 compatible = "rockchip,rk3288-dp-phy";
978 clocks = <&cru SCLK_EDP_24M>;
984 io_domains: io-domains {
985 compatible = "rockchip,rk3288-io-voltage-domain";
990 compatible = "rockchip,rk3288-usb-phy";
991 #address-cells = <1>;
995 usbphy0: usb-phy@320 {
998 clocks = <&cru SCLK_OTGPHY0>;
999 clock-names = "phyclk";
1001 resets = <&cru SRST_USBOTG_PHY>;
1002 reset-names = "phy-reset";
1005 usbphy1: usb-phy@334 {
1008 clocks = <&cru SCLK_OTGPHY1>;
1009 clock-names = "phyclk";
1013 usbphy2: usb-phy@348 {
1016 clocks = <&cru SCLK_OTGPHY2>;
1017 clock-names = "phyclk";
1019 resets = <&cru SRST_USBHOST1_PHY>;
1020 reset-names = "phy-reset";
1025 wdt: watchdog@ff800000 {
1026 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
1027 reg = <0x0 0xff800000 0x0 0x100>;
1028 clocks = <&cru PCLK_WDT>;
1029 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1030 status = "disabled";
1033 spdif: sound@ff8b0000 {
1034 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
1035 reg = <0x0 0xff8b0000 0x0 0x10000>;
1036 #sound-dai-cells = <0>;
1037 clock-names = "hclk", "mclk";
1038 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
1039 dmas = <&dmac_bus_s 3>;
1041 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1042 pinctrl-names = "default";
1043 pinctrl-0 = <&spdif_tx>;
1044 rockchip,grf = <&grf>;
1045 status = "disabled";
1049 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
1050 reg = <0x0 0xff890000 0x0 0x10000>;
1051 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1052 #address-cells = <1>;
1054 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
1055 dma-names = "tx", "rx";
1056 clock-names = "i2s_hclk", "i2s_clk";
1057 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
1058 pinctrl-names = "default";
1059 pinctrl-0 = <&i2s0_bus>;
1060 rockchip,playback-channels = <8>;
1061 rockchip,capture-channels = <2>;
1062 status = "disabled";
1066 compatible = "rockchip,iep";
1067 iommu_enabled = <1>;
1068 iommus = <&iep_mmu>;
1069 reg = <0x0 0xff900000 0x0 0x800>;
1070 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1071 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1072 clock-names = "aclk_iep", "hclk_iep";
1073 power-domains = <&power RK3288_PD_VIO>;
1076 status = "disabled";
1079 iep_mmu: iommu@ff900800 {
1080 compatible = "rockchip,iommu";
1081 reg = <0x0 0xff900800 0x0 0x40>;
1082 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1083 interrupt-names = "iep_mmu";
1085 status = "disabled";
1088 cif_isp0: cif_isp@ff910000 {
1089 compatible = "rockchip,rk3288-cif-isp";
1090 rockchip,grf = <&grf>;
1091 reg = <0x0 0xff910000 0x0 0x4000>, <0x0 0xff968000 0x0 0x4000>;
1092 reg-names = "register", "csihost-register";
1093 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1094 <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
1095 <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
1096 <&cru SCLK_MIPIDSI_24M>;
1097 clock-names = "aclk_isp", "hclk_isp",
1098 "sclk_isp", "sclk_isp_jpe",
1099 "pclk_mipi_csi", "pclk_isp_in",
1101 resets = <&cru SRST_ISP>;
1102 reset-names = "rst_isp";
1103 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1104 interrupt-names = "cif_isp10_irq";
1105 power-domains = <&power RK3288_PD_VIO>;
1106 rockchip,isp,iommu-enable = <1>;
1107 iommus = <&isp_mmu>;
1108 status = "disabled";
1112 compatible = "rockchip,rk3288-isp", "rockchip,isp";
1113 reg = <0x0 0xff910000 0x0 0x4000>;
1114 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1115 power-domains = <&power RK3288_PD_VIO>;
1117 <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
1118 <&cru SCLK_ISP_JPE>, <&cru PCLK_ISP_IN>,
1119 <&cru SCLK_VIP_OUT>, <&cru SCLK_MIPIDSI_24M>,
1120 <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>;
1122 "aclk_isp", "hclk_isp", "clk_isp",
1123 "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
1124 "clk_mipi_24m", "clk_cif_pll", "hclk_mipiphy1";
1126 "default", "isp_dvp8bit2", "isp_dvp10bit",
1127 "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl",
1128 "isp_mipi_fl_prefl", "isp_flash_as_gpio",
1129 "isp_flash_as_trigger_out";
1130 pinctrl-0 = <&isp_mipi>;
1131 pinctrl-1 = <&isp_mipi &isp_dvp_d2d9>;
1132 pinctrl-2 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1>;
1133 pinctrl-3 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1
1135 pinctrl-4 = <&isp_mipi &isp_dvp_d0d7>;
1136 pinctrl-5 = <&isp_mipi>;
1137 pinctrl-6 = <&isp_mipi &isp_prelight>;
1138 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1139 pinctrl-8 = <&isp_flash_trigger>;
1140 rockchip,isp,mipiphy = <2>;
1141 rockchip,isp,cifphy = <1>;
1142 rockchip,isp,mipiphy1,reg = <0xff968000 0x4000>;
1143 rockchip,grf = <&grf>;
1144 rockchip,cru = <&cru>;
1145 rockchip,gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>;
1146 rockchip,isp,iommu_enable = <1>;
1147 iommus = <&isp_mmu>;
1148 status = "disabled";
1151 isp_mmu: iommu@ff914000 {
1152 compatible = "rockchip,iommu";
1153 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1154 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1155 interrupt-names = "isp_mmu";
1156 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1157 clock-names = "aclk", "hclk";
1158 rk_iommu,disable_reset_quirk;
1160 power-domains = <&power RK3288_PD_VIO>;
1161 status = "disabled";
1165 compatible = "rockchip,rk3288-rga";
1166 reg = <0x0 0xff920000 0x0 0x180>;
1167 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1168 interrupt-names = "rga";
1169 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1170 clock-names = "aclk", "hclk", "sclk";
1171 power-domains = <&power RK3288_PD_VIO>;
1172 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1173 reset-names = "core", "axi", "ahb";
1175 status = "disabled";
1178 vopb: vop@ff930000 {
1179 compatible = "rockchip,rk3288-vop";
1180 reg = <0x0 0xff930000 0x0 0x19c>, <0x0 0xff931000 0x0 0x1000>;
1181 reg-names = "regs", "gamma_lut";
1182 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1183 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1184 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1185 power-domains = <&power RK3288_PD_VIO>;
1186 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1187 reset-names = "axi", "ahb", "dclk";
1188 iommus = <&vopb_mmu>;
1189 status = "disabled";
1192 #address-cells = <1>;
1195 vopb_out_hdmi: endpoint@0 {
1197 remote-endpoint = <&hdmi_in_vopb>;
1200 vopb_out_edp: endpoint@1 {
1202 remote-endpoint = <&edp_in_vopb>;
1205 vopb_out_dsi0: endpoint@2 {
1207 remote-endpoint = <&dsi0_in_vopb>;
1210 vopb_out_lvds: endpoint@3 {
1212 remote-endpoint = <&lvds_in_vopb>;
1217 vopb_mmu: iommu@ff930300 {
1218 compatible = "rockchip,iommu";
1219 reg = <0x0 0xff930300 0x0 0x100>;
1220 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1221 interrupt-names = "vopb_mmu";
1222 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1223 clock-names = "aclk", "hclk";
1224 power-domains = <&power RK3288_PD_VIO>;
1226 status = "disabled";
1229 vopl: vop@ff940000 {
1230 compatible = "rockchip,rk3288-vop";
1231 reg = <0x0 0xff940000 0x0 0x19c>, <0x0 0xff941000 0x0 0x1000>;
1232 reg-names = "regs", "gamma_lut";
1233 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1234 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1235 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1236 power-domains = <&power RK3288_PD_VIO>;
1237 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1238 reset-names = "axi", "ahb", "dclk";
1239 iommus = <&vopl_mmu>;
1240 status = "disabled";
1243 #address-cells = <1>;
1246 vopl_out_hdmi: endpoint@0 {
1248 remote-endpoint = <&hdmi_in_vopl>;
1251 vopl_out_edp: endpoint@1 {
1253 remote-endpoint = <&edp_in_vopl>;
1256 vopl_out_dsi0: endpoint@2 {
1258 remote-endpoint = <&dsi0_in_vopl>;
1261 vopl_out_lvds: endpoint@3 {
1263 remote-endpoint = <&lvds_in_vopl>;
1269 vopl_mmu: iommu@ff940300 {
1270 compatible = "rockchip,iommu";
1271 reg = <0x0 0xff940300 0x0 0x100>;
1272 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1273 interrupt-names = "vopl_mmu";
1274 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1275 clock-names = "aclk", "hclk";
1276 power-domains = <&power RK3288_PD_VIO>;
1278 status = "disabled";
1281 dsi0: dsi@ff960000 {
1282 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1283 reg = <0x0 0xff960000 0x0 0x4000>;
1284 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1285 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1286 clock-names = "ref", "pclk";
1287 power-domains = <&power RK3288_PD_VIO>;
1288 rockchip,grf = <&grf>;
1289 #address-cells = <1>;
1291 status = "disabled";
1295 #address-cells = <1>;
1297 dsi0_in_vopb: endpoint@0 {
1299 remote-endpoint = <&vopb_out_dsi0>;
1301 dsi0_in_vopl: endpoint@1 {
1303 remote-endpoint = <&vopl_out_dsi0>;
1310 compatible = "rockchip,rk3288-dp";
1311 reg = <0x0 0xff970000 0x0 0x4000>;
1312 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1313 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1314 clock-names = "dp", "pclk";
1315 power-domains = <&power RK3288_PD_VIO>;
1318 resets = <&cru SRST_EDP>;
1320 rockchip,grf = <&grf>;
1321 status = "disabled";
1324 #address-cells = <1>;
1328 #address-cells = <1>;
1330 edp_in_vopb: endpoint@0 {
1332 remote-endpoint = <&vopb_out_edp>;
1334 edp_in_vopl: endpoint@1 {
1336 remote-endpoint = <&vopl_out_edp>;
1342 lvds: lvds@ff96c000 {
1343 compatible = "rockchip,rk3288-lvds";
1344 reg = <0x0 0xff96c000 0x0 0x4000>;
1345 clocks = <&cru PCLK_LVDS_PHY>;
1346 clock-names = "pclk_lvds";
1347 pinctrl-names = "default";
1348 pinctrl-0 = <&lcdc0_ctl>;
1349 power-domains = <&power RK3288_PD_VIO>;
1350 rockchip,grf = <&grf>;
1351 status = "disabled";
1354 #address-cells = <1>;
1360 #address-cells = <1>;
1363 lvds_in_vopb: endpoint@0 {
1365 remote-endpoint = <&vopb_out_lvds>;
1367 lvds_in_vopl: endpoint@1 {
1369 remote-endpoint = <&vopl_out_lvds>;
1375 hdmi: hdmi@ff980000 {
1376 compatible = "rockchip,rk3288-dw-hdmi";
1377 reg = <0x0 0xff980000 0x0 0x20000>;
1379 rockchip,grf = <&grf>;
1380 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1381 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1382 clock-names = "iahb", "isfr";
1383 pinctrl-names = "default";
1384 pinctrl-0 = <&hdmi_ddc>;
1385 power-domains = <&power RK3288_PD_VIO>;
1386 status = "disabled";
1390 #address-cells = <1>;
1392 hdmi_in_vopb: endpoint@0 {
1394 remote-endpoint = <&vopb_out_hdmi>;
1396 hdmi_in_vopl: endpoint@1 {
1398 remote-endpoint = <&vopl_out_hdmi>;
1404 vpu: video-codec@ff9a0000 {
1405 compatible = "rockchip,rk3288-vpu";
1406 reg = <0x0 0xff9a0000 0x0 0x800>;
1407 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1408 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1409 interrupt-names = "vepu", "vdpu";
1410 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1411 clock-names = "aclk", "hclk";
1412 power-domains = <&power RK3288_PD_VIDEO>;
1413 iommus = <&vpu_mmu>;
1414 assigned-clocks = <&cru ACLK_VCODEC>;
1415 assigned-clock-rates = <400000000>;
1416 status = "disabled";
1419 vpu_service: vpu-service@ff9a0000 {
1420 compatible = "rockchip,vpu_service";
1421 reg = <0x0 0xff9a0000 0x0 0x800>;
1422 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1423 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1424 interrupt-names = "irq_enc", "irq_dec";
1425 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1426 clock-names = "aclk_vcodec", "hclk_vcodec";
1427 power-domains = <&power RK3288_PD_VIDEO>;
1428 rockchip,grf = <&grf>;
1429 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
1430 reset-names = "video_a", "video_h";
1431 iommus = <&vpu_mmu>;
1432 iommu_enabled = <1>;
1433 status = "disabled";
1434 /* 0 means ion, 1 means drm */
1438 vpu_mmu: iommu@ff9a0800 {
1439 compatible = "rockchip,iommu";
1440 reg = <0x0 0xff9a0800 0x0 0x100>;
1441 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1442 interrupt-names = "vpu_mmu";
1443 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1444 clock-names = "aclk", "hclk";
1445 power-domains = <&power RK3288_PD_VIDEO>;
1449 hevc_service: hevc-service@ff9c0000 {
1450 compatible = "rockchip,hevc_service";
1451 reg = <0x0 0xff9c0000 0x0 0x400>;
1452 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1453 interrupt-names = "irq_dec";
1454 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1455 <&cru SCLK_HEVC_CORE>,
1456 <&cru SCLK_HEVC_CABAC>;
1457 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
1460 * The 4K hevc would also work well with 500/125/300/300,
1461 * no more err irq and reset request.
1463 assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1464 <&cru SCLK_HEVC_CORE>,
1465 <&cru SCLK_HEVC_CABAC>;
1466 assigned-clock-rates = <400000000>, <100000000>,
1467 <300000000>, <300000000>;
1469 resets = <&cru SRST_HEVC>;
1470 reset-names = "video";
1471 power-domains = <&power RK3288_PD_HEVC>;
1472 rockchip,grf = <&grf>;
1473 iommus = <&hevc_mmu>;
1474 iommu_enabled = <1>;
1475 status = "disabled";
1476 /* 0 means ion, 1 means drm */
1480 hevc_mmu: iommu@ff9c0440 {
1481 compatible = "rockchip,iommu";
1482 reg = <0x0 0xff9c0440 0x0 0x40>, <0x0 0xff9c0480 0x0 0x40>;
1483 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1484 interrupt-names = "hevc_mmu";
1485 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1486 <&cru SCLK_HEVC_CORE>,
1487 <&cru SCLK_HEVC_CABAC>;
1488 clock-names = "aclk", "hclk", "clk_core",
1490 power-domains = <&power RK3288_PD_HEVC>;
1495 compatible = "arm,malit764",
1499 reg = <0x0 0xffa30000 0x0 0x10000>;
1500 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1501 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1502 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1503 interrupt-names = "JOB", "MMU", "GPU";
1504 clocks = <&cru ACLK_GPU>;
1505 clock-names = "clk_mali";
1506 operating-points-v2 = <&gpu_opp_table>;
1507 #cooling-cells = <2>; /* min followed by max */
1508 power-domains = <&power RK3288_PD_GPU>;
1509 status = "disabled";
1512 downdifferential = <10>;
1514 gpu_power_model: power_model {
1515 compatible = "arm,mali-simple-power-model";
1518 static-power = <300>;
1519 dynamic-power = <396>;
1520 ts = <32000 4700 (-80) 2>;
1521 thermal-zone = "gpu-thermal";
1525 gpu_opp_table: opp-table1 {
1526 compatible = "operating-points-v2";
1529 opp-hz = /bits/ 64 <100000000>;
1530 opp-microvolt = <950000>;
1533 opp-hz = /bits/ 64 <200000000>;
1534 opp-microvolt = <950000>;
1537 opp-hz = /bits/ 64 <300000000>;
1538 opp-microvolt = <1000000>;
1541 opp-hz = /bits/ 64 <400000000>;
1542 opp-microvolt = <1100000>;
1545 opp-hz = /bits/ 64 <600000000>;
1546 opp-microvolt = <1250000>;
1550 noc: syscon@ffac0000 {
1551 compatible = "rockchip,rk3288-noc", "syscon";
1552 reg = <0x0 0xffac0000 0x0 0x2000>;
1555 efuse: efuse@ffb40000 {
1556 compatible = "rockchip,rockchip-efuse";
1557 reg = <0x0 0xffb40000 0x0 0x20>;
1558 #address-cells = <1>;
1560 clocks = <&cru PCLK_EFUSE256>;
1561 clock-names = "pclk_efuse";
1563 cpu_leakage: cpu_leakage@17 {
1568 gic: interrupt-controller@ffc01000 {
1569 compatible = "arm,gic-400";
1570 interrupt-controller;
1571 #interrupt-cells = <3>;
1572 #address-cells = <0>;
1574 reg = <0x0 0xffc01000 0x0 0x1000>,
1575 <0x0 0xffc02000 0x0 0x2000>,
1576 <0x0 0xffc04000 0x0 0x2000>,
1577 <0x0 0xffc06000 0x0 0x2000>;
1578 interrupts = <GIC_PPI 9 0xf04>;
1582 compatible = "rockchip,rk3288-pinctrl";
1583 rockchip,grf = <&grf>;
1584 rockchip,pmu = <&pmu>;
1585 #address-cells = <2>;
1589 gpio0: gpio0@ff750000 {
1590 compatible = "rockchip,gpio-bank";
1591 reg = <0x0 0xff750000 0x0 0x100>;
1592 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1593 clocks = <&cru PCLK_GPIO0>;
1598 interrupt-controller;
1599 #interrupt-cells = <2>;
1602 gpio1: gpio1@ff780000 {
1603 compatible = "rockchip,gpio-bank";
1604 reg = <0x0 0xff780000 0x0 0x100>;
1605 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1606 clocks = <&cru PCLK_GPIO1>;
1611 interrupt-controller;
1612 #interrupt-cells = <2>;
1615 gpio2: gpio2@ff790000 {
1616 compatible = "rockchip,gpio-bank";
1617 reg = <0x0 0xff790000 0x0 0x100>;
1618 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1619 clocks = <&cru PCLK_GPIO2>;
1624 interrupt-controller;
1625 #interrupt-cells = <2>;
1628 gpio3: gpio3@ff7a0000 {
1629 compatible = "rockchip,gpio-bank";
1630 reg = <0x0 0xff7a0000 0x0 0x100>;
1631 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1632 clocks = <&cru PCLK_GPIO3>;
1637 interrupt-controller;
1638 #interrupt-cells = <2>;
1641 gpio4: gpio4@ff7b0000 {
1642 compatible = "rockchip,gpio-bank";
1643 reg = <0x0 0xff7b0000 0x0 0x100>;
1644 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1645 clocks = <&cru PCLK_GPIO4>;
1650 interrupt-controller;
1651 #interrupt-cells = <2>;
1654 gpio5: gpio5@ff7c0000 {
1655 compatible = "rockchip,gpio-bank";
1656 reg = <0x0 0xff7c0000 0x0 0x100>;
1657 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1658 clocks = <&cru PCLK_GPIO5>;
1663 interrupt-controller;
1664 #interrupt-cells = <2>;
1667 gpio6: gpio6@ff7d0000 {
1668 compatible = "rockchip,gpio-bank";
1669 reg = <0x0 0xff7d0000 0x0 0x100>;
1670 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1671 clocks = <&cru PCLK_GPIO6>;
1676 interrupt-controller;
1677 #interrupt-cells = <2>;
1680 gpio7: gpio7@ff7e0000 {
1681 compatible = "rockchip,gpio-bank";
1682 reg = <0x0 0xff7e0000 0x0 0x100>;
1683 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1684 clocks = <&cru PCLK_GPIO7>;
1689 interrupt-controller;
1690 #interrupt-cells = <2>;
1693 gpio8: gpio8@ff7f0000 {
1694 compatible = "rockchip,gpio-bank";
1695 reg = <0x0 0xff7f0000 0x0 0x100>;
1696 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1697 clocks = <&cru PCLK_GPIO8>;
1702 interrupt-controller;
1703 #interrupt-cells = <2>;
1707 hdmi_ddc: hdmi-ddc {
1708 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1709 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1713 pcfg_pull_up: pcfg-pull-up {
1717 pcfg_pull_down: pcfg-pull-down {
1721 pcfg_pull_none: pcfg-pull-none {
1725 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1727 drive-strength = <12>;
1731 global_pwroff: global-pwroff {
1732 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1735 ddrio_pwroff: ddrio-pwroff {
1736 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1739 ddr0_retention: ddr0-retention {
1740 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1743 ddr1_retention: ddr1-retention {
1744 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1750 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1755 i2c0_xfer: i2c0-xfer {
1756 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1757 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1762 i2c1_xfer: i2c1-xfer {
1763 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1764 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1769 i2c2_xfer: i2c2-xfer {
1770 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1771 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1776 i2c3_xfer: i2c3-xfer {
1777 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1778 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1783 i2c4_xfer: i2c4-xfer {
1784 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1785 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1790 i2c5_xfer: i2c5-xfer {
1791 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1792 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1797 i2s0_bus: i2s0-bus {
1798 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1799 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1800 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1801 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1802 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1803 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1808 lcdc0_ctl: lcdc0-ctl {
1809 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1810 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1811 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1812 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1817 sdmmc_clk: sdmmc-clk {
1818 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1821 sdmmc_cmd: sdmmc-cmd {
1822 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1825 sdmmc_cd: sdmmc-cd {
1826 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1829 sdmmc_bus1: sdmmc-bus1 {
1830 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1833 sdmmc_bus4: sdmmc-bus4 {
1834 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1835 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1836 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1837 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1842 sdio0_bus1: sdio0-bus1 {
1843 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1846 sdio0_bus4: sdio0-bus4 {
1847 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1848 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1849 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1850 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1853 sdio0_cmd: sdio0-cmd {
1854 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1857 sdio0_clk: sdio0-clk {
1858 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1861 sdio0_cd: sdio0-cd {
1862 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1865 sdio0_wp: sdio0-wp {
1866 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1869 sdio0_pwr: sdio0-pwr {
1870 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1873 sdio0_bkpwr: sdio0-bkpwr {
1874 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1877 sdio0_int: sdio0-int {
1878 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1883 sdio1_bus1: sdio1-bus1 {
1884 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1887 sdio1_bus4: sdio1-bus4 {
1888 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1889 <3 25 4 &pcfg_pull_up>,
1890 <3 26 4 &pcfg_pull_up>,
1891 <3 27 4 &pcfg_pull_up>;
1894 sdio1_cd: sdio1-cd {
1895 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1898 sdio1_wp: sdio1-wp {
1899 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1902 sdio1_bkpwr: sdio1-bkpwr {
1903 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1906 sdio1_int: sdio1-int {
1907 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1910 sdio1_cmd: sdio1-cmd {
1911 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1914 sdio1_clk: sdio1-clk {
1915 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1918 sdio1_pwr: sdio1-pwr {
1919 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1924 emmc_clk: emmc-clk {
1925 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1928 emmc_cmd: emmc-cmd {
1929 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1932 emmc_pwr: emmc-pwr {
1933 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1936 emmc_bus1: emmc-bus1 {
1937 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1940 emmc_bus4: emmc-bus4 {
1941 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1942 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1943 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1944 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1947 emmc_bus8: emmc-bus8 {
1948 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1949 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1950 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1951 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1952 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1953 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1954 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1955 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1960 spi0_clk: spi0-clk {
1961 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1963 spi0_cs0: spi0-cs0 {
1964 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1967 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1970 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1972 spi0_cs1: spi0-cs1 {
1973 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1977 spi1_clk: spi1-clk {
1978 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1980 spi1_cs0: spi1-cs0 {
1981 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1984 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1987 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1992 spi2_cs1: spi2-cs1 {
1993 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1995 spi2_clk: spi2-clk {
1996 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1998 spi2_cs0: spi2-cs0 {
1999 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
2002 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
2005 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
2010 uart0_xfer: uart0-xfer {
2011 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
2012 <4 17 RK_FUNC_1 &pcfg_pull_none>;
2015 uart0_cts: uart0-cts {
2016 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
2019 uart0_rts: uart0-rts {
2020 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
2025 uart1_xfer: uart1-xfer {
2026 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
2027 <5 9 RK_FUNC_1 &pcfg_pull_none>;
2030 uart1_cts: uart1-cts {
2031 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
2034 uart1_rts: uart1-rts {
2035 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
2040 uart2_xfer: uart2-xfer {
2041 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
2042 <7 23 RK_FUNC_1 &pcfg_pull_none>;
2044 /* no rts / cts for uart2 */
2048 uart3_xfer: uart3-xfer {
2049 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
2050 <7 8 RK_FUNC_1 &pcfg_pull_none>;
2053 uart3_cts: uart3-cts {
2054 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
2057 uart3_rts: uart3-rts {
2058 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
2063 uart4_xfer: uart4-xfer {
2064 rockchip,pins = <5 12 3 &pcfg_pull_up>,
2065 <5 13 3 &pcfg_pull_none>;
2068 uart4_cts: uart4-cts {
2069 rockchip,pins = <5 14 3 &pcfg_pull_up>;
2072 uart4_rts: uart4-rts {
2073 rockchip,pins = <5 15 3 &pcfg_pull_none>;
2078 otp_gpio: otp-gpio {
2079 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
2083 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
2088 pwm0_pin: pwm0-pin {
2089 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
2094 pwm1_pin: pwm1-pin {
2095 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
2100 pwm2_pin: pwm2-pin {
2101 rockchip,pins = <7 22 3 &pcfg_pull_none>;
2106 pwm3_pin: pwm3-pin {
2107 rockchip,pins = <7 23 3 &pcfg_pull_none>;
2112 rgmii_pins: rgmii-pins {
2113 rockchip,pins = <3 30 3 &pcfg_pull_none>,
2114 <3 31 3 &pcfg_pull_none>,
2115 <3 26 3 &pcfg_pull_none>,
2116 <3 27 3 &pcfg_pull_none>,
2117 <3 28 3 &pcfg_pull_none_12ma>,
2118 <3 29 3 &pcfg_pull_none_12ma>,
2119 <3 24 3 &pcfg_pull_none_12ma>,
2120 <3 25 3 &pcfg_pull_none_12ma>,
2121 <4 0 3 &pcfg_pull_none>,
2122 <4 5 3 &pcfg_pull_none>,
2123 <4 6 3 &pcfg_pull_none>,
2124 <4 9 3 &pcfg_pull_none_12ma>,
2125 <4 4 3 &pcfg_pull_none_12ma>,
2126 <4 1 3 &pcfg_pull_none>,
2127 <4 3 3 &pcfg_pull_none>;
2130 rmii_pins: rmii-pins {
2131 rockchip,pins = <3 30 3 &pcfg_pull_none>,
2132 <3 31 3 &pcfg_pull_none>,
2133 <3 28 3 &pcfg_pull_none>,
2134 <3 29 3 &pcfg_pull_none>,
2135 <4 0 3 &pcfg_pull_none>,
2136 <4 5 3 &pcfg_pull_none>,
2137 <4 4 3 &pcfg_pull_none>,
2138 <4 1 3 &pcfg_pull_none>,
2139 <4 2 3 &pcfg_pull_none>,
2140 <4 3 3 &pcfg_pull_none>;
2145 spdif_tx: spdif-tx {
2146 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
2151 cif_dvp_d2d9: cif-dvp-d2d9 {
2152 rockchip,pins = <2 0 RK_FUNC_1 &pcfg_pull_none>,
2153 <2 1 RK_FUNC_1 &pcfg_pull_none>,
2154 <2 2 RK_FUNC_1 &pcfg_pull_none>,
2155 <2 3 RK_FUNC_1 &pcfg_pull_none>,
2156 <2 4 RK_FUNC_1 &pcfg_pull_none>,
2157 <2 5 RK_FUNC_1 &pcfg_pull_none>,
2158 <2 6 RK_FUNC_1 &pcfg_pull_none>,
2159 <2 7 RK_FUNC_1 &pcfg_pull_none>,
2160 <2 8 RK_FUNC_1 &pcfg_pull_none>,
2161 <2 9 RK_FUNC_1 &pcfg_pull_none>,
2162 <2 11 RK_FUNC_1 &pcfg_pull_none>;
2167 isp_mipi: isp-mipi {
2170 <2 11 RK_FUNC_1 &pcfg_pull_none>;
2173 isp_dvp_d2d9: isp-d2d9 {
2175 /* cif_data2 ... cif_data9 */
2176 <2 0 RK_FUNC_1 &pcfg_pull_none>,
2177 <2 1 RK_FUNC_1 &pcfg_pull_none>,
2178 <2 2 RK_FUNC_1 &pcfg_pull_none>,
2179 <2 3 RK_FUNC_1 &pcfg_pull_none>,
2180 <2 4 RK_FUNC_1 &pcfg_pull_none>,
2181 <2 5 RK_FUNC_1 &pcfg_pull_none>,
2182 <2 6 RK_FUNC_1 &pcfg_pull_none>,
2183 <2 7 RK_FUNC_1 &pcfg_pull_none>,
2184 /* cif_sync, cif_href */
2185 <2 8 RK_FUNC_1 &pcfg_pull_none>,
2186 <2 9 RK_FUNC_1 &pcfg_pull_none>,
2187 /* cif_clkin, cif_clkout */
2188 <2 10 RK_FUNC_1 &pcfg_pull_none>,
2189 <2 11 RK_FUNC_1 &pcfg_pull_none>;
2192 isp_dvp_d0d1: isp-d0d1 {
2194 /* cif_data0, cif_data1 */
2195 <2 12 RK_FUNC_1 &pcfg_pull_none>,
2196 <2 13 RK_FUNC_1 &pcfg_pull_none>;
2199 isp_dvp_d10d11: isp-d10d11 {
2201 /* cif_data10, cif_data11 */
2202 <2 14 RK_FUNC_1 &pcfg_pull_none>,
2203 <2 15 RK_FUNC_1 &pcfg_pull_none>;
2206 isp_dvp_d0d7: isp-d0d7 {
2208 /* cif_data0 ... cif_data7 */
2209 <2 12 RK_FUNC_1 &pcfg_pull_none>,
2210 <2 13 RK_FUNC_1 &pcfg_pull_none>,
2211 <2 0 RK_FUNC_1 &pcfg_pull_none>,
2212 <2 1 RK_FUNC_1 &pcfg_pull_none>,
2213 <2 2 RK_FUNC_1 &pcfg_pull_none>,
2214 <2 3 RK_FUNC_1 &pcfg_pull_none>,
2215 <2 4 RK_FUNC_1 &pcfg_pull_none>,
2216 <2 5 RK_FUNC_1 &pcfg_pull_none>;
2219 isp_shutter: isp-shutter {
2221 /* SHUTTEREN, SHUTTERTRIG */
2222 <7 12 RK_FUNC_2 &pcfg_pull_none>,
2223 <7 15 RK_FUNC_2 &pcfg_pull_none>;
2226 isp_flash_trigger: isp-flash-trigger {
2228 /* ISP_FLASHTRIGOU */
2229 <7 13 RK_FUNC_2 &pcfg_pull_none>;
2232 isp_prelight: isp-prelight {
2234 /* ISP_PRELIGHTTRIG */
2235 <7 14 RK_FUNC_2 &pcfg_pull_none>;
2238 isp_flash_trigger_as_gpio: isp-flash-trigger-as-gpio {
2240 /* ISP_FLASHTRIGOU */
2241 <7 13 RK_FUNC_2 &pcfg_pull_none>;
2246 rockchip_suspend: rockchip-suspend {
2247 compatible = "rockchip,pm-rk3288";
2248 status = "disabled";
2249 rockchip,sleep-mode-config = <
2254 |RKPM_CTR_ARMOFF_LPMD
2257 rockchip,wakeup-config = <
2262 rockchip,pwm-regulator-config = <