2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3288-cru.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/power/rk3288-power.h>
48 #include "skeleton.dtsi"
51 compatible = "rockchip,rk3288";
53 interrupt-parent = <&gic>;
77 compatible = "arm,cortex-a12-pmu";
78 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
82 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
88 enable-method = "rockchip,rk3066-smp";
89 rockchip,pmu = <&pmu>;
93 compatible = "arm,cortex-a12";
95 resets = <&cru SRST_CORE0>;
111 #cooling-cells = <2>; /* min followed by max */
112 clock-latency = <40000>;
113 clocks = <&cru ARMCLK>;
117 compatible = "arm,cortex-a12";
119 resets = <&cru SRST_CORE1>;
123 compatible = "arm,cortex-a12";
125 resets = <&cru SRST_CORE2>;
129 compatible = "arm,cortex-a12";
131 resets = <&cru SRST_CORE3>;
136 compatible = "arm,amba-bus";
137 #address-cells = <1>;
141 dmac_peri: dma-controller@ff250000 {
142 compatible = "arm,pl330", "arm,primecell";
143 reg = <0xff250000 0x4000>;
144 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&cru ACLK_DMAC2>;
148 clock-names = "apb_pclk";
151 dmac_bus_ns: dma-controller@ff600000 {
152 compatible = "arm,pl330", "arm,primecell";
153 reg = <0xff600000 0x4000>;
154 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
157 clocks = <&cru ACLK_DMAC1>;
158 clock-names = "apb_pclk";
162 dmac_bus_s: dma-controller@ffb20000 {
163 compatible = "arm,pl330", "arm,primecell";
164 reg = <0xffb20000 0x4000>;
165 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
168 clocks = <&cru ACLK_DMAC1>;
169 clock-names = "apb_pclk";
174 #address-cells = <1>;
179 * The rk3288 cannot use the memory area above 0xfe000000
180 * for dma operations for some reason. While there is
181 * probably a better solution available somewhere, we
182 * haven't found it yet and while devices with 2GB of ram
183 * are not affected, this issue prevents 4GB from booting.
184 * So to make these devices at least bootable, block
185 * this area for the time being until the real solution
188 dma-unusable@fe000000 {
189 reg = <0xfe000000 0x1000000>;
194 compatible = "fixed-clock";
195 clock-frequency = <24000000>;
196 clock-output-names = "xin24m";
201 compatible = "arm,armv7-timer";
202 arm,cpu-registers-not-fw-configured;
203 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
204 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
205 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
206 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
207 clock-frequency = <24000000>;
210 timer: timer@ff810000 {
211 compatible = "rockchip,rk3288-timer";
212 reg = <0xff810000 0x20>;
213 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&xin24m>, <&cru PCLK_TIMER>;
215 clock-names = "timer", "pclk";
219 compatible = "rockchip,display-subsystem";
220 ports = <&vopl_out>, <&vopb_out>;
223 sdmmc: dwmmc@ff0c0000 {
224 compatible = "rockchip,rk3288-dw-mshc";
225 clock-freq-min-max = <400000 150000000>;
226 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
227 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
228 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
229 fifo-depth = <0x100>;
230 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
231 reg = <0xff0c0000 0x4000>;
235 sdio0: dwmmc@ff0d0000 {
236 compatible = "rockchip,rk3288-dw-mshc";
237 clock-freq-min-max = <400000 150000000>;
238 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
239 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
240 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
241 fifo-depth = <0x100>;
242 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
243 reg = <0xff0d0000 0x4000>;
247 sdio1: dwmmc@ff0e0000 {
248 compatible = "rockchip,rk3288-dw-mshc";
249 clock-freq-min-max = <400000 150000000>;
250 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
251 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
252 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
253 fifo-depth = <0x100>;
254 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
255 reg = <0xff0e0000 0x4000>;
259 emmc: dwmmc@ff0f0000 {
260 compatible = "rockchip,rk3288-dw-mshc";
261 clock-freq-min-max = <400000 150000000>;
262 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
263 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
264 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
265 fifo-depth = <0x100>;
266 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
267 reg = <0xff0f0000 0x4000>;
271 saradc: saradc@ff100000 {
272 compatible = "rockchip,saradc";
273 reg = <0xff100000 0x100>;
274 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
275 #io-channel-cells = <1>;
276 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
277 clock-names = "saradc", "apb_pclk";
282 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
283 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
284 clock-names = "spiclk", "apb_pclk";
285 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
286 dma-names = "tx", "rx";
287 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
288 pinctrl-names = "default";
289 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
290 reg = <0xff110000 0x1000>;
291 #address-cells = <1>;
297 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
298 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
299 clock-names = "spiclk", "apb_pclk";
300 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
301 dma-names = "tx", "rx";
302 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
303 pinctrl-names = "default";
304 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
305 reg = <0xff120000 0x1000>;
306 #address-cells = <1>;
312 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
313 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
314 clock-names = "spiclk", "apb_pclk";
315 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
316 dma-names = "tx", "rx";
317 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
318 pinctrl-names = "default";
319 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
320 reg = <0xff130000 0x1000>;
321 #address-cells = <1>;
327 compatible = "rockchip,rk3288-i2c";
328 reg = <0xff140000 0x1000>;
329 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
330 #address-cells = <1>;
333 clocks = <&cru PCLK_I2C1>;
334 pinctrl-names = "default";
335 pinctrl-0 = <&i2c1_xfer>;
340 compatible = "rockchip,rk3288-i2c";
341 reg = <0xff150000 0x1000>;
342 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
343 #address-cells = <1>;
346 clocks = <&cru PCLK_I2C3>;
347 pinctrl-names = "default";
348 pinctrl-0 = <&i2c3_xfer>;
353 compatible = "rockchip,rk3288-i2c";
354 reg = <0xff160000 0x1000>;
355 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
356 #address-cells = <1>;
359 clocks = <&cru PCLK_I2C4>;
360 pinctrl-names = "default";
361 pinctrl-0 = <&i2c4_xfer>;
366 compatible = "rockchip,rk3288-i2c";
367 reg = <0xff170000 0x1000>;
368 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
369 #address-cells = <1>;
372 clocks = <&cru PCLK_I2C5>;
373 pinctrl-names = "default";
374 pinctrl-0 = <&i2c5_xfer>;
378 uart0: serial@ff180000 {
379 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
380 reg = <0xff180000 0x100>;
381 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
385 clock-names = "baudclk", "apb_pclk";
386 pinctrl-names = "default";
387 pinctrl-0 = <&uart0_xfer>;
391 uart1: serial@ff190000 {
392 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
393 reg = <0xff190000 0x100>;
394 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
398 clock-names = "baudclk", "apb_pclk";
399 pinctrl-names = "default";
400 pinctrl-0 = <&uart1_xfer>;
404 uart2: serial@ff690000 {
405 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
406 reg = <0xff690000 0x100>;
407 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
411 clock-names = "baudclk", "apb_pclk";
412 pinctrl-names = "default";
413 pinctrl-0 = <&uart2_xfer>;
417 uart3: serial@ff1b0000 {
418 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
419 reg = <0xff1b0000 0x100>;
420 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
423 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
424 clock-names = "baudclk", "apb_pclk";
425 pinctrl-names = "default";
426 pinctrl-0 = <&uart3_xfer>;
430 uart4: serial@ff1c0000 {
431 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
432 reg = <0xff1c0000 0x100>;
433 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
436 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
437 clock-names = "baudclk", "apb_pclk";
438 pinctrl-names = "default";
439 pinctrl-0 = <&uart4_xfer>;
444 #include "rk3288-thermal.dtsi"
447 tsadc: tsadc@ff280000 {
448 compatible = "rockchip,rk3288-tsadc";
449 reg = <0xff280000 0x100>;
450 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
452 clock-names = "tsadc", "apb_pclk";
453 resets = <&cru SRST_TSADC>;
454 reset-names = "tsadc-apb";
455 pinctrl-names = "init", "default", "sleep";
456 pinctrl-0 = <&otp_gpio>;
457 pinctrl-1 = <&otp_out>;
458 pinctrl-2 = <&otp_gpio>;
459 #thermal-sensor-cells = <1>;
460 rockchip,hw-tshut-temp = <95000>;
464 gmac: ethernet@ff290000 {
465 compatible = "rockchip,rk3288-gmac";
466 reg = <0xff290000 0x10000>;
467 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
468 interrupt-names = "macirq";
469 rockchip,grf = <&grf>;
470 clocks = <&cru SCLK_MAC>,
471 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
472 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
473 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
474 clock-names = "stmmaceth",
475 "mac_clk_rx", "mac_clk_tx",
476 "clk_mac_ref", "clk_mac_refout",
477 "aclk_mac", "pclk_mac";
478 resets = <&cru SRST_MAC>;
479 reset-names = "stmmaceth";
483 usb_host0_ehci: usb@ff500000 {
484 compatible = "generic-ehci";
485 reg = <0xff500000 0x100>;
486 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&cru HCLK_USBHOST0>;
488 clock-names = "usbhost";
494 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
496 usb_host1: usb@ff540000 {
497 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
499 reg = <0xff540000 0x40000>;
500 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&cru HCLK_USBHOST1>;
505 phy-names = "usb2-phy";
509 usb_otg: usb@ff580000 {
510 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
512 reg = <0xff580000 0x40000>;
513 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
514 clocks = <&cru HCLK_OTG0>;
517 g-np-tx-fifo-size = <16>;
518 g-rx-fifo-size = <275>;
519 g-tx-fifo-size = <256 128 128 64 64 32>;
522 phy-names = "usb2-phy";
526 usb_hsic: usb@ff5c0000 {
527 compatible = "generic-ehci";
528 reg = <0xff5c0000 0x100>;
529 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
530 clocks = <&cru HCLK_HSIC>;
531 clock-names = "usbhost";
536 compatible = "rockchip,rk3288-i2c";
537 reg = <0xff650000 0x1000>;
538 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
539 #address-cells = <1>;
542 clocks = <&cru PCLK_I2C0>;
543 pinctrl-names = "default";
544 pinctrl-0 = <&i2c0_xfer>;
549 compatible = "rockchip,rk3288-i2c";
550 reg = <0xff660000 0x1000>;
551 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
552 #address-cells = <1>;
555 clocks = <&cru PCLK_I2C2>;
556 pinctrl-names = "default";
557 pinctrl-0 = <&i2c2_xfer>;
562 compatible = "rockchip,rk3288-pwm";
563 reg = <0xff680000 0x10>;
565 pinctrl-names = "default";
566 pinctrl-0 = <&pwm0_pin>;
567 clocks = <&cru PCLK_PWM>;
573 compatible = "rockchip,rk3288-pwm";
574 reg = <0xff680010 0x10>;
576 pinctrl-names = "default";
577 pinctrl-0 = <&pwm1_pin>;
578 clocks = <&cru PCLK_PWM>;
584 compatible = "rockchip,rk3288-pwm";
585 reg = <0xff680020 0x10>;
587 pinctrl-names = "default";
588 pinctrl-0 = <&pwm2_pin>;
589 clocks = <&cru PCLK_PWM>;
595 compatible = "rockchip,rk3288-pwm";
596 reg = <0xff680030 0x10>;
598 pinctrl-names = "default";
599 pinctrl-0 = <&pwm3_pin>;
600 clocks = <&cru PCLK_PWM>;
605 bus_intmem@ff700000 {
606 compatible = "mmio-sram";
607 reg = <0xff700000 0x18000>;
608 #address-cells = <1>;
610 ranges = <0 0xff700000 0x18000>;
612 compatible = "rockchip,rk3066-smp-sram";
618 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
619 reg = <0xff720000 0x1000>;
622 pmu: power-management@ff730000 {
623 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
624 reg = <0xff730000 0x100>;
626 power: power-controller {
627 compatible = "rockchip,rk3288-power-controller";
628 #power-domain-cells = <1>;
629 #address-cells = <1>;
633 * Note: Although SCLK_* are the working clocks
634 * of device without including on the NOC, needed for
637 * The clocks on the which NOC:
638 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
639 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
640 * ACLK_RGA is on ACLK_RGA_NIU.
641 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
643 * Which clock are device clocks:
645 * *_IEP IEP:Image Enhancement Processor
646 * *_ISP ISP:Image Signal Processing
647 * *_VIP VIP:Video Input Processor
648 * *_VOP* VOP:Visual Output Processor
656 reg = <RK3288_PD_VIO>;
657 clocks = <&cru ACLK_IEP>,
671 <&cru PCLK_EDP_CTRL>,
672 <&cru PCLK_HDMI_CTRL>,
673 <&cru PCLK_LVDS_PHY>,
674 <&cru PCLK_MIPI_CSI>,
675 <&cru PCLK_MIPI_DSI0>,
676 <&cru PCLK_MIPI_DSI1>,
685 * Note: The following 3 are HEVC(H.265) clocks,
686 * and on the ACLK_HEVC_NIU (NOC).
689 reg = <RK3288_PD_HEVC>;
690 clocks = <&cru ACLK_HEVC>,
691 <&cru SCLK_HEVC_CABAC>,
692 <&cru SCLK_HEVC_CORE>;
696 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
697 * (video endecoder & decoder) clocks that on the
698 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
701 reg = <RK3288_PD_VIDEO>;
702 clocks = <&cru ACLK_VCODEC>,
707 * Note: ACLK_GPU is the GPU clock,
708 * and on the ACLK_GPU_NIU (NOC).
711 reg = <RK3288_PD_GPU>;
712 clocks = <&cru ACLK_GPU>;
717 sgrf: syscon@ff740000 {
718 compatible = "rockchip,rk3288-sgrf", "syscon";
719 reg = <0xff740000 0x1000>;
722 cru: clock-controller@ff760000 {
723 compatible = "rockchip,rk3288-cru";
724 reg = <0xff760000 0x1000>;
725 rockchip,grf = <&grf>;
728 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
729 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
730 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
731 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
733 assigned-clock-rates = <594000000>, <400000000>,
734 <500000000>, <300000000>,
735 <150000000>, <75000000>,
736 <300000000>, <150000000>,
740 grf: syscon@ff770000 {
741 compatible = "rockchip,rk3288-grf", "syscon";
742 reg = <0xff770000 0x1000>;
745 wdt: watchdog@ff800000 {
746 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
747 reg = <0xff800000 0x100>;
748 clocks = <&cru PCLK_WDT>;
749 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
753 spdif: sound@ff88b0000 {
754 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
755 reg = <0xff8b0000 0x10000>;
756 #sound-dai-cells = <0>;
757 clock-names = "hclk", "mclk";
758 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
759 dmas = <&dmac_bus_s 3>;
761 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
762 pinctrl-names = "default";
763 pinctrl-0 = <&spdif_tx>;
764 rockchip,grf = <&grf>;
769 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
770 reg = <0xff890000 0x10000>;
771 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
772 #address-cells = <1>;
774 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
775 dma-names = "tx", "rx";
776 clock-names = "i2s_hclk", "i2s_clk";
777 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
778 pinctrl-names = "default";
779 pinctrl-0 = <&i2s0_bus>;
784 compatible = "rockchip,rk3288-vop";
785 reg = <0xff930000 0x19c>;
786 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
787 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
788 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
789 power-domains = <&power RK3288_PD_VIO>;
790 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
791 reset-names = "axi", "ahb", "dclk";
792 iommus = <&vopb_mmu>;
796 #address-cells = <1>;
799 vopb_out_hdmi: endpoint@0 {
801 remote-endpoint = <&hdmi_in_vopb>;
803 vopb_out_mipi: endpoint@2 {
805 remote-endpoint = <&mipi_in_vopb>;
810 vopb_mmu: iommu@ff930300 {
811 compatible = "rockchip,iommu";
812 reg = <0xff930300 0x100>;
813 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
814 interrupt-names = "vopb_mmu";
815 power-domains = <&power RK3288_PD_VIO>;
821 compatible = "rockchip,rk3288-vop";
822 reg = <0xff940000 0x19c>;
823 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
824 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
825 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
826 power-domains = <&power RK3288_PD_VIO>;
827 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
828 reset-names = "axi", "ahb", "dclk";
829 iommus = <&vopl_mmu>;
833 #address-cells = <1>;
836 vopl_out_hdmi: endpoint@0 {
838 remote-endpoint = <&hdmi_in_vopl>;
840 vopl_out_mipi: endpoint@2 {
842 remote-endpoint = <&mipi_in_vopl>;
847 vopl_mmu: iommu@ff940300 {
848 compatible = "rockchip,iommu";
849 reg = <0xff940300 0x100>;
850 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
851 interrupt-names = "vopl_mmu";
852 power-domains = <&power RK3288_PD_VIO>;
857 mipi_dsi: mipi@ff960000 {
858 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
859 reg = <0xff960000 0x4000>;
860 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
862 clock-names = "ref", "pclk";
863 rockchip,grf = <&grf>;
864 #address-cells = <1>;
869 #address-cells = <1>;
874 #address-cells = <1>;
876 mipi_in_vopb: endpoint@0 {
878 remote-endpoint = <&vopb_out_mipi>;
880 mipi_in_vopl: endpoint@1 {
882 remote-endpoint = <&vopl_out_mipi>;
888 hdmi: hdmi@ff980000 {
889 compatible = "rockchip,rk3288-dw-hdmi";
890 reg = <0xff980000 0x20000>;
892 rockchip,grf = <&grf>;
893 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
894 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
895 clock-names = "iahb", "isfr";
896 power-domains = <&power RK3288_PD_VIO>;
901 #address-cells = <1>;
903 hdmi_in_vopb: endpoint@0 {
905 remote-endpoint = <&vopb_out_hdmi>;
907 hdmi_in_vopl: endpoint@1 {
909 remote-endpoint = <&vopl_out_hdmi>;
915 gic: interrupt-controller@ffc01000 {
916 compatible = "arm,gic-400";
917 interrupt-controller;
918 #interrupt-cells = <3>;
919 #address-cells = <0>;
921 reg = <0xffc01000 0x1000>,
925 interrupts = <GIC_PPI 9 0xf04>;
929 compatible = "rockchip,rk3288-usb-phy";
930 rockchip,grf = <&grf>;
931 #address-cells = <1>;
938 clocks = <&cru SCLK_OTGPHY0>;
939 clock-names = "phyclk";
945 clocks = <&cru SCLK_OTGPHY1>;
946 clock-names = "phyclk";
952 clocks = <&cru SCLK_OTGPHY2>;
953 clock-names = "phyclk";
958 compatible = "rockchip,rk3288-pinctrl";
959 rockchip,grf = <&grf>;
960 rockchip,pmu = <&pmu>;
961 #address-cells = <1>;
965 gpio0: gpio0@ff750000 {
966 compatible = "rockchip,gpio-bank";
967 reg = <0xff750000 0x100>;
968 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
969 clocks = <&cru PCLK_GPIO0>;
974 interrupt-controller;
975 #interrupt-cells = <2>;
978 gpio1: gpio1@ff780000 {
979 compatible = "rockchip,gpio-bank";
980 reg = <0xff780000 0x100>;
981 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
982 clocks = <&cru PCLK_GPIO1>;
987 interrupt-controller;
988 #interrupt-cells = <2>;
991 gpio2: gpio2@ff790000 {
992 compatible = "rockchip,gpio-bank";
993 reg = <0xff790000 0x100>;
994 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
995 clocks = <&cru PCLK_GPIO2>;
1000 interrupt-controller;
1001 #interrupt-cells = <2>;
1004 gpio3: gpio3@ff7a0000 {
1005 compatible = "rockchip,gpio-bank";
1006 reg = <0xff7a0000 0x100>;
1007 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1008 clocks = <&cru PCLK_GPIO3>;
1013 interrupt-controller;
1014 #interrupt-cells = <2>;
1017 gpio4: gpio4@ff7b0000 {
1018 compatible = "rockchip,gpio-bank";
1019 reg = <0xff7b0000 0x100>;
1020 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1021 clocks = <&cru PCLK_GPIO4>;
1026 interrupt-controller;
1027 #interrupt-cells = <2>;
1030 gpio5: gpio5@ff7c0000 {
1031 compatible = "rockchip,gpio-bank";
1032 reg = <0xff7c0000 0x100>;
1033 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1034 clocks = <&cru PCLK_GPIO5>;
1039 interrupt-controller;
1040 #interrupt-cells = <2>;
1043 gpio6: gpio6@ff7d0000 {
1044 compatible = "rockchip,gpio-bank";
1045 reg = <0xff7d0000 0x100>;
1046 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1047 clocks = <&cru PCLK_GPIO6>;
1052 interrupt-controller;
1053 #interrupt-cells = <2>;
1056 gpio7: gpio7@ff7e0000 {
1057 compatible = "rockchip,gpio-bank";
1058 reg = <0xff7e0000 0x100>;
1059 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1060 clocks = <&cru PCLK_GPIO7>;
1065 interrupt-controller;
1066 #interrupt-cells = <2>;
1069 gpio8: gpio8@ff7f0000 {
1070 compatible = "rockchip,gpio-bank";
1071 reg = <0xff7f0000 0x100>;
1072 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1073 clocks = <&cru PCLK_GPIO8>;
1078 interrupt-controller;
1079 #interrupt-cells = <2>;
1083 hdmi_ddc: hdmi-ddc {
1084 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1085 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1089 pcfg_pull_up: pcfg-pull-up {
1093 pcfg_pull_down: pcfg-pull-down {
1097 pcfg_pull_none: pcfg-pull-none {
1101 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1103 drive-strength = <12>;
1107 global_pwroff: global-pwroff {
1108 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1111 ddrio_pwroff: ddrio-pwroff {
1112 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1115 ddr0_retention: ddr0-retention {
1116 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1119 ddr1_retention: ddr1-retention {
1120 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1125 i2c0_xfer: i2c0-xfer {
1126 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1127 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1132 i2c1_xfer: i2c1-xfer {
1133 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1134 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1139 i2c2_xfer: i2c2-xfer {
1140 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1141 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1146 i2c3_xfer: i2c3-xfer {
1147 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1148 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1153 i2c4_xfer: i2c4-xfer {
1154 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1155 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1160 i2c5_xfer: i2c5-xfer {
1161 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1162 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1167 i2s0_bus: i2s0-bus {
1168 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1169 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1170 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1171 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1172 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1173 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1178 sdmmc_clk: sdmmc-clk {
1179 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1182 sdmmc_cmd: sdmmc-cmd {
1183 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1186 sdmmc_cd: sdmcc-cd {
1187 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1190 sdmmc_bus1: sdmmc-bus1 {
1191 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1194 sdmmc_bus4: sdmmc-bus4 {
1195 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1196 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1197 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1198 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1203 sdio0_bus1: sdio0-bus1 {
1204 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1207 sdio0_bus4: sdio0-bus4 {
1208 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1209 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1210 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1211 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1214 sdio0_cmd: sdio0-cmd {
1215 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1218 sdio0_clk: sdio0-clk {
1219 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1222 sdio0_cd: sdio0-cd {
1223 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1226 sdio0_wp: sdio0-wp {
1227 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1230 sdio0_pwr: sdio0-pwr {
1231 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1234 sdio0_bkpwr: sdio0-bkpwr {
1235 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1238 sdio0_int: sdio0-int {
1239 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1244 sdio1_bus1: sdio1-bus1 {
1245 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1248 sdio1_bus4: sdio1-bus4 {
1249 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1250 <3 25 4 &pcfg_pull_up>,
1251 <3 26 4 &pcfg_pull_up>,
1252 <3 27 4 &pcfg_pull_up>;
1255 sdio1_cd: sdio1-cd {
1256 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1259 sdio1_wp: sdio1-wp {
1260 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1263 sdio1_bkpwr: sdio1-bkpwr {
1264 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1267 sdio1_int: sdio1-int {
1268 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1271 sdio1_cmd: sdio1-cmd {
1272 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1275 sdio1_clk: sdio1-clk {
1276 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1279 sdio1_pwr: sdio1-pwr {
1280 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1285 emmc_clk: emmc-clk {
1286 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1289 emmc_cmd: emmc-cmd {
1290 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1293 emmc_pwr: emmc-pwr {
1294 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1297 emmc_bus1: emmc-bus1 {
1298 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1301 emmc_bus4: emmc-bus4 {
1302 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1303 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1304 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1305 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1308 emmc_bus8: emmc-bus8 {
1309 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1310 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1311 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1312 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1313 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1314 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1315 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1316 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1321 spi0_clk: spi0-clk {
1322 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1324 spi0_cs0: spi0-cs0 {
1325 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1328 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1331 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1333 spi0_cs1: spi0-cs1 {
1334 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1338 spi1_clk: spi1-clk {
1339 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1341 spi1_cs0: spi1-cs0 {
1342 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1345 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1348 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1353 spi2_cs1: spi2-cs1 {
1354 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1356 spi2_clk: spi2-clk {
1357 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1359 spi2_cs0: spi2-cs0 {
1360 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1363 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1366 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1371 uart0_xfer: uart0-xfer {
1372 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1373 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1376 uart0_cts: uart0-cts {
1377 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1380 uart0_rts: uart0-rts {
1381 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1386 uart1_xfer: uart1-xfer {
1387 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1388 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1391 uart1_cts: uart1-cts {
1392 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1395 uart1_rts: uart1-rts {
1396 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1401 uart2_xfer: uart2-xfer {
1402 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1403 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1405 /* no rts / cts for uart2 */
1409 uart3_xfer: uart3-xfer {
1410 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1411 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1414 uart3_cts: uart3-cts {
1415 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1418 uart3_rts: uart3-rts {
1419 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1424 uart4_xfer: uart4-xfer {
1425 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1426 <5 13 3 &pcfg_pull_none>;
1429 uart4_cts: uart4-cts {
1430 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1433 uart4_rts: uart4-rts {
1434 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1439 otp_gpio: otp-gpio {
1440 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1444 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1449 pwm0_pin: pwm0-pin {
1450 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1455 pwm1_pin: pwm1-pin {
1456 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1461 pwm2_pin: pwm2-pin {
1462 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1467 pwm3_pin: pwm3-pin {
1468 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1473 rgmii_pins: rgmii-pins {
1474 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1475 <3 31 3 &pcfg_pull_none>,
1476 <3 26 3 &pcfg_pull_none>,
1477 <3 27 3 &pcfg_pull_none>,
1478 <3 28 3 &pcfg_pull_none_12ma>,
1479 <3 29 3 &pcfg_pull_none_12ma>,
1480 <3 24 3 &pcfg_pull_none_12ma>,
1481 <3 25 3 &pcfg_pull_none_12ma>,
1482 <4 0 3 &pcfg_pull_none>,
1483 <4 5 3 &pcfg_pull_none>,
1484 <4 6 3 &pcfg_pull_none>,
1485 <4 9 3 &pcfg_pull_none_12ma>,
1486 <4 4 3 &pcfg_pull_none_12ma>,
1487 <4 1 3 &pcfg_pull_none>,
1488 <4 3 3 &pcfg_pull_none>;
1491 rmii_pins: rmii-pins {
1492 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1493 <3 31 3 &pcfg_pull_none>,
1494 <3 28 3 &pcfg_pull_none>,
1495 <3 29 3 &pcfg_pull_none>,
1496 <4 0 3 &pcfg_pull_none>,
1497 <4 5 3 &pcfg_pull_none>,
1498 <4 4 3 &pcfg_pull_none>,
1499 <4 1 3 &pcfg_pull_none>,
1500 <4 2 3 &pcfg_pull_none>,
1501 <4 3 3 &pcfg_pull_none>;
1506 spdif_tx: spdif-tx {
1507 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;