arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include <dt-bindings/soc/rockchip_boot-mode.h>
  49 #include "skeleton.dtsi"
  50
  51 / {
  52         compatible = "rockchip,rk3288";
  53
  54         interrupt-parent = <&gic>;
  55
  56         aliases {
  57                 i2c0 = &i2c0;
  58                 i2c1 = &i2c1;
  59                 i2c2 = &i2c2;
  60                 i2c3 = &i2c3;
  61                 i2c4 = &i2c4;
  62                 i2c5 = &i2c5;
  63                 mshc0 = &emmc;
  64                 mshc1 = &sdmmc;
  65                 mshc2 = &sdio0;
  66                 mshc3 = &sdio1;
  67                 serial0 = &uart0;
  68                 serial1 = &uart1;
  69                 serial2 = &uart2;
  70                 serial3 = &uart3;
  71                 serial4 = &uart4;
  72                 spi0 = &spi0;
  73                 spi1 = &spi1;
  74                 spi2 = &spi2;
  75         };
  76
  77         arm-pmu {
  78                 compatible = "arm,cortex-a12-pmu";
  79                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  80                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  81                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  82                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  83                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  84         };
  85
  86         cpus {
  87                 #address-cells = <1>;
  88                 #size-cells = <0>;
  89                 enable-method = "rockchip,rk3066-smp";
  90                 rockchip,pmu = <&pmu>;
  91
  92                 cpu0: cpu@500 {
  93                         device_type = "cpu";
  94                         compatible = "arm,cortex-a12";
  95                         reg = <0x500>;
  96                         resets = <&cru SRST_CORE0>;
  97                         operating-points = <
  98                                 /* KHz    uV */
  99                                 1608000 1350000
 100                                 1512000 1300000
 101                                 1416000 1200000
 102                                 1200000 1100000
 103                                 1008000 1050000
 104                                  816000 1000000
 105                                  696000  950000
 106                                  600000  900000
 107                                  408000  900000
 108                                  312000  900000
 109                                  216000  900000
 110                                  126000  900000
 111                         >;
 112                         #cooling-cells = <2>; /* min followed by max */
 113                         clock-latency = <40000>;
 114                         clocks = <&cru ARMCLK>;
 115                 };
 116                 cpu1: cpu@501 {
 117                         device_type = "cpu";
 118                         compatible = "arm,cortex-a12";
 119                         reg = <0x501>;
 120                         resets = <&cru SRST_CORE1>;
 121                 };
 122                 cpu2: cpu@502 {
 123                         device_type = "cpu";
 124                         compatible = "arm,cortex-a12";
 125                         reg = <0x502>;
 126                         resets = <&cru SRST_CORE2>;
 127                 };
 128                 cpu3: cpu@503 {
 129                         device_type = "cpu";
 130                         compatible = "arm,cortex-a12";
 131                         reg = <0x503>;
 132                         resets = <&cru SRST_CORE3>;
 133                 };
 134         };
 135
 136         amba {
 137                 compatible = "arm,amba-bus";
 138                 #address-cells = <1>;
 139                 #size-cells = <1>;
 140                 ranges;
 141
 142                 dmac_peri: dma-controller@ff250000 {
 143                         compatible = "arm,pl330", "arm,primecell";
 144                         reg = <0xff250000 0x4000>;
 145                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 146                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 147                         #dma-cells = <1>;
 148                         arm,pl330-broken-no-flushp;
 149                         peripherals-req-type-burst;
 150                         clocks = <&cru ACLK_DMAC2>;
 151                         clock-names = "apb_pclk";
 152                 };
 153
 154                 dmac_bus_ns: dma-controller@ff600000 {
 155                         compatible = "arm,pl330", "arm,primecell";
 156                         reg = <0xff600000 0x4000>;
 157                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 158                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 159                         #dma-cells = <1>;
 160                         arm,pl330-broken-no-flushp;
 161                         peripherals-req-type-burst;
 162                         clocks = <&cru ACLK_DMAC1>;
 163                         clock-names = "apb_pclk";
 164                         status = "disabled";
 165                 };
 166
 167                 dmac_bus_s: dma-controller@ffb20000 {
 168                         compatible = "arm,pl330", "arm,primecell";
 169                         reg = <0xffb20000 0x4000>;
 170                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 171                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 172                         #dma-cells = <1>;
 173                         arm,pl330-broken-no-flushp;
 174                         peripherals-req-type-burst;
 175                         clocks = <&cru ACLK_DMAC1>;
 176                         clock-names = "apb_pclk";
 177                 };
 178         };
 179
 180         reserved-memory {
 181                 #address-cells = <1>;
 182                 #size-cells = <1>;
 183                 ranges;
 184
 185                 /*
 186                  * The rk3288 cannot use the memory area above 0xfe000000
 187                  * for dma operations for some reason. While there is
 188                  * probably a better solution available somewhere, we
 189                  * haven't found it yet and while devices with 2GB of ram
 190                  * are not affected, this issue prevents 4GB from booting.
 191                  * So to make these devices at least bootable, block
 192                  * this area for the time being until the real solution
 193                  * is found.
 194                  */
 195                 dma-unusable@fe000000 {
 196                         reg = <0xfe000000 0x1000000>;
 197                 };
 198         };
 199
 200         xin24m: oscillator {
 201                 compatible = "fixed-clock";
 202                 clock-frequency = <24000000>;
 203                 clock-output-names = "xin24m";
 204                 #clock-cells = <0>;
 205         };
 206
 207         edp_phy: edp-phy {
 208                 compatible = "rockchip,rk3288-dp-phy";
 209                 clocks = <&cru SCLK_EDP_24M>;
 210                 clock-names = "24m";
 211                 rockchip,grf = <&grf>;
 212                 #phy-cells = <0>;
 213                 status = "disabled";
 214         };
 215
 216         timer {
 217                 compatible = "arm,armv7-timer";
 218                 arm,cpu-registers-not-fw-configured;
 219                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 220                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 221                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 222                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 223                 clock-frequency = <24000000>;
 224         };
 225
 226         timer: timer@ff810000 {
 227                 compatible = "rockchip,rk3288-timer";
 228                 reg = <0xff810000 0x20>;
 229                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 230                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 231                 clock-names = "timer", "pclk";
 232         };
 233
 234         display-subsystem {
 235                 compatible = "rockchip,display-subsystem";
 236                 ports = <&vopl_out>, <&vopb_out>;
 237         };
 238
 239         sdmmc: dwmmc@ff0c0000 {
 240                 compatible = "rockchip,rk3288-dw-mshc";
 241                 clock-freq-min-max = <400000 150000000>;
 242                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 243                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 244                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 245                 fifo-depth = <0x100>;
 246                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 247                 reg = <0xff0c0000 0x4000>;
 248                 status = "disabled";
 249         };
 250
 251         sdio0: dwmmc@ff0d0000 {
 252                 compatible = "rockchip,rk3288-dw-mshc";
 253                 clock-freq-min-max = <400000 150000000>;
 254                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 255                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 256                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 257                 fifo-depth = <0x100>;
 258                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 259                 reg = <0xff0d0000 0x4000>;
 260                 status = "disabled";
 261         };
 262
 263         sdio1: dwmmc@ff0e0000 {
 264                 compatible = "rockchip,rk3288-dw-mshc";
 265                 clock-freq-min-max = <400000 150000000>;
 266                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 267                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 268                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 269                 fifo-depth = <0x100>;
 270                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 271                 reg = <0xff0e0000 0x4000>;
 272                 status = "disabled";
 273         };
 274
 275         emmc: dwmmc@ff0f0000 {
 276                 compatible = "rockchip,rk3288-dw-mshc";
 277                 clock-freq-min-max = <400000 150000000>;
 278                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 279                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 280                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 281                 fifo-depth = <0x100>;
 282                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 283                 reg = <0xff0f0000 0x4000>;
 284                 status = "disabled";
 285                 supports-emmc;
 286         };
 287
 288         saradc: saradc@ff100000 {
 289                 compatible = "rockchip,saradc";
 290                 reg = <0xff100000 0x100>;
 291                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 292                 #io-channel-cells = <1>;
 293                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 294                 clock-names = "saradc", "apb_pclk";
 295                 status = "disabled";
 296         };
 297
 298         spi0: spi@ff110000 {
 299                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 300                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 301                 clock-names = "spiclk", "apb_pclk";
 302                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 303                 dma-names = "tx", "rx";
 304                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 305                 pinctrl-names = "default";
 306                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 307                 reg = <0xff110000 0x1000>;
 308                 #address-cells = <1>;
 309                 #size-cells = <0>;
 310                 status = "disabled";
 311         };
 312
 313         spi1: spi@ff120000 {
 314                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 315                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 316                 clock-names = "spiclk", "apb_pclk";
 317                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 318                 dma-names = "tx", "rx";
 319                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 320                 pinctrl-names = "default";
 321                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 322                 reg = <0xff120000 0x1000>;
 323                 #address-cells = <1>;
 324                 #size-cells = <0>;
 325                 status = "disabled";
 326         };
 327
 328         spi2: spi@ff130000 {
 329                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 330                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 331                 clock-names = "spiclk", "apb_pclk";
 332                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 333                 dma-names = "tx", "rx";
 334                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 335                 pinctrl-names = "default";
 336                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 337                 reg = <0xff130000 0x1000>;
 338                 #address-cells = <1>;
 339                 #size-cells = <0>;
 340                 status = "disabled";
 341         };
 342
 343         i2c1: i2c@ff140000 {
 344                 compatible = "rockchip,rk3288-i2c";
 345                 reg = <0xff140000 0x1000>;
 346                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 347                 #address-cells = <1>;
 348                 #size-cells = <0>;
 349                 clock-names = "i2c";
 350                 clocks = <&cru PCLK_I2C1>;
 351                 pinctrl-names = "default";
 352                 pinctrl-0 = <&i2c1_xfer>;
 353                 status = "disabled";
 354         };
 355
 356         i2c3: i2c@ff150000 {
 357                 compatible = "rockchip,rk3288-i2c";
 358                 reg = <0xff150000 0x1000>;
 359                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 360                 #address-cells = <1>;
 361                 #size-cells = <0>;
 362                 clock-names = "i2c";
 363                 clocks = <&cru PCLK_I2C3>;
 364                 pinctrl-names = "default";
 365                 pinctrl-0 = <&i2c3_xfer>;
 366                 status = "disabled";
 367         };
 368
 369         i2c4: i2c@ff160000 {
 370                 compatible = "rockchip,rk3288-i2c";
 371                 reg = <0xff160000 0x1000>;
 372                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 373                 #address-cells = <1>;
 374                 #size-cells = <0>;
 375                 clock-names = "i2c";
 376                 clocks = <&cru PCLK_I2C4>;
 377                 pinctrl-names = "default";
 378                 pinctrl-0 = <&i2c4_xfer>;
 379                 status = "disabled";
 380         };
 381
 382         i2c5: i2c@ff170000 {
 383                 compatible = "rockchip,rk3288-i2c";
 384                 reg = <0xff170000 0x1000>;
 385                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 386                 #address-cells = <1>;
 387                 #size-cells = <0>;
 388                 clock-names = "i2c";
 389                 clocks = <&cru PCLK_I2C5>;
 390                 pinctrl-names = "default";
 391                 pinctrl-0 = <&i2c5_xfer>;
 392                 status = "disabled";
 393         };
 394
 395         uart0: serial@ff180000 {
 396                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 397                 reg = <0xff180000 0x100>;
 398                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 399                 reg-shift = <2>;
 400                 reg-io-width = <4>;
 401                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 402                 clock-names = "baudclk", "apb_pclk";
 403                 pinctrl-names = "default";
 404                 pinctrl-0 = <&uart0_xfer>;
 405                 status = "disabled";
 406         };
 407
 408         uart1: serial@ff190000 {
 409                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 410                 reg = <0xff190000 0x100>;
 411                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 412                 reg-shift = <2>;
 413                 reg-io-width = <4>;
 414                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 415                 clock-names = "baudclk", "apb_pclk";
 416                 pinctrl-names = "default";
 417                 pinctrl-0 = <&uart1_xfer>;
 418                 status = "disabled";
 419         };
 420
 421         uart2: serial@ff690000 {
 422                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 423                 reg = <0xff690000 0x100>;
 424                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 425                 reg-shift = <2>;
 426                 reg-io-width = <4>;
 427                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 428                 clock-names = "baudclk", "apb_pclk";
 429                 pinctrl-names = "default";
 430                 pinctrl-0 = <&uart2_xfer>;
 431                 status = "disabled";
 432         };
 433
 434         uart3: serial@ff1b0000 {
 435                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 436                 reg = <0xff1b0000 0x100>;
 437                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 438                 reg-shift = <2>;
 439                 reg-io-width = <4>;
 440                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 441                 clock-names = "baudclk", "apb_pclk";
 442                 pinctrl-names = "default";
 443                 pinctrl-0 = <&uart3_xfer>;
 444                 status = "disabled";
 445         };
 446
 447         uart4: serial@ff1c0000 {
 448                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 449                 reg = <0xff1c0000 0x100>;
 450                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 451                 reg-shift = <2>;
 452                 reg-io-width = <4>;
 453                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 454                 clock-names = "baudclk", "apb_pclk";
 455                 pinctrl-names = "default";
 456                 pinctrl-0 = <&uart4_xfer>;
 457                 status = "disabled";
 458         };
 459
 460         thermal-zones {
 461                 #include "rk3288-thermal.dtsi"
 462         };
 463
 464         tsadc: tsadc@ff280000 {
 465                 compatible = "rockchip,rk3288-tsadc";
 466                 reg = <0xff280000 0x100>;
 467                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 468                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 469                 clock-names = "tsadc", "apb_pclk";
 470                 resets = <&cru SRST_TSADC>;
 471                 reset-names = "tsadc-apb";
 472                 pinctrl-names = "init", "default", "sleep";
 473                 pinctrl-0 = <&otp_gpio>;
 474                 pinctrl-1 = <&otp_out>;
 475                 pinctrl-2 = <&otp_gpio>;
 476                 #thermal-sensor-cells = <1>;
 477                 rockchip,hw-tshut-temp = <95000>;
 478                 status = "disabled";
 479         };
 480
 481         gmac: ethernet@ff290000 {
 482                 compatible = "rockchip,rk3288-gmac";
 483                 reg = <0xff290000 0x10000>;
 484                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 485                 interrupt-names = "macirq";
 486                 rockchip,grf = <&grf>;
 487                 clocks = <&cru SCLK_MAC>,
 488                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 489                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 490                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 491                 clock-names = "stmmaceth",
 492                         "mac_clk_rx", "mac_clk_tx",
 493                         "clk_mac_ref", "clk_mac_refout",
 494                         "aclk_mac", "pclk_mac";
 495                 resets = <&cru SRST_MAC>;
 496                 reset-names = "stmmaceth";
 497                 status = "disabled";
 498         };
 499
 500         usb_host0_ehci: usb@ff500000 {
 501                 compatible = "generic-ehci";
 502                 reg = <0xff500000 0x100>;
 503                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 504                 clocks = <&cru HCLK_USBHOST0>;
 505                 clock-names = "usbhost";
 506                 phys = <&usbphy1>;
 507                 phy-names = "usb";
 508                 status = "disabled";
 509         };
 510
 511         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 512
 513         usb_host1: usb@ff540000 {
 514                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 515                                 "snps,dwc2";
 516                 reg = <0xff540000 0x40000>;
 517                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 518                 clocks = <&cru HCLK_USBHOST1>;
 519                 clock-names = "otg";
 520                 dr_mode = "host";
 521                 phys = <&usbphy2>;
 522                 phy-names = "usb2-phy";
 523                 status = "disabled";
 524         };
 525
 526         usb_otg: usb@ff580000 {
 527                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 528                                 "snps,dwc2";
 529                 reg = <0xff580000 0x40000>;
 530                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 531                 clocks = <&cru HCLK_OTG0>;
 532                 clock-names = "otg";
 533                 dr_mode = "otg";
 534                 g-np-tx-fifo-size = <16>;
 535                 g-rx-fifo-size = <275>;
 536                 g-tx-fifo-size = <256 128 128 64 64 32>;
 537                 g-use-dma;
 538                 phys = <&usbphy0>;
 539                 phy-names = "usb2-phy";
 540                 status = "disabled";
 541         };
 542
 543         usb_hsic: usb@ff5c0000 {
 544                 compatible = "generic-ehci";
 545                 reg = <0xff5c0000 0x100>;
 546                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 547                 clocks = <&cru HCLK_HSIC>;
 548                 clock-names = "usbhost";
 549                 status = "disabled";
 550         };
 551
 552         i2c0: i2c@ff650000 {
 553                 compatible = "rockchip,rk3288-i2c";
 554                 reg = <0xff650000 0x1000>;
 555                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 556                 #address-cells = <1>;
 557                 #size-cells = <0>;
 558                 clock-names = "i2c";
 559                 clocks = <&cru PCLK_I2C0>;
 560                 pinctrl-names = "default";
 561                 pinctrl-0 = <&i2c0_xfer>;
 562                 status = "disabled";
 563         };
 564
 565         i2c2: i2c@ff660000 {
 566                 compatible = "rockchip,rk3288-i2c";
 567                 reg = <0xff660000 0x1000>;
 568                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 569                 #address-cells = <1>;
 570                 #size-cells = <0>;
 571                 clock-names = "i2c";
 572                 clocks = <&cru PCLK_I2C2>;
 573                 pinctrl-names = "default";
 574                 pinctrl-0 = <&i2c2_xfer>;
 575                 status = "disabled";
 576         };
 577
 578         pwm0: pwm@ff680000 {
 579                 compatible = "rockchip,rk3288-pwm";
 580                 reg = <0xff680000 0x10>;
 581                 #pwm-cells = <3>;
 582                 pinctrl-names = "default";
 583                 pinctrl-0 = <&pwm0_pin>;
 584                 clocks = <&cru PCLK_PWM>;
 585                 clock-names = "pwm";
 586                 status = "disabled";
 587         };
 588
 589         pwm1: pwm@ff680010 {
 590                 compatible = "rockchip,rk3288-pwm";
 591                 reg = <0xff680010 0x10>;
 592                 #pwm-cells = <3>;
 593                 pinctrl-names = "default";
 594                 pinctrl-0 = <&pwm1_pin>;
 595                 clocks = <&cru PCLK_PWM>;
 596                 clock-names = "pwm";
 597                 status = "disabled";
 598         };
 599
 600         pwm2: pwm@ff680020 {
 601                 compatible = "rockchip,rk3288-pwm";
 602                 reg = <0xff680020 0x10>;
 603                 #pwm-cells = <3>;
 604                 pinctrl-names = "default";
 605                 pinctrl-0 = <&pwm2_pin>;
 606                 clocks = <&cru PCLK_PWM>;
 607                 clock-names = "pwm";
 608                 status = "disabled";
 609         };
 610
 611         pwm3: pwm@ff680030 {
 612                 compatible = "rockchip,rk3288-pwm";
 613                 reg = <0xff680030 0x10>;
 614                 #pwm-cells = <2>;
 615                 pinctrl-names = "default";
 616                 pinctrl-0 = <&pwm3_pin>;
 617                 clocks = <&cru PCLK_PWM>;
 618                 clock-names = "pwm";
 619                 status = "disabled";
 620         };
 621
 622         bus_intmem@ff700000 {
 623                 compatible = "mmio-sram";
 624                 reg = <0xff700000 0x18000>;
 625                 #address-cells = <1>;
 626                 #size-cells = <1>;
 627                 ranges = <0 0xff700000 0x18000>;
 628                 smp-sram@0 {
 629                         compatible = "rockchip,rk3066-smp-sram";
 630                         reg = <0x00 0x10>;
 631                 };
 632         };
 633
 634         sram@ff720000 {
 635                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 636                 reg = <0xff720000 0x1000>;
 637         };
 638
 639         pmu: power-management@ff730000 {
 640                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 641                 reg = <0xff730000 0x100>;
 642
 643                 power: power-controller {
 644                         compatible = "rockchip,rk3288-power-controller";
 645                         #power-domain-cells = <1>;
 646                         #address-cells = <1>;
 647                         #size-cells = <0>;
 648
 649                         /*
 650                          * Note: Although SCLK_* are the working clocks
 651                          * of device without including on the NOC, needed for
 652                          * synchronous reset.
 653                          *
 654                          * The clocks on the which NOC:
 655                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 656                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 657                          * ACLK_RGA is on ACLK_RGA_NIU.
 658                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 659                          *
 660                          * Which clock are device clocks:
 661                          *      clocks          devices
 662                          *      *_IEP           IEP:Image Enhancement Processor
 663                          *      *_ISP           ISP:Image Signal Processing
 664                          *      *_VIP           VIP:Video Input Processor
 665                          *      *_VOP*          VOP:Visual Output Processor
 666                          *      *_RGA           RGA
 667                          *      *_EDP*          EDP
 668                          *      *_LVDS_*        LVDS
 669                          *      *_HDMI          HDMI
 670                          *      *_MIPI_*        MIPI
 671                          */
 672                         pd_vio {
 673                                 reg = <RK3288_PD_VIO>;
 674                                 clocks = <&cru ACLK_IEP>,
 675                                          <&cru ACLK_ISP>,
 676                                          <&cru ACLK_RGA>,
 677                                          <&cru ACLK_VIP>,
 678                                          <&cru ACLK_VOP0>,
 679                                          <&cru ACLK_VOP1>,
 680                                          <&cru DCLK_VOP0>,
 681                                          <&cru DCLK_VOP1>,
 682                                          <&cru HCLK_IEP>,
 683                                          <&cru HCLK_ISP>,
 684                                          <&cru HCLK_RGA>,
 685                                          <&cru HCLK_VIP>,
 686                                          <&cru HCLK_VOP0>,
 687                                          <&cru HCLK_VOP1>,
 688                                          <&cru PCLK_EDP_CTRL>,
 689                                          <&cru PCLK_HDMI_CTRL>,
 690                                          <&cru PCLK_LVDS_PHY>,
 691                                          <&cru PCLK_MIPI_CSI>,
 692                                          <&cru PCLK_MIPI_DSI0>,
 693                                          <&cru PCLK_MIPI_DSI1>,
 694                                          <&cru SCLK_EDP_24M>,
 695                                          <&cru SCLK_EDP>,
 696                                          <&cru SCLK_ISP_JPE>,
 697                                          <&cru SCLK_ISP>,
 698                                          <&cru SCLK_RGA>;
 699                         };
 700
 701                         /*
 702                          * Note: The following 3 are HEVC(H.265) clocks,
 703                          * and on the ACLK_HEVC_NIU (NOC).
 704                          */
 705                         pd_hevc {
 706                                 reg = <RK3288_PD_HEVC>;
 707                                 clocks = <&cru ACLK_HEVC>,
 708                                          <&cru SCLK_HEVC_CABAC>,
 709                                          <&cru SCLK_HEVC_CORE>;
 710                         };
 711
 712                         /*
 713                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 714                          * (video endecoder & decoder) clocks that on the
 715                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 716                          */
 717                         pd_video {
 718                                 reg = <RK3288_PD_VIDEO>;
 719                                 clocks = <&cru ACLK_VCODEC>,
 720                                          <&cru HCLK_VCODEC>;
 721                         };
 722
 723                         /*
 724                          * Note: ACLK_GPU is the GPU clock,
 725                          * and on the ACLK_GPU_NIU (NOC).
 726                          */
 727                         pd_gpu {
 728                                 reg = <RK3288_PD_GPU>;
 729                                 clocks = <&cru ACLK_GPU>;
 730                         };
 731                 };
 732
 733                 reboot-mode {
 734                         compatible = "syscon-reboot-mode";
 735                         offset = <0x94>;
 736                         mode-normal = <BOOT_NORMAL>;
 737                         mode-recovery = <BOOT_RECOVERY>;
 738                         mode-bootloader = <BOOT_FASTBOOT>;
 739                         mode-loader = <BOOT_LOADER>;
 740                 };
 741         };
 742
 743         sgrf: syscon@ff740000 {
 744                 compatible = "rockchip,rk3288-sgrf", "syscon";
 745                 reg = <0xff740000 0x1000>;
 746         };
 747
 748         cru: clock-controller@ff760000 {
 749                 compatible = "rockchip,rk3288-cru";
 750                 reg = <0xff760000 0x1000>;
 751                 rockchip,grf = <&grf>;
 752                 #clock-cells = <1>;
 753                 #reset-cells = <1>;
 754                 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
 755                                   <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 756                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 757                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 758                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 759                                   <&cru PCLK_PERI>;
 760                 assigned-clock-rates = <0>, <0>,
 761                                        <594000000>, <400000000>,
 762                                        <500000000>, <300000000>,
 763                                        <150000000>, <75000000>,
 764                                        <300000000>, <150000000>,
 765                                        <75000000>;
 766                 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
 767         };
 768
 769         grf: syscon@ff770000 {
 770                 compatible = "rockchip,rk3288-grf", "syscon";
 771                 reg = <0xff770000 0x1000>;
 772         };
 773
 774         wdt: watchdog@ff800000 {
 775                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
 776                 reg = <0xff800000 0x100>;
 777                 clocks = <&cru PCLK_WDT>;
 778                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 779                 status = "disabled";
 780         };
 781
 782         spdif: sound@ff88b0000 {
 783                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
 784                 reg = <0xff8b0000 0x10000>;
 785                 #sound-dai-cells = <0>;
 786                 clock-names = "hclk", "mclk";
 787                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
 788                 dmas = <&dmac_bus_s 3>;
 789                 dma-names = "tx";
 790                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 791                 pinctrl-names = "default";
 792                 pinctrl-0 = <&spdif_tx>;
 793                 rockchip,grf = <&grf>;
 794                 status = "disabled";
 795         };
 796
 797         i2s: i2s@ff890000 {
 798                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
 799                 reg = <0xff890000 0x10000>;
 800                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 801                 #address-cells = <1>;
 802                 #size-cells = <0>;
 803                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
 804                 dma-names = "tx", "rx";
 805                 clock-names = "i2s_hclk", "i2s_clk";
 806                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
 807                 pinctrl-names = "default";
 808                 pinctrl-0 = <&i2s0_bus>;
 809                 status = "disabled";
 810         };
 811
 812         vopb: vop@ff930000 {
 813                 compatible = "rockchip,rk3288-vop";
 814                 reg = <0xff930000 0x19c>;
 815                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 816                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
 817                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 818                 power-domains = <&power RK3288_PD_VIO>;
 819                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
 820                 reset-names = "axi", "ahb", "dclk";
 821                 iommus = <&vopb_mmu>;
 822                 status = "disabled";
 823
 824                 vopb_out: port {
 825                         #address-cells = <1>;
 826                         #size-cells = <0>;
 827
 828                         vopb_out_hdmi: endpoint@0 {
 829                                 reg = <0>;
 830                                 remote-endpoint = <&hdmi_in_vopb>;
 831                         };
 832
 833                         vopb_out_edp: endpoint@1 {
 834                                 reg = <1>;
 835                                 remote-endpoint = <&edp_in_vopb>;
 836                         };
 837
 838                         vopb_out_mipi: endpoint@2 {
 839                                 reg = <2>;
 840                                 remote-endpoint = <&mipi_in_vopb>;
 841                         };
 842
 843                         vopb_out_lvds: endpoint@3 {
 844                                 reg = <3>;
 845                                 remote-endpoint = <&lvds_in_vopb>;
 846                         };
 847                 };
 848         };
 849
 850         vopb_mmu: iommu@ff930300 {
 851                 compatible = "rockchip,iommu";
 852                 reg = <0xff930300 0x100>;
 853                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 854                 interrupt-names = "vopb_mmu";
 855                 power-domains = <&power RK3288_PD_VIO>;
 856                 #iommu-cells = <0>;
 857                 status = "disabled";
 858         };
 859
 860         vopl: vop@ff940000 {
 861                 compatible = "rockchip,rk3288-vop";
 862                 reg = <0xff940000 0x19c>;
 863                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 864                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
 865                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
 866                 power-domains = <&power RK3288_PD_VIO>;
 867                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
 868                 reset-names = "axi", "ahb", "dclk";
 869                 iommus = <&vopl_mmu>;
 870                 status = "disabled";
 871
 872                 vopl_out: port {
 873                         #address-cells = <1>;
 874                         #size-cells = <0>;
 875
 876                         vopl_out_hdmi: endpoint@0 {
 877                                 reg = <0>;
 878                                 remote-endpoint = <&hdmi_in_vopl>;
 879                         };
 880
 881                         vopl_out_edp: endpoint@1 {
 882                                 reg = <1>;
 883                                 remote-endpoint = <&edp_in_vopl>;
 884                         };
 885
 886                         vopl_out_mipi: endpoint@2 {
 887                                 reg = <2>;
 888                                 remote-endpoint = <&mipi_in_vopl>;
 889                         };
 890
 891                         vopl_out_lvds: endpoint@3 {
 892                                 reg = <3>;
 893                                 remote-endpoint = <&lvds_in_vopl>;
 894                         };
 895
 896                 };
 897         };
 898
 899         vopl_mmu: iommu@ff940300 {
 900                 compatible = "rockchip,iommu";
 901                 reg = <0xff940300 0x100>;
 902                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 903                 interrupt-names = "vopl_mmu";
 904                 power-domains = <&power RK3288_PD_VIO>;
 905                 #iommu-cells = <0>;
 906                 status = "disabled";
 907         };
 908
 909         mipi_dsi: mipi@ff960000 {
 910                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
 911                 reg = <0xff960000 0x4000>;
 912                 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 913                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
 914                 clock-names = "ref", "pclk";
 915                 rockchip,grf = <&grf>;
 916                 #address-cells = <1>;
 917                 #size-cells = <0>;
 918                 status = "disabled";
 919
 920                 ports {
 921                         #address-cells = <1>;
 922                         #size-cells = <0>;
 923                         reg = <1>;
 924
 925                         mipi_in: port {
 926                                 #address-cells = <1>;
 927                                 #size-cells = <0>;
 928                                 mipi_in_vopb: endpoint@0 {
 929                                         reg = <0>;
 930                                         remote-endpoint = <&vopb_out_mipi>;
 931                                 };
 932                                 mipi_in_vopl: endpoint@1 {
 933                                         reg = <1>;
 934                                         remote-endpoint = <&vopl_out_mipi>;
 935                                 };
 936                         };
 937                 };
 938         };
 939
 940         edp: dp@ff970000 {
 941                 compatible = "rockchip,rk3288-dp";
 942                 reg = <0xff970000 0x4000>;
 943                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 944                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
 945                 clock-names = "dp", "pclk";
 946                 phys = <&edp_phy>;
 947                 phy-names = "dp";
 948                 resets = <&cru SRST_EDP>;
 949                 reset-names = "dp";
 950                 rockchip,grf = <&grf>;
 951                 status = "disabled";
 952
 953                 ports {
 954                         #address-cells = <1>;
 955                         #size-cells = <0>;
 956                         edp_in: port@0 {
 957                                 reg = <0>;
 958                                 #address-cells = <1>;
 959                                 #size-cells = <0>;
 960                                 edp_in_vopb: endpoint@0 {
 961                                         reg = <0>;
 962                                         remote-endpoint = <&vopb_out_edp>;
 963                                 };
 964                                 edp_in_vopl: endpoint@1 {
 965                                         reg = <1>;
 966                                         remote-endpoint = <&vopl_out_edp>;
 967                                 };
 968                         };
 969                 };
 970         };
 971
 972         lvds: lvds@ff96c000 {
 973                 compatible = "rockchip,rk3288-lvds";
 974                 reg = <0xff96c000 0x4000>;
 975                 clocks = <&cru PCLK_LVDS_PHY>;
 976                 clock-names = "pclk_lvds";
 977                 pinctrl-names = "default";
 978                 pinctrl-0 = <&lcdc0_ctl>;
 979                 power-domains = <&power RK3288_PD_VIO>;
 980                 rockchip,grf = <&grf>;
 981                 status = "disabled";
 982
 983                 ports {
 984                         #address-cells = <1>;
 985                         #size-cells = <0>;
 986
 987                         lvds_in: port@0 {
 988                                 reg = <0>;
 989
 990                                 #address-cells = <1>;
 991                                 #size-cells = <0>;
 992
 993                                 lvds_in_vopb: endpoint@0 {
 994                                         reg = <0>;
 995                                         remote-endpoint = <&vopb_out_lvds>;
 996                                 };
 997                                 lvds_in_vopl: endpoint@1 {
 998                                         reg = <1>;
 999                                         remote-endpoint = <&vopl_out_lvds>;
1000                                 };
1001                         };
1002                 };
1003         };
1004
1005         hdmi: hdmi@ff980000 {
1006                 compatible = "rockchip,rk3288-dw-hdmi";
1007                 reg = <0xff980000 0x20000>;
1008                 reg-io-width = <4>;
1009                 rockchip,grf = <&grf>;
1010                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1011                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1012                 clock-names = "iahb", "isfr";
1013                 power-domains = <&power RK3288_PD_VIO>;
1014                 status = "disabled";
1015
1016                 ports {
1017                         hdmi_in: port {
1018                                 #address-cells = <1>;
1019                                 #size-cells = <0>;
1020                                 hdmi_in_vopb: endpoint@0 {
1021                                         reg = <0>;
1022                                         remote-endpoint = <&vopb_out_hdmi>;
1023                                 };
1024                                 hdmi_in_vopl: endpoint@1 {
1025                                         reg = <1>;
1026                                         remote-endpoint = <&vopl_out_hdmi>;
1027                                 };
1028                         };
1029                 };
1030         };
1031
1032         gpu: gpu@ffa30000 {
1033                 compatible = "arm,malit764",
1034                              "arm,malit76x",
1035                              "arm,malit7xx",
1036                              "arm,mali-midgard";
1037                 reg = <0xffa30000 0x10000>;
1038                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1039                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1040                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1041                 interrupt-names = "JOB", "MMU", "GPU";
1042                 clocks = <&cru ACLK_GPU>;
1043                 clock-names = "clk_mali";
1044                 operating-points = <
1045                         /* KHz uV */
1046                         600000 1250000
1047                         /* 500000 1200000 - See crosbug.com/p/33857 */
1048                         400000 1100000
1049                         300000 1000000
1050                         200000 950000
1051                         100000 950000
1052                 >;
1053                 #cooling-cells = <2>; /* min followed by max */
1054                 power-domains = <&power RK3288_PD_GPU>;
1055                 status = "disabled";
1056         };
1057
1058         vpu: video-codec@ff9a0000 {
1059                 compatible = "rockchip,rk3288-vpu";
1060                 reg = <0xff9a0000 0x800>;
1061                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1062                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1063                 interrupt-names = "vepu", "vdpu";
1064                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1065                 clock-names = "aclk", "hclk";
1066                 power-domains = <&power RK3288_PD_VIDEO>;
1067                 iommus = <&vpu_mmu>;
1068                 assigned-clocks = <&cru ACLK_VCODEC>;
1069                 assigned-clock-rates = <400000000>;
1070                 status = "disabled";
1071         };
1072
1073         vpu_mmu: iommu@ff9a0800 {
1074                 compatible = "rockchip,iommu";
1075                 reg = <0xff9a0800 0x100>;
1076                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1077                 interrupt-names = "vpu_mmu";
1078                 power-domains = <&power RK3288_PD_VIDEO>;
1079                 #iommu-cells = <0>;
1080         };
1081
1082         gic: interrupt-controller@ffc01000 {
1083                 compatible = "arm,gic-400";
1084                 interrupt-controller;
1085                 #interrupt-cells = <3>;
1086                 #address-cells = <0>;
1087
1088                 reg = <0xffc01000 0x1000>,
1089                       <0xffc02000 0x1000>,
1090                       <0xffc04000 0x2000>,
1091                       <0xffc06000 0x2000>;
1092                 interrupts = <GIC_PPI 9 0xf04>;
1093         };
1094
1095         efuse: efuse@ffb40000 {
1096                 compatible = "rockchip,rockchip-efuse";
1097                 reg = <0xffb40000 0x20>;
1098                 #address-cells = <1>;
1099                 #size-cells = <1>;
1100                 clocks = <&cru PCLK_EFUSE256>;
1101                 clock-names = "pclk_efuse";
1102
1103                 cpu_leakage: cpu_leakage@17 {
1104                         reg = <0x17 0x1>;
1105                 };
1106         };
1107
1108         usbphy: phy {
1109                 compatible = "rockchip,rk3288-usb-phy";
1110                 rockchip,grf = <&grf>;
1111                 #address-cells = <1>;
1112                 #size-cells = <0>;
1113                 status = "disabled";
1114
1115                 usbphy0: usb-phy0 {
1116                         #phy-cells = <0>;
1117                         reg = <0x320>;
1118                         clocks = <&cru SCLK_OTGPHY0>;
1119                         clock-names = "phyclk";
1120                 };
1121
1122                 usbphy1: usb-phy1 {
1123                         #phy-cells = <0>;
1124                         reg = <0x334>;
1125                         clocks = <&cru SCLK_OTGPHY1>;
1126                         clock-names = "phyclk";
1127                 };
1128
1129                 usbphy2: usb-phy2 {
1130                         #phy-cells = <0>;
1131                         reg = <0x348>;
1132                         clocks = <&cru SCLK_OTGPHY2>;
1133                         clock-names = "phyclk";
1134                 };
1135         };
1136
1137         pinctrl: pinctrl {
1138                 compatible = "rockchip,rk3288-pinctrl";
1139                 rockchip,grf = <&grf>;
1140                 rockchip,pmu = <&pmu>;
1141                 #address-cells = <1>;
1142                 #size-cells = <1>;
1143                 ranges;
1144
1145                 gpio0: gpio0@ff750000 {
1146                         compatible = "rockchip,gpio-bank";
1147                         reg =   <0xff750000 0x100>;
1148                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1149                         clocks = <&cru PCLK_GPIO0>;
1150
1151                         gpio-controller;
1152                         #gpio-cells = <2>;
1153
1154                         interrupt-controller;
1155                         #interrupt-cells = <2>;
1156                 };
1157
1158                 gpio1: gpio1@ff780000 {
1159                         compatible = "rockchip,gpio-bank";
1160                         reg = <0xff780000 0x100>;
1161                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1162                         clocks = <&cru PCLK_GPIO1>;
1163
1164                         gpio-controller;
1165                         #gpio-cells = <2>;
1166
1167                         interrupt-controller;
1168                         #interrupt-cells = <2>;
1169                 };
1170
1171                 gpio2: gpio2@ff790000 {
1172                         compatible = "rockchip,gpio-bank";
1173                         reg = <0xff790000 0x100>;
1174                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1175                         clocks = <&cru PCLK_GPIO2>;
1176
1177                         gpio-controller;
1178                         #gpio-cells = <2>;
1179
1180                         interrupt-controller;
1181                         #interrupt-cells = <2>;
1182                 };
1183
1184                 gpio3: gpio3@ff7a0000 {
1185                         compatible = "rockchip,gpio-bank";
1186                         reg = <0xff7a0000 0x100>;
1187                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1188                         clocks = <&cru PCLK_GPIO3>;
1189
1190                         gpio-controller;
1191                         #gpio-cells = <2>;
1192
1193                         interrupt-controller;
1194                         #interrupt-cells = <2>;
1195                 };
1196
1197                 gpio4: gpio4@ff7b0000 {
1198                         compatible = "rockchip,gpio-bank";
1199                         reg = <0xff7b0000 0x100>;
1200                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1201                         clocks = <&cru PCLK_GPIO4>;
1202
1203                         gpio-controller;
1204                         #gpio-cells = <2>;
1205
1206                         interrupt-controller;
1207                         #interrupt-cells = <2>;
1208                 };
1209
1210                 gpio5: gpio5@ff7c0000 {
1211                         compatible = "rockchip,gpio-bank";
1212                         reg = <0xff7c0000 0x100>;
1213                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1214                         clocks = <&cru PCLK_GPIO5>;
1215
1216                         gpio-controller;
1217                         #gpio-cells = <2>;
1218
1219                         interrupt-controller;
1220                         #interrupt-cells = <2>;
1221                 };
1222
1223                 gpio6: gpio6@ff7d0000 {
1224                         compatible = "rockchip,gpio-bank";
1225                         reg = <0xff7d0000 0x100>;
1226                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1227                         clocks = <&cru PCLK_GPIO6>;
1228
1229                         gpio-controller;
1230                         #gpio-cells = <2>;
1231
1232                         interrupt-controller;
1233                         #interrupt-cells = <2>;
1234                 };
1235
1236                 gpio7: gpio7@ff7e0000 {
1237                         compatible = "rockchip,gpio-bank";
1238                         reg = <0xff7e0000 0x100>;
1239                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1240                         clocks = <&cru PCLK_GPIO7>;
1241
1242                         gpio-controller;
1243                         #gpio-cells = <2>;
1244
1245                         interrupt-controller;
1246                         #interrupt-cells = <2>;
1247                 };
1248
1249                 gpio8: gpio8@ff7f0000 {
1250                         compatible = "rockchip,gpio-bank";
1251                         reg = <0xff7f0000 0x100>;
1252                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1253                         clocks = <&cru PCLK_GPIO8>;
1254
1255                         gpio-controller;
1256                         #gpio-cells = <2>;
1257
1258                         interrupt-controller;
1259                         #interrupt-cells = <2>;
1260                 };
1261
1262                 hdmi {
1263                         hdmi_ddc: hdmi-ddc {
1264                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1265                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1266                         };
1267                 };
1268
1269                 pcfg_pull_up: pcfg-pull-up {
1270                         bias-pull-up;
1271                 };
1272
1273                 pcfg_pull_down: pcfg-pull-down {
1274                         bias-pull-down;
1275                 };
1276
1277                 pcfg_pull_none: pcfg-pull-none {
1278                         bias-disable;
1279                 };
1280
1281                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1282                         bias-disable;
1283                         drive-strength = <12>;
1284                 };
1285
1286                 sleep {
1287                         global_pwroff: global-pwroff {
1288                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1289                         };
1290
1291                         ddrio_pwroff: ddrio-pwroff {
1292                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1293                         };
1294
1295                         ddr0_retention: ddr0-retention {
1296                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1297                         };
1298
1299                         ddr1_retention: ddr1-retention {
1300                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1301                         };
1302                 };
1303
1304                 edp {
1305                         edp_hpd: edp-hpd {
1306                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1307                         };
1308                 };
1309
1310                 i2c0 {
1311                         i2c0_xfer: i2c0-xfer {
1312                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1313                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1314                         };
1315                 };
1316
1317                 i2c1 {
1318                         i2c1_xfer: i2c1-xfer {
1319                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1320                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1321                         };
1322                 };
1323
1324                 i2c2 {
1325                         i2c2_xfer: i2c2-xfer {
1326                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1327                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1328                         };
1329                 };
1330
1331                 i2c3 {
1332                         i2c3_xfer: i2c3-xfer {
1333                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1334                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1335                         };
1336                 };
1337
1338                 i2c4 {
1339                         i2c4_xfer: i2c4-xfer {
1340                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1341                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1342                         };
1343                 };
1344
1345                 i2c5 {
1346                         i2c5_xfer: i2c5-xfer {
1347                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1348                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1349                         };
1350                 };
1351
1352                 i2s0 {
1353                         i2s0_bus: i2s0-bus {
1354                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1355                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1356                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1357                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1358                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1359                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1360                         };
1361                 };
1362
1363                 lcdc0 {
1364                         lcdc0_ctl: lcdc0-ctl {
1365                                 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1366                                                 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1367                                                 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1368                                                 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1369                         };
1370                 };
1371
1372                 sdmmc {
1373                         sdmmc_clk: sdmmc-clk {
1374                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1375                         };
1376
1377                         sdmmc_cmd: sdmmc-cmd {
1378                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1379                         };
1380
1381                         sdmmc_cd: sdmcc-cd {
1382                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1383                         };
1384
1385                         sdmmc_bus1: sdmmc-bus1 {
1386                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1387                         };
1388
1389                         sdmmc_bus4: sdmmc-bus4 {
1390                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1391                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1392                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1393                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1394                         };
1395                 };
1396
1397                 sdio0 {
1398                         sdio0_bus1: sdio0-bus1 {
1399                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1400                         };
1401
1402                         sdio0_bus4: sdio0-bus4 {
1403                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1404                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1405                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1406                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1407                         };
1408
1409                         sdio0_cmd: sdio0-cmd {
1410                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1411                         };
1412
1413                         sdio0_clk: sdio0-clk {
1414                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1415                         };
1416
1417                         sdio0_cd: sdio0-cd {
1418                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1419                         };
1420
1421                         sdio0_wp: sdio0-wp {
1422                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1423                         };
1424
1425                         sdio0_pwr: sdio0-pwr {
1426                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1427                         };
1428
1429                         sdio0_bkpwr: sdio0-bkpwr {
1430                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1431                         };
1432
1433                         sdio0_int: sdio0-int {
1434                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1435                         };
1436                 };
1437
1438                 sdio1 {
1439                         sdio1_bus1: sdio1-bus1 {
1440                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1441                         };
1442
1443                         sdio1_bus4: sdio1-bus4 {
1444                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1445                                                 <3 25 4 &pcfg_pull_up>,
1446                                                 <3 26 4 &pcfg_pull_up>,
1447                                                 <3 27 4 &pcfg_pull_up>;
1448                         };
1449
1450                         sdio1_cd: sdio1-cd {
1451                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1452                         };
1453
1454                         sdio1_wp: sdio1-wp {
1455                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1456                         };
1457
1458                         sdio1_bkpwr: sdio1-bkpwr {
1459                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1460                         };
1461
1462                         sdio1_int: sdio1-int {
1463                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1464                         };
1465
1466                         sdio1_cmd: sdio1-cmd {
1467                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1468                         };
1469
1470                         sdio1_clk: sdio1-clk {
1471                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1472                         };
1473
1474                         sdio1_pwr: sdio1-pwr {
1475                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1476                         };
1477                 };
1478
1479                 emmc {
1480                         emmc_clk: emmc-clk {
1481                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1482                         };
1483
1484                         emmc_cmd: emmc-cmd {
1485                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1486                         };
1487
1488                         emmc_pwr: emmc-pwr {
1489                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1490                         };
1491
1492                         emmc_bus1: emmc-bus1 {
1493                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1494                         };
1495
1496                         emmc_bus4: emmc-bus4 {
1497                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1498                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1499                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1500                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1501                         };
1502
1503                         emmc_bus8: emmc-bus8 {
1504                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1505                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1506                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1507                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1508                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1509                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1510                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1511                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1512                         };
1513                 };
1514
1515                 spi0 {
1516                         spi0_clk: spi0-clk {
1517                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1518                         };
1519                         spi0_cs0: spi0-cs0 {
1520                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1521                         };
1522                         spi0_tx: spi0-tx {
1523                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1524                         };
1525                         spi0_rx: spi0-rx {
1526                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1527                         };
1528                         spi0_cs1: spi0-cs1 {
1529                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1530                         };
1531                 };
1532                 spi1 {
1533                         spi1_clk: spi1-clk {
1534                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1535                         };
1536                         spi1_cs0: spi1-cs0 {
1537                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1538                         };
1539                         spi1_rx: spi1-rx {
1540                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1541                         };
1542                         spi1_tx: spi1-tx {
1543                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1544                         };
1545                 };
1546
1547                 spi2 {
1548                         spi2_cs1: spi2-cs1 {
1549                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1550                         };
1551                         spi2_clk: spi2-clk {
1552                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1553                         };
1554                         spi2_cs0: spi2-cs0 {
1555                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1556                         };
1557                         spi2_rx: spi2-rx {
1558                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1559                         };
1560                         spi2_tx: spi2-tx {
1561                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1562                         };
1563                 };
1564
1565                 uart0 {
1566                         uart0_xfer: uart0-xfer {
1567                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1568                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1569                         };
1570
1571                         uart0_cts: uart0-cts {
1572                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1573                         };
1574
1575                         uart0_rts: uart0-rts {
1576                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1577                         };
1578                 };
1579
1580                 uart1 {
1581                         uart1_xfer: uart1-xfer {
1582                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1583                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1584                         };
1585
1586                         uart1_cts: uart1-cts {
1587                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1588                         };
1589
1590                         uart1_rts: uart1-rts {
1591                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1592                         };
1593                 };
1594
1595                 uart2 {
1596                         uart2_xfer: uart2-xfer {
1597                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1598                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1599                         };
1600                         /* no rts / cts for uart2 */
1601                 };
1602
1603                 uart3 {
1604                         uart3_xfer: uart3-xfer {
1605                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1606                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1607                         };
1608
1609                         uart3_cts: uart3-cts {
1610                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1611                         };
1612
1613                         uart3_rts: uart3-rts {
1614                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1615                         };
1616                 };
1617
1618                 uart4 {
1619                         uart4_xfer: uart4-xfer {
1620                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1621                                                 <5 13 3 &pcfg_pull_none>;
1622                         };
1623
1624                         uart4_cts: uart4-cts {
1625                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1626                         };
1627
1628                         uart4_rts: uart4-rts {
1629                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1630                         };
1631                 };
1632
1633                 tsadc {
1634                         otp_gpio: otp-gpio {
1635                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1636                         };
1637
1638                         otp_out: otp-out {
1639                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1640                         };
1641                 };
1642
1643                 pwm0 {
1644                         pwm0_pin: pwm0-pin {
1645                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1646                         };
1647                 };
1648
1649                 pwm1 {
1650                         pwm1_pin: pwm1-pin {
1651                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1652                         };
1653                 };
1654
1655                 pwm2 {
1656                         pwm2_pin: pwm2-pin {
1657                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1658                         };
1659                 };
1660
1661                 pwm3 {
1662                         pwm3_pin: pwm3-pin {
1663                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1664                         };
1665                 };
1666
1667                 gmac {
1668                         rgmii_pins: rgmii-pins {
1669                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1670                                                 <3 31 3 &pcfg_pull_none>,
1671                                                 <3 26 3 &pcfg_pull_none>,
1672                                                 <3 27 3 &pcfg_pull_none>,
1673                                                 <3 28 3 &pcfg_pull_none_12ma>,
1674                                                 <3 29 3 &pcfg_pull_none_12ma>,
1675                                                 <3 24 3 &pcfg_pull_none_12ma>,
1676                                                 <3 25 3 &pcfg_pull_none_12ma>,
1677                                                 <4 0 3 &pcfg_pull_none>,
1678                                                 <4 5 3 &pcfg_pull_none>,
1679                                                 <4 6 3 &pcfg_pull_none>,
1680                                                 <4 9 3 &pcfg_pull_none_12ma>,
1681                                                 <4 4 3 &pcfg_pull_none_12ma>,
1682                                                 <4 1 3 &pcfg_pull_none>,
1683                                                 <4 3 3 &pcfg_pull_none>;
1684                         };
1685
1686                         rmii_pins: rmii-pins {
1687                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1688                                                 <3 31 3 &pcfg_pull_none>,
1689                                                 <3 28 3 &pcfg_pull_none>,
1690                                                 <3 29 3 &pcfg_pull_none>,
1691                                                 <4 0 3 &pcfg_pull_none>,
1692                                                 <4 5 3 &pcfg_pull_none>,
1693                                                 <4 4 3 &pcfg_pull_none>,
1694                                                 <4 1 3 &pcfg_pull_none>,
1695                                                 <4 2 3 &pcfg_pull_none>,
1696                                                 <4 3 3 &pcfg_pull_none>;
1697                         };
1698                 };
1699
1700                 spdif {
1701                         spdif_tx: spdif-tx {
1702                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1703                         };
1704                 };
1705         };
1706 };