arch/arm/boot/dts/rk3288.dtsi

   1 /*
   2  * This file is dual-licensed: you can use it either under the terms
   3  * of the GPL or the X11 license, at your option. Note that this dual
   4  * licensing only applies to this file, and not this project as a
   5  * whole.
   6  *
   7  *  a) This file is free software; you can redistribute it and/or
   8  *     modify it under the terms of the GNU General Public License as
   9  *     published by the Free Software Foundation; either version 2 of the
  10  *     License, or (at your option) any later version.
  11  *
  12  *     This file is distributed in the hope that it will be useful,
  13  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *     GNU General Public License for more details.
  16  *
  17  * Or, alternatively,
  18  *
  19  *  b) Permission is hereby granted, free of charge, to any person
  20  *     obtaining a copy of this software and associated documentation
  21  *     files (the "Software"), to deal in the Software without
  22  *     restriction, including without limitation the rights to use,
  23  *     copy, modify, merge, publish, distribute, sublicense, and/or
  24  *     sell copies of the Software, and to permit persons to whom the
  25  *     Software is furnished to do so, subject to the following
  26  *     conditions:
  27  *
  28  *     The above copyright notice and this permission notice shall be
  29  *     included in all copies or substantial portions of the Software.
  30  *
  31  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  33  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  34  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  35  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  36  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  37  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  38  *     OTHER DEALINGS IN THE SOFTWARE.
  39  */
  40
  41 #include <dt-bindings/gpio/gpio.h>
  42 #include <dt-bindings/interrupt-controller/irq.h>
  43 #include <dt-bindings/interrupt-controller/arm-gic.h>
  44 #include <dt-bindings/pinctrl/rockchip.h>
  45 #include <dt-bindings/clock/rk3288-cru.h>
  46 #include <dt-bindings/thermal/thermal.h>
  47 #include <dt-bindings/power/rk3288-power.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49 #include <dt-bindings/suspend/rockchip-rk3288.h>
  50 #include <dt-bindings/display/drm_mipi_dsi.h>
  51 #include "skeleton.dtsi"
  52
  53 / {
  54         compatible = "rockchip,rk3288";
  55
  56         interrupt-parent = <&gic>;
  57
  58         aliases {
  59                 ethernet0 = &gmac;
  60                 i2c0 = &i2c0;
  61                 i2c1 = &i2c1;
  62                 i2c2 = &i2c2;
  63                 i2c3 = &i2c3;
  64                 i2c4 = &i2c4;
  65                 i2c5 = &i2c5;
  66                 mshc0 = &emmc;
  67                 mshc1 = &sdmmc;
  68                 mshc2 = &sdio0;
  69                 mshc3 = &sdio1;
  70                 serial0 = &uart0;
  71                 serial1 = &uart1;
  72                 serial2 = &uart2;
  73                 serial3 = &uart3;
  74                 serial4 = &uart4;
  75                 spi0 = &spi0;
  76                 spi1 = &spi1;
  77                 spi2 = &spi2;
  78         };
  79
  80         arm-pmu {
  81                 compatible = "arm,cortex-a12-pmu";
  82                 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
  83                              <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
  84                              <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
  85                              <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
  86                 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
  87         };
  88
  89         cpus {
  90                 #address-cells = <1>;
  91                 #size-cells = <0>;
  92                 enable-method = "rockchip,rk3066-smp";
  93                 rockchip,pmu = <&pmu>;
  94
  95                 cpu0: cpu@500 {
  96                         device_type = "cpu";
  97                         compatible = "arm,cortex-a12";
  98                         reg = <0x500>;
  99                         resets = <&cru SRST_CORE0>;
 100                         operating-points-v2 = <&cpu0_opp_table>;
 101                         #cooling-cells = <2>; /* min followed by max */
 102                         dynamic-power-coefficient = <322>;
 103                         clocks = <&cru ARMCLK>;
 104                 };
 105                 cpu1: cpu@501 {
 106                         device_type = "cpu";
 107                         compatible = "arm,cortex-a12";
 108                         reg = <0x501>;
 109                         resets = <&cru SRST_CORE1>;
 110                         operating-points-v2 = <&cpu0_opp_table>;
 111                 };
 112                 cpu2: cpu@502 {
 113                         device_type = "cpu";
 114                         compatible = "arm,cortex-a12";
 115                         reg = <0x502>;
 116                         resets = <&cru SRST_CORE2>;
 117                         operating-points-v2 = <&cpu0_opp_table>;
 118                 };
 119                 cpu3: cpu@503 {
 120                         device_type = "cpu";
 121                         compatible = "arm,cortex-a12";
 122                         reg = <0x503>;
 123                         resets = <&cru SRST_CORE3>;
 124                         operating-points-v2 = <&cpu0_opp_table>;
 125                 };
 126         };
 127
 128         cpu0_opp_table: opp_table0 {
 129                 compatible = "operating-points-v2";
 130                 opp-shared;
 131
 132                 opp-126000000 {
 133                         opp-hz = /bits/ 64 <126000000>;
 134                         opp-microvolt = <900000>;
 135                         clock-latency-ns = <40000>;
 136                 };
 137                 opp-216000000 {
 138                         opp-hz = /bits/ 64 <216000000>;
 139                         opp-microvolt = <900000>;
 140                         clock-latency-ns = <40000>;
 141                 };
 142                 opp-408000000 {
 143                         opp-hz = /bits/ 64 <408000000>;
 144                         opp-microvolt = <900000>;
 145                         clock-latency-ns = <40000>;
 146                 };
 147                 opp-600000000 {
 148                         opp-hz = /bits/ 64 <600000000>;
 149                         opp-microvolt = <900000>;
 150                         clock-latency-ns = <40000>;
 151                 };
 152                 opp-696000000 {
 153                         opp-hz = /bits/ 64 <696000000>;
 154                         opp-microvolt = <950000>;
 155                         clock-latency-ns = <40000>;
 156                 };
 157                 opp-816000000 {
 158                         opp-hz = /bits/ 64 <816000000>;
 159                         opp-microvolt = <1000000>;
 160                         clock-latency-ns = <40000>;
 161                         opp-suspend;
 162                 };
 163                 opp-1008000000 {
 164                         opp-hz = /bits/ 64 <1008000000>;
 165                         opp-microvolt = <1050000>;
 166                         clock-latency-ns = <40000>;
 167                 };
 168                 opp-1200000000 {
 169                         opp-hz = /bits/ 64 <1200000000>;
 170                         opp-microvolt = <1100000>;
 171                         clock-latency-ns = <40000>;
 172                 };
 173                 opp-1416000000 {
 174                         opp-hz = /bits/ 64 <1416000000>;
 175                         opp-microvolt = <1200000>;
 176                         clock-latency-ns = <40000>;
 177                 };
 178                 opp-1512000000 {
 179                         opp-hz = /bits/ 64 <1512000000>;
 180                         opp-microvolt = <1300000>;
 181                         clock-latency-ns = <40000>;
 182                 };
 183                 opp-1608000000 {
 184                         opp-hz = /bits/ 64 <1608000000>;
 185                         opp-microvolt = <1350000>;
 186                         clock-latency-ns = <40000>;
 187                 };
 188         };
 189
 190         amba {
 191                 compatible = "arm,amba-bus";
 192                 #address-cells = <1>;
 193                 #size-cells = <1>;
 194                 ranges;
 195
 196                 dmac_peri: dma-controller@ff250000 {
 197                         compatible = "arm,pl330", "arm,primecell";
 198                         reg = <0xff250000 0x4000>;
 199                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 200                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 201                         #dma-cells = <1>;
 202                         arm,pl330-broken-no-flushp;
 203                         peripherals-req-type-burst;
 204                         clocks = <&cru ACLK_DMAC2>;
 205                         clock-names = "apb_pclk";
 206                 };
 207
 208                 dmac_bus_ns: dma-controller@ff600000 {
 209                         compatible = "arm,pl330", "arm,primecell";
 210                         reg = <0xff600000 0x4000>;
 211                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 212                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 213                         #dma-cells = <1>;
 214                         arm,pl330-broken-no-flushp;
 215                         peripherals-req-type-burst;
 216                         clocks = <&cru ACLK_DMAC1>;
 217                         clock-names = "apb_pclk";
 218                         status = "disabled";
 219                 };
 220
 221                 dmac_bus_s: dma-controller@ffb20000 {
 222                         compatible = "arm,pl330", "arm,primecell";
 223                         reg = <0xffb20000 0x4000>;
 224                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 225                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 226                         #dma-cells = <1>;
 227                         arm,pl330-broken-no-flushp;
 228                         peripherals-req-type-burst;
 229                         clocks = <&cru ACLK_DMAC1>;
 230                         clock-names = "apb_pclk";
 231                 };
 232         };
 233
 234         reserved-memory {
 235                 #address-cells = <1>;
 236                 #size-cells = <1>;
 237                 ranges;
 238
 239                 /*
 240                  * The rk3288 cannot use the memory area above 0xfe000000
 241                  * for dma operations for some reason. While there is
 242                  * probably a better solution available somewhere, we
 243                  * haven't found it yet and while devices with 2GB of ram
 244                  * are not affected, this issue prevents 4GB from booting.
 245                  * So to make these devices at least bootable, block
 246                  * this area for the time being until the real solution
 247                  * is found.
 248                  */
 249                 dma-unusable@fe000000 {
 250                         reg = <0xfe000000 0x1000000>;
 251                 };
 252         };
 253
 254         xin24m: oscillator {
 255                 compatible = "fixed-clock";
 256                 clock-frequency = <24000000>;
 257                 clock-output-names = "xin24m";
 258                 #clock-cells = <0>;
 259         };
 260
 261         timer {
 262                 compatible = "arm,armv7-timer";
 263                 arm,cpu-registers-not-fw-configured;
 264                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 265                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 266                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
 267                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 268                 clock-frequency = <24000000>;
 269         };
 270
 271         timer: timer@ff810000 {
 272                 compatible = "rockchip,rk3288-timer";
 273                 reg = <0xff810000 0x20>;
 274                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 275                 clocks = <&xin24m>, <&cru PCLK_TIMER>;
 276                 clock-names = "timer", "pclk";
 277         };
 278
 279         display-subsystem {
 280                 compatible = "rockchip,display-subsystem";
 281                 ports = <&vopl_out>, <&vopb_out>;
 282         };
 283
 284         sdmmc: dwmmc@ff0c0000 {
 285                 compatible = "rockchip,rk3288-dw-mshc";
 286                 clock-freq-min-max = <400000 150000000>;
 287                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 288                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 289                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 290                 fifo-depth = <0x100>;
 291                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 292                 reg = <0xff0c0000 0x4000>;
 293                 status = "disabled";
 294         };
 295
 296         sdio0: dwmmc@ff0d0000 {
 297                 compatible = "rockchip,rk3288-dw-mshc";
 298                 clock-freq-min-max = <400000 150000000>;
 299                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 300                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 301                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 302                 fifo-depth = <0x100>;
 303                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 304                 reg = <0xff0d0000 0x4000>;
 305                 status = "disabled";
 306         };
 307
 308         sdio1: dwmmc@ff0e0000 {
 309                 compatible = "rockchip,rk3288-dw-mshc";
 310                 clock-freq-min-max = <400000 150000000>;
 311                 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
 312                          <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
 313                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 314                 fifo-depth = <0x100>;
 315                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 316                 reg = <0xff0e0000 0x4000>;
 317                 status = "disabled";
 318         };
 319
 320         emmc: dwmmc@ff0f0000 {
 321                 compatible = "rockchip,rk3288-dw-mshc";
 322                 clock-freq-min-max = <400000 150000000>;
 323                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 324                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 325                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 326                 fifo-depth = <0x100>;
 327                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 328                 reg = <0xff0f0000 0x4000>;
 329                 status = "disabled";
 330                 supports-emmc;
 331         };
 332
 333         saradc: saradc@ff100000 {
 334                 compatible = "rockchip,saradc";
 335                 reg = <0xff100000 0x100>;
 336                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 337                 #io-channel-cells = <1>;
 338                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 339                 clock-names = "saradc", "apb_pclk";
 340                 resets = <&cru SRST_SARADC>;
 341                 reset-names = "saradc-apb";
 342                 status = "disabled";
 343         };
 344
 345         spi0: spi@ff110000 {
 346                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 347                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 348                 clock-names = "spiclk", "apb_pclk";
 349                 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
 350                 dma-names = "tx", "rx";
 351                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 352                 pinctrl-names = "default";
 353                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 354                 reg = <0xff110000 0x1000>;
 355                 #address-cells = <1>;
 356                 #size-cells = <0>;
 357                 status = "disabled";
 358         };
 359
 360         spi1: spi@ff120000 {
 361                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 362                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 363                 clock-names = "spiclk", "apb_pclk";
 364                 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
 365                 dma-names = "tx", "rx";
 366                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 367                 pinctrl-names = "default";
 368                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 369                 reg = <0xff120000 0x1000>;
 370                 #address-cells = <1>;
 371                 #size-cells = <0>;
 372                 status = "disabled";
 373         };
 374
 375         spi2: spi@ff130000 {
 376                 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
 377                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 378                 clock-names = "spiclk", "apb_pclk";
 379                 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
 380                 dma-names = "tx", "rx";
 381                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
 382                 pinctrl-names = "default";
 383                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 384                 reg = <0xff130000 0x1000>;
 385                 #address-cells = <1>;
 386                 #size-cells = <0>;
 387                 status = "disabled";
 388         };
 389
 390         i2c0: i2c@ff650000 {
 391                 compatible = "rockchip,rk3288-i2c";
 392                 reg = <0xff650000 0x1000>;
 393                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 394                 #address-cells = <1>;
 395                 #size-cells = <0>;
 396                 clock-names = "i2c";
 397                 clocks = <&cru PCLK_I2C0>;
 398                 pinctrl-names = "default";
 399                 pinctrl-0 = <&i2c0_xfer>;
 400                 status = "disabled";
 401         };
 402
 403         i2c1: i2c@ff140000 {
 404                 compatible = "rockchip,rk3288-i2c";
 405                 reg = <0xff140000 0x1000>;
 406                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 407                 #address-cells = <1>;
 408                 #size-cells = <0>;
 409                 clock-names = "i2c";
 410                 clocks = <&cru PCLK_I2C1>;
 411                 pinctrl-names = "default";
 412                 pinctrl-0 = <&i2c1_xfer>;
 413                 status = "disabled";
 414         };
 415
 416         i2c3: i2c@ff150000 {
 417                 compatible = "rockchip,rk3288-i2c";
 418                 reg = <0xff150000 0x1000>;
 419                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 420                 #address-cells = <1>;
 421                 #size-cells = <0>;
 422                 clock-names = "i2c";
 423                 clocks = <&cru PCLK_I2C3>;
 424                 pinctrl-names = "default";
 425                 pinctrl-0 = <&i2c3_xfer>;
 426                 status = "disabled";
 427         };
 428
 429         i2c4: i2c@ff160000 {
 430                 compatible = "rockchip,rk3288-i2c";
 431                 reg = <0xff160000 0x1000>;
 432                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 433                 #address-cells = <1>;
 434                 #size-cells = <0>;
 435                 clock-names = "i2c";
 436                 clocks = <&cru PCLK_I2C4>;
 437                 pinctrl-names = "default";
 438                 pinctrl-0 = <&i2c4_xfer>;
 439                 status = "disabled";
 440         };
 441
 442         i2c5: i2c@ff170000 {
 443                 compatible = "rockchip,rk3288-i2c";
 444                 reg = <0xff170000 0x1000>;
 445                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 446                 #address-cells = <1>;
 447                 #size-cells = <0>;
 448                 clock-names = "i2c";
 449                 clocks = <&cru PCLK_I2C5>;
 450                 pinctrl-names = "default";
 451                 pinctrl-0 = <&i2c5_xfer>;
 452                 status = "disabled";
 453         };
 454
 455         uart0: serial@ff180000 {
 456                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 457                 reg = <0xff180000 0x100>;
 458                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 459                 reg-shift = <2>;
 460                 reg-io-width = <4>;
 461                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 462                 clock-names = "baudclk", "apb_pclk";
 463                 pinctrl-names = "default";
 464                 pinctrl-0 = <&uart0_xfer>;
 465                 status = "disabled";
 466         };
 467
 468         uart1: serial@ff190000 {
 469                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 470                 reg = <0xff190000 0x100>;
 471                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 472                 reg-shift = <2>;
 473                 reg-io-width = <4>;
 474                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 475                 clock-names = "baudclk", "apb_pclk";
 476                 pinctrl-names = "default";
 477                 pinctrl-0 = <&uart1_xfer>;
 478                 status = "disabled";
 479         };
 480
 481         uart2: serial@ff690000 {
 482                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 483                 reg = <0xff690000 0x100>;
 484                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 485                 reg-shift = <2>;
 486                 reg-io-width = <4>;
 487                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 488                 clock-names = "baudclk", "apb_pclk";
 489                 pinctrl-names = "default";
 490                 pinctrl-0 = <&uart2_xfer>;
 491                 status = "disabled";
 492         };
 493
 494         uart3: serial@ff1b0000 {
 495                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 496                 reg = <0xff1b0000 0x100>;
 497                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 498                 reg-shift = <2>;
 499                 reg-io-width = <4>;
 500                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 501                 clock-names = "baudclk", "apb_pclk";
 502                 pinctrl-names = "default";
 503                 pinctrl-0 = <&uart3_xfer>;
 504                 status = "disabled";
 505         };
 506
 507         uart4: serial@ff1c0000 {
 508                 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
 509                 reg = <0xff1c0000 0x100>;
 510                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 511                 reg-shift = <2>;
 512                 reg-io-width = <4>;
 513                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 514                 clock-names = "baudclk", "apb_pclk";
 515                 pinctrl-names = "default";
 516                 pinctrl-0 = <&uart4_xfer>;
 517                 status = "disabled";
 518         };
 519
 520         thermal_zones: thermal-zones {
 521                 soc_thermal: soc-thermal {
 522                         polling-delay-passive = <200>; /* milliseconds */
 523                         polling-delay = <1000>; /* milliseconds */
 524                         sustainable-power = <1200>; /* milliwatts */
 525
 526                         thermal-sensors = <&tsadc 1>;
 527                         trips {
 528                                 threshold: trip-point@0 {
 529                                         temperature = <75000>; /* millicelsius */
 530                                         hysteresis = <2000>; /* millicelsius */
 531                                         type = "passive";
 532                                 };
 533                                 target: trip-point@1 {
 534                                         temperature = <85000>; /* millicelsius */
 535                                         hysteresis = <2000>; /* millicelsius */
 536                                         type = "passive";
 537                                 };
 538                                 soc_crit: soc-crit {
 539                                         temperature = <90000>; /* millicelsius */
 540                                         hysteresis = <2000>; /* millicelsius */
 541                                         type = "critical";
 542                                 };
 543                         };
 544
 545                         cooling-maps {
 546                                 map0 {
 547                                         trip = <&target>;
 548                                         cooling-device =
 549                                         <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 550                                         contribution = <1024>;
 551                                 };
 552                                 map1 {
 553                                         trip = <&target>;
 554                                         cooling-device =
 555                                         <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 556                                         contribution = <1024>;
 557                                 };
 558                         };
 559                 };
 560
 561                 gpu_thermal: gpu-thermal {
 562                         polling-delay-passive = <200>; /* milliseconds */
 563                         polling-delay = <1000>; /* milliseconds */
 564                         thermal-sensors = <&tsadc 2>;
 565                 };
 566         };
 567
 568         tsadc: tsadc@ff280000 {
 569                 compatible = "rockchip,rk3288-tsadc";
 570                 reg = <0xff280000 0x100>;
 571                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 572                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 573                 clock-names = "tsadc", "apb_pclk";
 574                 assigned-clocks = <&cru SCLK_TSADC>;
 575                 assigned-clock-rates = <10000>;
 576                 resets = <&cru SRST_TSADC>;
 577                 reset-names = "tsadc-apb";
 578                 pinctrl-names = "init", "default", "sleep";
 579                 pinctrl-0 = <&otp_gpio>;
 580                 pinctrl-1 = <&otp_out>;
 581                 pinctrl-2 = <&otp_gpio>;
 582                 #thermal-sensor-cells = <1>;
 583                 rockchip,hw-tshut-temp = <95000>;
 584                 status = "disabled";
 585         };
 586
 587         gmac: ethernet@ff290000 {
 588                 compatible = "rockchip,rk3288-gmac";
 589                 reg = <0xff290000 0x10000>;
 590                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
 591                                 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 592                 interrupt-names = "macirq", "eth_wake_irq";
 593                 rockchip,grf = <&grf>;
 594                 clocks = <&cru SCLK_MAC>,
 595                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 596                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 597                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 598                 clock-names = "stmmaceth",
 599                         "mac_clk_rx", "mac_clk_tx",
 600                         "clk_mac_ref", "clk_mac_refout",
 601                         "aclk_mac", "pclk_mac";
 602                 resets = <&cru SRST_MAC>;
 603                 reset-names = "stmmaceth";
 604                 status = "disabled";
 605         };
 606
 607         usb_host0_ehci: usb@ff500000 {
 608                 compatible = "generic-ehci";
 609                 reg = <0xff500000 0x100>;
 610                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 611                 clocks = <&cru HCLK_USBHOST0>;
 612                 clock-names = "usbhost";
 613                 phys = <&usbphy1>;
 614                 phy-names = "usb";
 615                 status = "disabled";
 616         };
 617
 618         /* NOTE: ohci@ff520000 doesn't actually work on hardware */
 619
 620         usb_host1: usb@ff540000 {
 621                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 622                                 "snps,dwc2";
 623                 reg = <0xff540000 0x40000>;
 624                 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 625                 clocks = <&cru HCLK_USBHOST1>;
 626                 clock-names = "otg";
 627                 dr_mode = "host";
 628                 phys = <&usbphy2>;
 629                 phy-names = "usb2-phy";
 630                 status = "disabled";
 631         };
 632
 633         usb_otg: usb@ff580000 {
 634                 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
 635                                 "snps,dwc2";
 636                 reg = <0xff580000 0x40000>;
 637                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 638                 clocks = <&cru HCLK_OTG0>;
 639                 clock-names = "otg";
 640                 dr_mode = "otg";
 641                 g-np-tx-fifo-size = <16>;
 642                 g-rx-fifo-size = <275>;
 643                 g-tx-fifo-size = <256 128 128 64 64 32>;
 644                 g-use-dma;
 645                 phys = <&usbphy0>;
 646                 phy-names = "usb2-phy";
 647                 status = "disabled";
 648         };
 649
 650         usb_hsic: usb@ff5c0000 {
 651                 compatible = "generic-ehci";
 652                 reg = <0xff5c0000 0x100>;
 653                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 654                 clocks = <&cru HCLK_HSIC>;
 655                 clock-names = "usbhost";
 656                 status = "disabled";
 657         };
 658
 659         dmc: dmc@ff610000 {
 660                 compatible = "rockchip,rk3288-dmc", "syscon";
 661                 rockchip,cru = <&cru>;
 662                 rockchip,grf = <&grf>;
 663                 rockchip,pmu = <&pmu>;
 664                 rockchip,sgrf = <&sgrf>;
 665                 rockchip,noc = <&noc>;
 666                 reg = <0xff610000 0x3fc
 667                        0xff620000 0x294
 668                        0xff630000 0x3fc
 669                        0xff640000 0x294>;
 670                 rockchip,sram = <&ddr_sram>;
 671                 clocks = <&cru PCLK_DDRUPCTL0>, <&cru PCLK_PUBL0>,
 672                          <&cru PCLK_DDRUPCTL1>, <&cru PCLK_PUBL1>,
 673                          <&cru ARMCLK>, <&cru ACLK_DMAC1>;
 674                 clock-names = "pclk_ddrupctl0", "pclk_publ0",
 675                               "pclk_ddrupctl1", "pclk_publ1",
 676                               "arm_clk", "aclk_dmac1";
 677         };
 678
 679         i2c2: i2c@ff660000 {
 680                 compatible = "rockchip,rk3288-i2c";
 681                 reg = <0xff660000 0x1000>;
 682                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 683                 #address-cells = <1>;
 684                 #size-cells = <0>;
 685                 clock-names = "i2c";
 686                 clocks = <&cru PCLK_I2C2>;
 687                 pinctrl-names = "default";
 688                 pinctrl-0 = <&i2c2_xfer>;
 689                 status = "disabled";
 690         };
 691
 692         pwm0: pwm@ff680000 {
 693                 compatible = "rockchip,rk3288-pwm";
 694                 reg = <0xff680000 0x10>;
 695                 #pwm-cells = <3>;
 696                 pinctrl-names = "default";
 697                 pinctrl-0 = <&pwm0_pin>;
 698                 clocks = <&cru PCLK_PWM>;
 699                 clock-names = "pwm";
 700                 status = "disabled";
 701         };
 702
 703         pwm1: pwm@ff680010 {
 704                 compatible = "rockchip,rk3288-pwm";
 705                 reg = <0xff680010 0x10>;
 706                 #pwm-cells = <3>;
 707                 pinctrl-names = "default";
 708                 pinctrl-0 = <&pwm1_pin>;
 709                 clocks = <&cru PCLK_PWM>;
 710                 clock-names = "pwm";
 711                 status = "disabled";
 712         };
 713
 714         pwm2: pwm@ff680020 {
 715                 compatible = "rockchip,rk3288-pwm";
 716                 reg = <0xff680020 0x10>;
 717                 #pwm-cells = <3>;
 718                 pinctrl-names = "default";
 719                 pinctrl-0 = <&pwm2_pin>;
 720                 clocks = <&cru PCLK_PWM>;
 721                 clock-names = "pwm";
 722                 status = "disabled";
 723         };
 724
 725         pwm3: pwm@ff680030 {
 726                 compatible = "rockchip,rk3288-pwm";
 727                 reg = <0xff680030 0x10>;
 728                 #pwm-cells = <2>;
 729                 pinctrl-names = "default";
 730                 pinctrl-0 = <&pwm3_pin>;
 731                 clocks = <&cru PCLK_PWM>;
 732                 clock-names = "pwm";
 733                 status = "disabled";
 734         };
 735
 736         bus_intmem@ff700000 {
 737                 compatible = "mmio-sram";
 738                 reg = <0xff700000 0x18000>;
 739                 #address-cells = <1>;
 740                 #size-cells = <1>;
 741                 ranges = <0 0xff700000 0x18000>;
 742                 smp-sram@0 {
 743                         compatible = "rockchip,rk3066-smp-sram";
 744                         reg = <0x00 0x10>;
 745                 };
 746                 ddr_sram: ddr-sram@1000 {
 747                         compatible = "rockchip,rk3288-ddr-sram";
 748                         reg = <0x1000 0x4000>;
 749                 };
 750         };
 751
 752         sram@ff720000 {
 753                 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
 754                 reg = <0xff720000 0x1000>;
 755         };
 756
 757         qos_gpu_r: qos@ffaa0000 {
 758                 compatible = "syscon";
 759                 reg = <0xffaa0000 0x20>;
 760         };
 761
 762         qos_gpu_w: qos@ffaa0080 {
 763                 compatible = "syscon";
 764                 reg = <0xffaa0080 0x20>;
 765         };
 766
 767         qos_vio1_vop: qos@ffad0000 {
 768                 compatible = "syscon";
 769                 reg = <0xffad0000 0x20>;
 770         };
 771
 772         qos_vio1_isp_w0: qos@ffad0100 {
 773                 compatible = "syscon";
 774                 reg = <0xffad0100 0x20>;
 775         };
 776
 777         qos_vio1_isp_w1: qos@ffad0180 {
 778                 compatible = "syscon";
 779                 reg = <0xffad0180 0x20>;
 780         };
 781
 782         qos_vio0_vop: qos@ffad0400 {
 783                 compatible = "syscon";
 784                 reg = <0xffad0400 0x20>;
 785         };
 786
 787         qos_vio0_vip: qos@ffad0480 {
 788                 compatible = "syscon";
 789                 reg = <0xffad0480 0x20>;
 790         };
 791
 792         qos_vio0_iep: qos@ffad0500 {
 793                 compatible = "syscon";
 794                 reg = <0xffad0500 0x20>;
 795         };
 796
 797         qos_vio2_rga_r: qos@ffad0800 {
 798                 compatible = "syscon";
 799                 reg = <0xffad0800 0x20>;
 800         };
 801
 802         qos_vio2_rga_w: qos@ffad0880 {
 803                 compatible = "syscon";
 804                 reg = <0xffad0880 0x20>;
 805         };
 806
 807         qos_vio1_isp_r: qos@ffad0900 {
 808                 compatible = "syscon";
 809                 reg = <0xffad0900 0x20>;
 810         };
 811
 812         qos_video: qos@ffae0000 {
 813                 compatible = "syscon";
 814                 reg = <0xffae0000 0x20>;
 815         };
 816
 817         qos_hevc_r: qos@ffaf0000 {
 818                 compatible = "syscon";
 819                 reg = <0xffaf0000 0x20>;
 820         };
 821
 822         qos_hevc_w: qos@ffaf0080 {
 823                 compatible = "syscon";
 824                 reg = <0xffaf0080 0x20>;
 825         };
 826
 827         pmu: power-management@ff730000 {
 828                 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
 829                 reg = <0xff730000 0x100>;
 830
 831                 power: power-controller {
 832                         compatible = "rockchip,rk3288-power-controller";
 833                         #power-domain-cells = <1>;
 834                         #address-cells = <1>;
 835                         #size-cells = <0>;
 836
 837                         /*
 838                          * Note: Although SCLK_* are the working clocks
 839                          * of device without including on the NOC, needed for
 840                          * synchronous reset.
 841                          *
 842                          * The clocks on the which NOC:
 843                          * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
 844                          * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
 845                          * ACLK_RGA is on ACLK_RGA_NIU.
 846                          * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
 847                          *
 848                          * Which clock are device clocks:
 849                          *      clocks          devices
 850                          *      *_IEP           IEP:Image Enhancement Processor
 851                          *      *_ISP           ISP:Image Signal Processing
 852                          *      *_VIP           VIP:Video Input Processor
 853                          *      *_VOP*          VOP:Visual Output Processor
 854                          *      *_RGA           RGA
 855                          *      *_EDP*          EDP
 856                          *      *_LVDS_*        LVDS
 857                          *      *_HDMI          HDMI
 858                          *      *_MIPI_*        MIPI
 859                          */
 860                         pd_vio@RK3288_PD_VIO {
 861                                 reg = <RK3288_PD_VIO>;
 862                                 clocks = <&cru ACLK_IEP>,
 863                                          <&cru ACLK_ISP>,
 864                                          <&cru ACLK_RGA>,
 865                                          <&cru ACLK_VIP>,
 866                                          <&cru ACLK_VOP0>,
 867                                          <&cru ACLK_VOP1>,
 868                                          <&cru DCLK_VOP0>,
 869                                          <&cru DCLK_VOP1>,
 870                                          <&cru HCLK_IEP>,
 871                                          <&cru HCLK_ISP>,
 872                                          <&cru HCLK_RGA>,
 873                                          <&cru HCLK_VIP>,
 874                                          <&cru HCLK_VOP0>,
 875                                          <&cru HCLK_VOP1>,
 876                                          <&cru PCLK_EDP_CTRL>,
 877                                          <&cru PCLK_HDMI_CTRL>,
 878                                          <&cru PCLK_LVDS_PHY>,
 879                                          <&cru PCLK_MIPI_CSI>,
 880                                          <&cru PCLK_MIPI_DSI0>,
 881                                          <&cru PCLK_MIPI_DSI1>,
 882                                          <&cru SCLK_EDP_24M>,
 883                                          <&cru SCLK_EDP>,
 884                                          <&cru SCLK_ISP_JPE>,
 885                                          <&cru SCLK_ISP>,
 886                                          <&cru SCLK_RGA>;
 887                                 pm_qos = <&qos_vio0_iep>,
 888                                          <&qos_vio1_vop>,
 889                                          <&qos_vio1_isp_w0>,
 890                                          <&qos_vio1_isp_w1>,
 891                                          <&qos_vio0_vop>,
 892                                          <&qos_vio0_vip>,
 893                                          <&qos_vio2_rga_r>,
 894                                          <&qos_vio2_rga_w>,
 895                                          <&qos_vio1_isp_r>;
 896                         };
 897
 898                         /*
 899                          * Note: The following 3 are HEVC(H.265) clocks,
 900                          * and on the ACLK_HEVC_NIU (NOC).
 901                          */
 902                         pd_hevc@RK3288_PD_HEVC {
 903                                 reg = <RK3288_PD_HEVC>;
 904                                 clocks = <&cru ACLK_HEVC>,
 905                                          <&cru SCLK_HEVC_CABAC>,
 906                                          <&cru SCLK_HEVC_CORE>;
 907                                 pm_qos = <&qos_hevc_r>,
 908                                          <&qos_hevc_w>;
 909                         };
 910
 911                         /*
 912                          * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
 913                          * (video endecoder & decoder) clocks that on the
 914                          * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
 915                          */
 916                         pd_video@RK3288_PD_VIDEO {
 917                                 reg = <RK3288_PD_VIDEO>;
 918                                 clocks = <&cru ACLK_VCODEC>,
 919                                          <&cru HCLK_VCODEC>;
 920                                 pm_qos = <&qos_video>;
 921                         };
 922
 923                         /*
 924                          * Note: ACLK_GPU is the GPU clock,
 925                          * and on the ACLK_GPU_NIU (NOC).
 926                          */
 927                         pd_gpu@RK3288_PD_GPU {
 928                                 reg = <RK3288_PD_GPU>;
 929                                 clocks = <&cru ACLK_GPU>;
 930                                 pm_qos = <&qos_gpu_r>,
 931                                          <&qos_gpu_w>;
 932                         };
 933                 };
 934
 935                 reboot-mode {
 936                         compatible = "syscon-reboot-mode";
 937                         offset = <0x94>;
 938                         mode-normal = <BOOT_NORMAL>;
 939                         mode-recovery = <BOOT_RECOVERY>;
 940                         mode-bootloader = <BOOT_FASTBOOT>;
 941                         mode-loader = <BOOT_BL_DOWNLOAD>;
 942                         mode-ums = <BOOT_UMS>;
 943                 };
 944         };
 945
 946         sgrf: syscon@ff740000 {
 947                 compatible = "rockchip,rk3288-sgrf", "syscon";
 948                 reg = <0xff740000 0x1000>;
 949         };
 950
 951         cru: clock-controller@ff760000 {
 952                 compatible = "rockchip,rk3288-cru";
 953                 reg = <0xff760000 0x1000>;
 954                 rockchip,grf = <&grf>;
 955                 #clock-cells = <1>;
 956                 #reset-cells = <1>;
 957                 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
 958                                   <&cru PLL_NPLL>, <&cru ACLK_CPU>,
 959                                   <&cru HCLK_CPU>, <&cru PCLK_CPU>,
 960                                   <&cru ACLK_PERI>, <&cru HCLK_PERI>,
 961                                   <&cru PCLK_PERI>;
 962                 assigned-clock-rates = <594000000>, <400000000>,
 963                                        <500000000>, <300000000>,
 964                                        <150000000>, <75000000>,
 965                                        <300000000>, <150000000>,
 966                                        <75000000>;
 967         };
 968
 969         grf: syscon@ff770000 {
 970                 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
 971                 reg = <0xff770000 0x1000>;
 972
 973                 edp_phy: edp-phy {
 974                         compatible = "rockchip,rk3288-dp-phy";
 975                         clocks = <&cru SCLK_EDP_24M>;
 976                         clock-names = "24m";
 977                         #phy-cells = <0>;
 978                         status = "disabled";
 979                 };
 980
 981                 io_domains: io-domains {
 982                         compatible = "rockchip,rk3288-io-voltage-domain";
 983                         status = "disabled";
 984                 };
 985
 986                 usbphy: usbphy {
 987                         compatible = "rockchip,rk3288-usb-phy";
 988                         #address-cells = <1>;
 989                         #size-cells = <0>;
 990                         status = "disabled";
 991
 992                         usbphy0: usb-phy@320 {
 993                                 #phy-cells = <0>;
 994                                 reg = <0x320>;
 995                                 clocks = <&cru SCLK_OTGPHY0>;
 996                                 clock-names = "phyclk";
 997                                 #clock-cells = <0>;
 998                                 resets = <&cru SRST_USBOTG_PHY>;
 999                                 reset-names = "phy-reset";
1000                         };
1001
1002                         usbphy1: usb-phy@334 {
1003                                 #phy-cells = <0>;
1004                                 reg = <0x334>;
1005                                 clocks = <&cru SCLK_OTGPHY1>;
1006                                 clock-names = "phyclk";
1007                                 #clock-cells = <0>;
1008                         };
1009
1010                         usbphy2: usb-phy@348 {
1011                                 #phy-cells = <0>;
1012                                 reg = <0x348>;
1013                                 clocks = <&cru SCLK_OTGPHY2>;
1014                                 clock-names = "phyclk";
1015                                 #clock-cells = <0>;
1016                                 resets = <&cru SRST_USBHOST1_PHY>;
1017                                 reset-names = "phy-reset";
1018                         };
1019                 };
1020         };
1021
1022         wdt: watchdog@ff800000 {
1023                 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
1024                 reg = <0xff800000 0x100>;
1025                 clocks = <&cru PCLK_WDT>;
1026                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1027                 status = "disabled";
1028         };
1029
1030         spdif: sound@ff8b0000 {
1031                 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
1032                 reg = <0xff8b0000 0x10000>;
1033                 #sound-dai-cells = <0>;
1034                 clock-names = "hclk", "mclk";
1035                 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
1036                 dmas = <&dmac_bus_s 3>;
1037                 dma-names = "tx";
1038                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1039                 pinctrl-names = "default";
1040                 pinctrl-0 = <&spdif_tx>;
1041                 rockchip,grf = <&grf>;
1042                 status = "disabled";
1043         };
1044
1045         i2s: i2s@ff890000 {
1046                 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
1047                 reg = <0xff890000 0x10000>;
1048                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1049                 #address-cells = <1>;
1050                 #size-cells = <0>;
1051                 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
1052                 dma-names = "tx", "rx";
1053                 clock-names = "i2s_hclk", "i2s_clk";
1054                 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
1055                 pinctrl-names = "default";
1056                 pinctrl-0 = <&i2s0_bus>;
1057                 rockchip,playback-channels = <8>;
1058                 rockchip,capture-channels = <2>;
1059                 status = "disabled";
1060         };
1061
1062         cif_isp0: cif_isp@ff910000 {
1063                 compatible = "rockchip,rk3288-cif-isp";
1064                 rockchip,grf = <&grf>;
1065                 reg = <0xff910000 0x10000>, <0xff968000 0x4000>;
1066                 reg-names = "register", "csihost-register";
1067                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1068                         <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
1069                         <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
1070                         <&cru SCLK_MIPIDSI_24M>;
1071                 clock-names = "aclk_isp", "hclk_isp",
1072                         "sclk_isp", "sclk_isp_jpe",
1073                         "pclk_mipi_csi", "pclk_isp_in",
1074                         "sclk_mipidsi_24m";
1075                 resets = <&cru SRST_ISP>;
1076                 reset-names = "rst_isp";
1077                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1078                 interrupt-names = "cif_isp10_irq";
1079                 status = "disabled";
1080         };
1081
1082         isp: isp@ff910000 {
1083                 compatible = "rockchip,rk3288-isp", "rockchip,isp";
1084                 reg = <0xff910000 0x4000>;
1085                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1086                 power-domains = <&power RK3288_PD_VIO>;
1087                 clocks =
1088                         <&cru ACLK_ISP>, <&cru HCLK_ISP>, <&cru SCLK_ISP>,
1089                         <&cru SCLK_ISP_JPE>, <&cru PCLK_ISP_IN>,
1090                         <&cru SCLK_VIP_OUT>, <&cru SCLK_MIPIDSI_24M>,
1091                         <&cru SCLK_VIP_OUT>, <&cru PCLK_MIPI_CSI>;
1092                 clock-names =
1093                         "aclk_isp", "hclk_isp", "clk_isp",
1094                         "clk_isp_jpe", "pclkin_isp", "clk_cif_out",
1095                         "clk_mipi_24m", "clk_cif_pll", "hclk_mipiphy1";
1096                 pinctrl-names =
1097                         "default", "isp_dvp8bit2", "isp_dvp10bit",
1098                         "isp_dvp12bit", "isp_dvp8bit0", "isp_mipi_fl",
1099                         "isp_mipi_fl_prefl", "isp_flash_as_gpio",
1100                         "isp_flash_as_trigger_out";
1101                 pinctrl-0 = <&isp_mipi>;
1102                 pinctrl-1 = <&isp_mipi &isp_dvp_d2d9>;
1103                 pinctrl-2 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1>;
1104                 pinctrl-3 = <&isp_mipi &isp_dvp_d2d9 &isp_dvp_d0d1
1105                                         &isp_dvp_d10d11>;
1106                 pinctrl-4 = <&isp_mipi &isp_dvp_d0d7>;
1107                 pinctrl-5 = <&isp_mipi>;
1108                 pinctrl-6 = <&isp_mipi &isp_prelight>;
1109                 pinctrl-7 = <&isp_flash_trigger_as_gpio>;
1110                 pinctrl-8 = <&isp_flash_trigger>;
1111                 rockchip,isp,mipiphy = <2>;
1112                 rockchip,isp,cifphy = <1>;
1113                 rockchip,isp,mipiphy1,reg = <0xff968000 0x4000>;
1114                 rockchip,grf = <&grf>;
1115                 rockchip,cru = <&cru>;
1116                 rockchip,gpios = <&gpio7 13 GPIO_ACTIVE_HIGH>;
1117                 rockchip,isp,iommu_enable = <1>;
1118                 iommus = <&isp_mmu>;
1119                 status = "disabled";
1120         };
1121
1122         isp_mmu: iommu@ff914000 {
1123                 compatible = "rockchip,iommu";
1124                 reg = <0xff914000 0x100>, <0xff915000 0x100>;
1125                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1126                 interrupt-names = "isp_mmu";
1127                 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>;
1128                 clock-names = "aclk", "hclk";
1129                 rk_iommu,disable_reset_quirk;
1130                 #iommu-cells = <0>;
1131                 power-domains = <&power RK3288_PD_VIO>;
1132                 status = "disabled";
1133         };
1134
1135         rga: rga@ff920000 {
1136                 compatible = "rockchip,rk3288-rga";
1137                 reg = <0xff920000 0x180>;
1138                 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1139                 interrupt-names = "rga";
1140                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1141                 clock-names = "aclk", "hclk", "sclk";
1142                 power-domains = <&power RK3288_PD_VIO>;
1143                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1144                 reset-names = "core", "axi", "ahb";
1145                 dma-coherent;
1146                 status = "disabled";
1147         };
1148
1149         vopb: vop@ff930000 {
1150                 compatible = "rockchip,rk3288-vop";
1151                 reg = <0xff930000 0x19c>, <0xff931000 0x1000>;
1152                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1153                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1154                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1155                 power-domains = <&power RK3288_PD_VIO>;
1156                 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1157                 reset-names = "axi", "ahb", "dclk";
1158                 iommus = <&vopb_mmu>;
1159                 status = "disabled";
1160
1161                 vopb_out: port {
1162                         #address-cells = <1>;
1163                         #size-cells = <0>;
1164
1165                         vopb_out_hdmi: endpoint@0 {
1166                                 reg = <0>;
1167                                 remote-endpoint = <&hdmi_in_vopb>;
1168                         };
1169
1170                         vopb_out_edp: endpoint@1 {
1171                                 reg = <1>;
1172                                 remote-endpoint = <&edp_in_vopb>;
1173                         };
1174
1175                         vopb_out_mipi: endpoint@2 {
1176                                 reg = <2>;
1177                                 remote-endpoint = <&mipi_in_vopb>;
1178                         };
1179
1180                         vopb_out_lvds: endpoint@3 {
1181                                 reg = <3>;
1182                                 remote-endpoint = <&lvds_in_vopb>;
1183                         };
1184                 };
1185         };
1186
1187         vopb_mmu: iommu@ff930300 {
1188                 compatible = "rockchip,iommu";
1189                 reg = <0xff930300 0x100>;
1190                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1191                 interrupt-names = "vopb_mmu";
1192                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1193                 clock-names = "aclk", "hclk";
1194                 power-domains = <&power RK3288_PD_VIO>;
1195                 #iommu-cells = <0>;
1196                 status = "disabled";
1197         };
1198
1199         vopl: vop@ff940000 {
1200                 compatible = "rockchip,rk3288-vop";
1201                 reg = <0xff940000 0x19c>, <0xff941000 0x1000>;
1202                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1203                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1204                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1205                 power-domains = <&power RK3288_PD_VIO>;
1206                 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1207                 reset-names = "axi", "ahb", "dclk";
1208                 iommus = <&vopl_mmu>;
1209                 status = "disabled";
1210
1211                 vopl_out: port {
1212                         #address-cells = <1>;
1213                         #size-cells = <0>;
1214
1215                         vopl_out_hdmi: endpoint@0 {
1216                                 reg = <0>;
1217                                 remote-endpoint = <&hdmi_in_vopl>;
1218                         };
1219
1220                         vopl_out_edp: endpoint@1 {
1221                                 reg = <1>;
1222                                 remote-endpoint = <&edp_in_vopl>;
1223                         };
1224
1225                         vopl_out_mipi: endpoint@2 {
1226                                 reg = <2>;
1227                                 remote-endpoint = <&mipi_in_vopl>;
1228                         };
1229
1230                         vopl_out_lvds: endpoint@3 {
1231                                 reg = <3>;
1232                                 remote-endpoint = <&lvds_in_vopl>;
1233                         };
1234
1235                 };
1236         };
1237
1238         vopl_mmu: iommu@ff940300 {
1239                 compatible = "rockchip,iommu";
1240                 reg = <0xff940300 0x100>;
1241                 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1242                 interrupt-names = "vopl_mmu";
1243                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1244                 clock-names = "aclk", "hclk";
1245                 power-domains = <&power RK3288_PD_VIO>;
1246                 #iommu-cells = <0>;
1247                 status = "disabled";
1248         };
1249
1250         mipi_dsi: mipi@ff960000 {
1251                 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1252                 reg = <0xff960000 0x4000>;
1253                 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1254                 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1255                 clock-names = "ref", "pclk";
1256                 power-domains = <&power RK3288_PD_VIO>;
1257                 rockchip,grf = <&grf>;
1258                 #address-cells = <1>;
1259                 #size-cells = <0>;
1260                 status = "disabled";
1261
1262                 ports {
1263                         mipi_in: port {
1264                                 #address-cells = <1>;
1265                                 #size-cells = <0>;
1266                                 mipi_in_vopb: endpoint@0 {
1267                                         reg = <0>;
1268                                         remote-endpoint = <&vopb_out_mipi>;
1269                                 };
1270                                 mipi_in_vopl: endpoint@1 {
1271                                         reg = <1>;
1272                                         remote-endpoint = <&vopl_out_mipi>;
1273                                 };
1274                         };
1275                 };
1276         };
1277
1278         edp: dp@ff970000 {
1279                 compatible = "rockchip,rk3288-dp";
1280                 reg = <0xff970000 0x4000>;
1281                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1282                 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1283                 clock-names = "dp", "pclk";
1284                 power-domains = <&power RK3288_PD_VIO>;
1285                 phys = <&edp_phy>;
1286                 phy-names = "dp";
1287                 resets = <&cru SRST_EDP>;
1288                 reset-names = "dp";
1289                 rockchip,grf = <&grf>;
1290                 status = "disabled";
1291
1292                 ports {
1293                         #address-cells = <1>;
1294                         #size-cells = <0>;
1295                         edp_in: port@0 {
1296                                 reg = <0>;
1297                                 #address-cells = <1>;
1298                                 #size-cells = <0>;
1299                                 edp_in_vopb: endpoint@0 {
1300                                         reg = <0>;
1301                                         remote-endpoint = <&vopb_out_edp>;
1302                                 };
1303                                 edp_in_vopl: endpoint@1 {
1304                                         reg = <1>;
1305                                         remote-endpoint = <&vopl_out_edp>;
1306                                 };
1307                         };
1308                 };
1309         };
1310
1311         lvds: lvds@ff96c000 {
1312                 compatible = "rockchip,rk3288-lvds";
1313                 reg = <0xff96c000 0x4000>;
1314                 clocks = <&cru PCLK_LVDS_PHY>;
1315                 clock-names = "pclk_lvds";
1316                 pinctrl-names = "default";
1317                 pinctrl-0 = <&lcdc0_ctl>;
1318                 power-domains = <&power RK3288_PD_VIO>;
1319                 rockchip,grf = <&grf>;
1320                 status = "disabled";
1321
1322                 ports {
1323                         #address-cells = <1>;
1324                         #size-cells = <0>;
1325
1326                         lvds_in: port@0 {
1327                                 reg = <0>;
1328
1329                                 #address-cells = <1>;
1330                                 #size-cells = <0>;
1331
1332                                 lvds_in_vopb: endpoint@0 {
1333                                         reg = <0>;
1334                                         remote-endpoint = <&vopb_out_lvds>;
1335                                 };
1336                                 lvds_in_vopl: endpoint@1 {
1337                                         reg = <1>;
1338                                         remote-endpoint = <&vopl_out_lvds>;
1339                                 };
1340                         };
1341                 };
1342         };
1343
1344         hdmi: hdmi@ff980000 {
1345                 compatible = "rockchip,rk3288-dw-hdmi";
1346                 reg = <0xff980000 0x20000>;
1347                 reg-io-width = <4>;
1348                 rockchip,grf = <&grf>;
1349                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1350                 clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1351                 clock-names = "iahb", "isfr";
1352                 pinctrl-names = "default";
1353                 pinctrl-0 = <&hdmi_ddc>;
1354                 power-domains = <&power RK3288_PD_VIO>;
1355                 status = "disabled";
1356
1357                 ports {
1358                         hdmi_in: port {
1359                                 #address-cells = <1>;
1360                                 #size-cells = <0>;
1361                                 hdmi_in_vopb: endpoint@0 {
1362                                         reg = <0>;
1363                                         remote-endpoint = <&vopb_out_hdmi>;
1364                                 };
1365                                 hdmi_in_vopl: endpoint@1 {
1366                                         reg = <1>;
1367                                         remote-endpoint = <&vopl_out_hdmi>;
1368                                 };
1369                         };
1370                 };
1371         };
1372
1373         vpu: video-codec@ff9a0000 {
1374                 compatible = "rockchip,rk3288-vpu";
1375                 reg = <0xff9a0000 0x800>;
1376                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1377                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1378                 interrupt-names = "vepu", "vdpu";
1379                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1380                 clock-names = "aclk", "hclk";
1381                 power-domains = <&power RK3288_PD_VIDEO>;
1382                 iommus = <&vpu_mmu>;
1383                 assigned-clocks = <&cru ACLK_VCODEC>;
1384                 assigned-clock-rates = <400000000>;
1385                 status = "disabled";
1386         };
1387
1388         vpu_service: vpu-service@ff9a0000 {
1389                 compatible = "rockchip,vpu_service";
1390                 reg = <0xff9a0000 0x800>;
1391                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1392                                 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1393                 interrupt-names = "irq_enc", "irq_dec";
1394                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1395                 clock-names = "aclk_vcodec", "hclk_vcodec";
1396                 power-domains = <&power RK3288_PD_VIDEO>;
1397                 rockchip,grf = <&grf>;
1398                 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
1399                 reset-names = "video_a", "video_h";
1400                 iommus = <&vpu_mmu>;
1401                 iommu_enabled = <1>;
1402                 status = "disabled";
1403                 /* 0 means ion, 1 means drm */
1404                 allocator = <1>;
1405         };
1406
1407         vpu_mmu: iommu@ff9a0800 {
1408                 compatible = "rockchip,iommu";
1409                 reg = <0xff9a0800 0x100>;
1410                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1411                 interrupt-names = "vpu_mmu";
1412                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1413                 clock-names = "aclk", "hclk";
1414                 power-domains = <&power RK3288_PD_VIDEO>;
1415                 #iommu-cells = <0>;
1416         };
1417
1418         hevc_service: hevc-service@ff9c0000 {
1419                 compatible = "rockchip,hevc_service";
1420                 reg = <0xff9c0000 0x400>;
1421                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1422                 interrupt-names = "irq_dec";
1423                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1424                         <&cru SCLK_HEVC_CORE>,
1425                         <&cru SCLK_HEVC_CABAC>;
1426                 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
1427                         "clk_cabac";
1428                 /*
1429                  * The 4K hevc would also work well with 500/125/300/300,
1430                  * no more err irq and reset request.
1431                  */
1432                 assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1433                                   <&cru SCLK_HEVC_CORE>,
1434                                   <&cru SCLK_HEVC_CABAC>;
1435                 assigned-clock-rates = <400000000>, <100000000>,
1436                                        <300000000>, <300000000>;
1437
1438                 resets = <&cru SRST_HEVC>;
1439                 reset-names = "video";
1440                 power-domains = <&power RK3288_PD_HEVC>;
1441                 rockchip,grf = <&grf>;
1442                 iommus = <&hevc_mmu>;
1443                 iommu_enabled = <1>;
1444                 status = "disabled";
1445                 /* 0 means ion, 1 means drm */
1446                 allocator = <1>;
1447         };
1448
1449         hevc_mmu: iommu@ff9c0440 {
1450                 compatible = "rockchip,iommu";
1451                 reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
1452                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1453                 interrupt-names = "hevc_mmu";
1454                 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1455                         <&cru SCLK_HEVC_CORE>,
1456                         <&cru SCLK_HEVC_CABAC>;
1457                 clock-names = "aclk", "hclk", "clk_core",
1458                         "clk_cabac";
1459                 power-domains = <&power RK3288_PD_HEVC>;
1460                 #iommu-cells = <0>;
1461         };
1462
1463         gpu: gpu@ffa30000 {
1464                 compatible = "arm,malit764",
1465                              "arm,malit76x",
1466                              "arm,malit7xx",
1467                              "arm,mali-midgard";
1468                 reg = <0xffa30000 0x10000>;
1469                 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1470                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1471                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1472                 interrupt-names = "JOB", "MMU", "GPU";
1473                 clocks = <&cru ACLK_GPU>;
1474                 clock-names = "clk_mali";
1475                 operating-points-v2 = <&gpu_opp_table>;
1476                 #cooling-cells = <2>; /* min followed by max */
1477                 power-domains = <&power RK3288_PD_GPU>;
1478                 status = "disabled";
1479
1480                 upthreshold = <75>;
1481                 downdifferential = <10>;
1482
1483                 gpu_power_model: power_model {
1484                         compatible = "arm,mali-simple-power-model";
1485                         voltage = <950>;
1486                         frequency = <500>;
1487                         static-power = <300>;
1488                         dynamic-power = <396>;
1489                         ts = <32000 4700 (-80) 2>;
1490                         thermal-zone = "gpu-thermal";
1491                 };
1492         };
1493
1494         gpu_opp_table: opp-table1 {
1495                 compatible = "operating-points-v2";
1496
1497                 opp-100000000 {
1498                         opp-hz = /bits/ 64 <100000000>;
1499                         opp-microvolt = <950000>;
1500                 };
1501                 opp-200000000 {
1502                         opp-hz = /bits/ 64 <200000000>;
1503                         opp-microvolt = <950000>;
1504                 };
1505                 opp-300000000 {
1506                         opp-hz = /bits/ 64 <300000000>;
1507                         opp-microvolt = <1000000>;
1508                 };
1509                 opp-400000000 {
1510                         opp-hz = /bits/ 64 <400000000>;
1511                         opp-microvolt = <1100000>;
1512                 };
1513                 opp-600000000 {
1514                         opp-hz = /bits/ 64 <600000000>;
1515                         opp-microvolt = <1250000>;
1516                 };
1517         };
1518
1519         noc: syscon@ffac0000 {
1520                 compatible = "rockchip,rk3288-noc", "syscon";
1521                 reg = <0xffac0000 0x2000>;
1522         };
1523
1524         efuse: efuse@ffb40000 {
1525                 compatible = "rockchip,rockchip-efuse";
1526                 reg = <0xffb40000 0x20>;
1527                 #address-cells = <1>;
1528                 #size-cells = <1>;
1529                 clocks = <&cru PCLK_EFUSE256>;
1530                 clock-names = "pclk_efuse";
1531
1532                 cpu_leakage: cpu_leakage@17 {
1533                         reg = <0x17 0x1>;
1534                 };
1535         };
1536
1537         gic: interrupt-controller@ffc01000 {
1538                 compatible = "arm,gic-400";
1539                 interrupt-controller;
1540                 #interrupt-cells = <3>;
1541                 #address-cells = <0>;
1542
1543                 reg = <0xffc01000 0x1000>,
1544                       <0xffc02000 0x2000>,
1545                       <0xffc04000 0x2000>,
1546                       <0xffc06000 0x2000>;
1547                 interrupts = <GIC_PPI 9 0xf04>;
1548         };
1549
1550         pinctrl: pinctrl {
1551                 compatible = "rockchip,rk3288-pinctrl";
1552                 rockchip,grf = <&grf>;
1553                 rockchip,pmu = <&pmu>;
1554                 #address-cells = <1>;
1555                 #size-cells = <1>;
1556                 ranges;
1557
1558                 gpio0: gpio0@ff750000 {
1559                         compatible = "rockchip,gpio-bank";
1560                         reg =   <0xff750000 0x100>;
1561                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1562                         clocks = <&cru PCLK_GPIO0>;
1563
1564                         gpio-controller;
1565                         #gpio-cells = <2>;
1566
1567                         interrupt-controller;
1568                         #interrupt-cells = <2>;
1569                 };
1570
1571                 gpio1: gpio1@ff780000 {
1572                         compatible = "rockchip,gpio-bank";
1573                         reg = <0xff780000 0x100>;
1574                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1575                         clocks = <&cru PCLK_GPIO1>;
1576
1577                         gpio-controller;
1578                         #gpio-cells = <2>;
1579
1580                         interrupt-controller;
1581                         #interrupt-cells = <2>;
1582                 };
1583
1584                 gpio2: gpio2@ff790000 {
1585                         compatible = "rockchip,gpio-bank";
1586                         reg = <0xff790000 0x100>;
1587                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1588                         clocks = <&cru PCLK_GPIO2>;
1589
1590                         gpio-controller;
1591                         #gpio-cells = <2>;
1592
1593                         interrupt-controller;
1594                         #interrupt-cells = <2>;
1595                 };
1596
1597                 gpio3: gpio3@ff7a0000 {
1598                         compatible = "rockchip,gpio-bank";
1599                         reg = <0xff7a0000 0x100>;
1600                         interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1601                         clocks = <&cru PCLK_GPIO3>;
1602
1603                         gpio-controller;
1604                         #gpio-cells = <2>;
1605
1606                         interrupt-controller;
1607                         #interrupt-cells = <2>;
1608                 };
1609
1610                 gpio4: gpio4@ff7b0000 {
1611                         compatible = "rockchip,gpio-bank";
1612                         reg = <0xff7b0000 0x100>;
1613                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1614                         clocks = <&cru PCLK_GPIO4>;
1615
1616                         gpio-controller;
1617                         #gpio-cells = <2>;
1618
1619                         interrupt-controller;
1620                         #interrupt-cells = <2>;
1621                 };
1622
1623                 gpio5: gpio5@ff7c0000 {
1624                         compatible = "rockchip,gpio-bank";
1625                         reg = <0xff7c0000 0x100>;
1626                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1627                         clocks = <&cru PCLK_GPIO5>;
1628
1629                         gpio-controller;
1630                         #gpio-cells = <2>;
1631
1632                         interrupt-controller;
1633                         #interrupt-cells = <2>;
1634                 };
1635
1636                 gpio6: gpio6@ff7d0000 {
1637                         compatible = "rockchip,gpio-bank";
1638                         reg = <0xff7d0000 0x100>;
1639                         interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1640                         clocks = <&cru PCLK_GPIO6>;
1641
1642                         gpio-controller;
1643                         #gpio-cells = <2>;
1644
1645                         interrupt-controller;
1646                         #interrupt-cells = <2>;
1647                 };
1648
1649                 gpio7: gpio7@ff7e0000 {
1650                         compatible = "rockchip,gpio-bank";
1651                         reg = <0xff7e0000 0x100>;
1652                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1653                         clocks = <&cru PCLK_GPIO7>;
1654
1655                         gpio-controller;
1656                         #gpio-cells = <2>;
1657
1658                         interrupt-controller;
1659                         #interrupt-cells = <2>;
1660                 };
1661
1662                 gpio8: gpio8@ff7f0000 {
1663                         compatible = "rockchip,gpio-bank";
1664                         reg = <0xff7f0000 0x100>;
1665                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1666                         clocks = <&cru PCLK_GPIO8>;
1667
1668                         gpio-controller;
1669                         #gpio-cells = <2>;
1670
1671                         interrupt-controller;
1672                         #interrupt-cells = <2>;
1673                 };
1674
1675                 hdmi {
1676                         hdmi_ddc: hdmi-ddc {
1677                                 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1678                                                 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1679                         };
1680                 };
1681
1682                 pcfg_pull_up: pcfg-pull-up {
1683                         bias-pull-up;
1684                 };
1685
1686                 pcfg_pull_down: pcfg-pull-down {
1687                         bias-pull-down;
1688                 };
1689
1690                 pcfg_pull_none: pcfg-pull-none {
1691                         bias-disable;
1692                 };
1693
1694                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1695                         bias-disable;
1696                         drive-strength = <12>;
1697                 };
1698
1699                 sleep {
1700                         global_pwroff: global-pwroff {
1701                                 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1702                         };
1703
1704                         ddrio_pwroff: ddrio-pwroff {
1705                                 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1706                         };
1707
1708                         ddr0_retention: ddr0-retention {
1709                                 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1710                         };
1711
1712                         ddr1_retention: ddr1-retention {
1713                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1714                         };
1715                 };
1716
1717                 edp {
1718                         edp_hpd: edp-hpd {
1719                                 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1720                         };
1721                 };
1722
1723                 i2c0 {
1724                         i2c0_xfer: i2c0-xfer {
1725                                 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1726                                                 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1727                         };
1728                 };
1729
1730                 i2c1 {
1731                         i2c1_xfer: i2c1-xfer {
1732                                 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1733                                                 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1734                         };
1735                 };
1736
1737                 i2c2 {
1738                         i2c2_xfer: i2c2-xfer {
1739                                 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1740                                                 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1741                         };
1742                 };
1743
1744                 i2c3 {
1745                         i2c3_xfer: i2c3-xfer {
1746                                 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1747                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1748                         };
1749                 };
1750
1751                 i2c4 {
1752                         i2c4_xfer: i2c4-xfer {
1753                                 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1754                                                 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1755                         };
1756                 };
1757
1758                 i2c5 {
1759                         i2c5_xfer: i2c5-xfer {
1760                                 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1761                                                 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1762                         };
1763                 };
1764
1765                 i2s0 {
1766                         i2s0_bus: i2s0-bus {
1767                                 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1768                                                 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1769                                                 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1770                                                 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1771                                                 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1772                                                 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1773                         };
1774                 };
1775
1776                 lcdc0 {
1777                         lcdc0_ctl: lcdc0-ctl {
1778                                 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1779                                                 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1780                                                 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1781                                                 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1782                         };
1783                 };
1784
1785                 sdmmc {
1786                         sdmmc_clk: sdmmc-clk {
1787                                 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1788                         };
1789
1790                         sdmmc_cmd: sdmmc-cmd {
1791                                 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1792                         };
1793
1794                         sdmmc_cd: sdmmc-cd {
1795                                 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1796                         };
1797
1798                         sdmmc_bus1: sdmmc-bus1 {
1799                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1800                         };
1801
1802                         sdmmc_bus4: sdmmc-bus4 {
1803                                 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1804                                                 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1805                                                 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1806                                                 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1807                         };
1808                 };
1809
1810                 sdio0 {
1811                         sdio0_bus1: sdio0-bus1 {
1812                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1813                         };
1814
1815                         sdio0_bus4: sdio0-bus4 {
1816                                 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1817                                                 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1818                                                 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1819                                                 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1820                         };
1821
1822                         sdio0_cmd: sdio0-cmd {
1823                                 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1824                         };
1825
1826                         sdio0_clk: sdio0-clk {
1827                                 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1828                         };
1829
1830                         sdio0_cd: sdio0-cd {
1831                                 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1832                         };
1833
1834                         sdio0_wp: sdio0-wp {
1835                                 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1836                         };
1837
1838                         sdio0_pwr: sdio0-pwr {
1839                                 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1840                         };
1841
1842                         sdio0_bkpwr: sdio0-bkpwr {
1843                                 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1844                         };
1845
1846                         sdio0_int: sdio0-int {
1847                                 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1848                         };
1849                 };
1850
1851                 sdio1 {
1852                         sdio1_bus1: sdio1-bus1 {
1853                                 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1854                         };
1855
1856                         sdio1_bus4: sdio1-bus4 {
1857                                 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1858                                                 <3 25 4 &pcfg_pull_up>,
1859                                                 <3 26 4 &pcfg_pull_up>,
1860                                                 <3 27 4 &pcfg_pull_up>;
1861                         };
1862
1863                         sdio1_cd: sdio1-cd {
1864                                 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1865                         };
1866
1867                         sdio1_wp: sdio1-wp {
1868                                 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1869                         };
1870
1871                         sdio1_bkpwr: sdio1-bkpwr {
1872                                 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1873                         };
1874
1875                         sdio1_int: sdio1-int {
1876                                 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1877                         };
1878
1879                         sdio1_cmd: sdio1-cmd {
1880                                 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1881                         };
1882
1883                         sdio1_clk: sdio1-clk {
1884                                 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1885                         };
1886
1887                         sdio1_pwr: sdio1-pwr {
1888                                 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1889                         };
1890                 };
1891
1892                 emmc {
1893                         emmc_clk: emmc-clk {
1894                                 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1895                         };
1896
1897                         emmc_cmd: emmc-cmd {
1898                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1899                         };
1900
1901                         emmc_pwr: emmc-pwr {
1902                                 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1903                         };
1904
1905                         emmc_bus1: emmc-bus1 {
1906                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1907                         };
1908
1909                         emmc_bus4: emmc-bus4 {
1910                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1911                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1912                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1913                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1914                         };
1915
1916                         emmc_bus8: emmc-bus8 {
1917                                 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1918                                                 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1919                                                 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1920                                                 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1921                                                 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1922                                                 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1923                                                 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1924                                                 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1925                         };
1926                 };
1927
1928                 spi0 {
1929                         spi0_clk: spi0-clk {
1930                                 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1931                         };
1932                         spi0_cs0: spi0-cs0 {
1933                                 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1934                         };
1935                         spi0_tx: spi0-tx {
1936                                 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1937                         };
1938                         spi0_rx: spi0-rx {
1939                                 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1940                         };
1941                         spi0_cs1: spi0-cs1 {
1942                                 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1943                         };
1944                 };
1945                 spi1 {
1946                         spi1_clk: spi1-clk {
1947                                 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1948                         };
1949                         spi1_cs0: spi1-cs0 {
1950                                 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1951                         };
1952                         spi1_rx: spi1-rx {
1953                                 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1954                         };
1955                         spi1_tx: spi1-tx {
1956                                 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1957                         };
1958                 };
1959
1960                 spi2 {
1961                         spi2_cs1: spi2-cs1 {
1962                                 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1963                         };
1964                         spi2_clk: spi2-clk {
1965                                 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1966                         };
1967                         spi2_cs0: spi2-cs0 {
1968                                 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1969                         };
1970                         spi2_rx: spi2-rx {
1971                                 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1972                         };
1973                         spi2_tx: spi2-tx {
1974                                 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1975                         };
1976                 };
1977
1978                 uart0 {
1979                         uart0_xfer: uart0-xfer {
1980                                 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1981                                                 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1982                         };
1983
1984                         uart0_cts: uart0-cts {
1985                                 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1986                         };
1987
1988                         uart0_rts: uart0-rts {
1989                                 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1990                         };
1991                 };
1992
1993                 uart1 {
1994                         uart1_xfer: uart1-xfer {
1995                                 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1996                                                 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1997                         };
1998
1999                         uart1_cts: uart1-cts {
2000                                 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
2001                         };
2002
2003                         uart1_rts: uart1-rts {
2004                                 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
2005                         };
2006                 };
2007
2008                 uart2 {
2009                         uart2_xfer: uart2-xfer {
2010                                 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
2011                                                 <7 23 RK_FUNC_1 &pcfg_pull_none>;
2012                         };
2013                         /* no rts / cts for uart2 */
2014                 };
2015
2016                 uart3 {
2017                         uart3_xfer: uart3-xfer {
2018                                 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
2019                                                 <7 8 RK_FUNC_1 &pcfg_pull_none>;
2020                         };
2021
2022                         uart3_cts: uart3-cts {
2023                                 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
2024                         };
2025
2026                         uart3_rts: uart3-rts {
2027                                 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
2028                         };
2029                 };
2030
2031                 uart4 {
2032                         uart4_xfer: uart4-xfer {
2033                                 rockchip,pins = <5 12 3 &pcfg_pull_up>,
2034                                                 <5 13 3 &pcfg_pull_none>;
2035                         };
2036
2037                         uart4_cts: uart4-cts {
2038                                 rockchip,pins = <5 14 3 &pcfg_pull_up>;
2039                         };
2040
2041                         uart4_rts: uart4-rts {
2042                                 rockchip,pins = <5 15 3 &pcfg_pull_none>;
2043                         };
2044                 };
2045
2046                 tsadc {
2047                         otp_gpio: otp-gpio {
2048                                 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
2049                         };
2050
2051                         otp_out: otp-out {
2052                                 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
2053                         };
2054                 };
2055
2056                 pwm0 {
2057                         pwm0_pin: pwm0-pin {
2058                                 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
2059                         };
2060                 };
2061
2062                 pwm1 {
2063                         pwm1_pin: pwm1-pin {
2064                                 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
2065                         };
2066                 };
2067
2068                 pwm2 {
2069                         pwm2_pin: pwm2-pin {
2070                                 rockchip,pins = <7 22 3 &pcfg_pull_none>;
2071                         };
2072                 };
2073
2074                 pwm3 {
2075                         pwm3_pin: pwm3-pin {
2076                                 rockchip,pins = <7 23 3 &pcfg_pull_none>;
2077                         };
2078                 };
2079
2080                 gmac {
2081                         rgmii_pins: rgmii-pins {
2082                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
2083                                                 <3 31 3 &pcfg_pull_none>,
2084                                                 <3 26 3 &pcfg_pull_none>,
2085                                                 <3 27 3 &pcfg_pull_none>,
2086                                                 <3 28 3 &pcfg_pull_none_12ma>,
2087                                                 <3 29 3 &pcfg_pull_none_12ma>,
2088                                                 <3 24 3 &pcfg_pull_none_12ma>,
2089                                                 <3 25 3 &pcfg_pull_none_12ma>,
2090                                                 <4 0 3 &pcfg_pull_none>,
2091                                                 <4 5 3 &pcfg_pull_none>,
2092                                                 <4 6 3 &pcfg_pull_none>,
2093                                                 <4 9 3 &pcfg_pull_none_12ma>,
2094                                                 <4 4 3 &pcfg_pull_none_12ma>,
2095                                                 <4 1 3 &pcfg_pull_none>,
2096                                                 <4 3 3 &pcfg_pull_none>;
2097                         };
2098
2099                         rmii_pins: rmii-pins {
2100                                 rockchip,pins = <3 30 3 &pcfg_pull_none>,
2101                                                 <3 31 3 &pcfg_pull_none>,
2102                                                 <3 28 3 &pcfg_pull_none>,
2103                                                 <3 29 3 &pcfg_pull_none>,
2104                                                 <4 0 3 &pcfg_pull_none>,
2105                                                 <4 5 3 &pcfg_pull_none>,
2106                                                 <4 4 3 &pcfg_pull_none>,
2107                                                 <4 1 3 &pcfg_pull_none>,
2108                                                 <4 2 3 &pcfg_pull_none>,
2109                                                 <4 3 3 &pcfg_pull_none>;
2110                         };
2111                 };
2112
2113                 spdif {
2114                         spdif_tx: spdif-tx {
2115                                 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
2116                         };
2117                 };
2118
2119                 cif {
2120                         cif_dvp_d2d9: cif-dvp-d2d9 {
2121                                 rockchip,pins = <2 0 RK_FUNC_1 &pcfg_pull_none>,
2122                                                 <2 1 RK_FUNC_1 &pcfg_pull_none>,
2123                                                 <2 2 RK_FUNC_1 &pcfg_pull_none>,
2124                                                 <2 3 RK_FUNC_1 &pcfg_pull_none>,
2125                                                 <2 4 RK_FUNC_1 &pcfg_pull_none>,
2126                                                 <2 5 RK_FUNC_1 &pcfg_pull_none>,
2127                                                 <2 6 RK_FUNC_1 &pcfg_pull_none>,
2128                                                 <2 7 RK_FUNC_1 &pcfg_pull_none>,
2129                                                 <2 8 RK_FUNC_1 &pcfg_pull_none>,
2130                                                 <2 9 RK_FUNC_1 &pcfg_pull_none>,
2131                                                 <2 11 RK_FUNC_1 &pcfg_pull_none>;
2132                         };
2133                 };
2134
2135                 isp_pin {
2136                         isp_mipi: isp-mipi {
2137                                 rockchip,pins =
2138                                         /* cif_clkout */
2139                                         <2 11 RK_FUNC_1 &pcfg_pull_none>;
2140                         };
2141
2142                         isp_dvp_d2d9: isp-d2d9 {
2143                                 rockchip,pins =
2144                                         /* cif_data2 ... cif_data9 */
2145                                         <2 0 RK_FUNC_1 &pcfg_pull_none>,
2146                                         <2 1 RK_FUNC_1 &pcfg_pull_none>,
2147                                         <2 2 RK_FUNC_1 &pcfg_pull_none>,
2148                                         <2 3 RK_FUNC_1 &pcfg_pull_none>,
2149                                         <2 4 RK_FUNC_1 &pcfg_pull_none>,
2150                                         <2 5 RK_FUNC_1 &pcfg_pull_none>,
2151                                         <2 6 RK_FUNC_1 &pcfg_pull_none>,
2152                                         <2 7 RK_FUNC_1 &pcfg_pull_none>,
2153                                         /* cif_sync, cif_href */
2154                                         <2 8 RK_FUNC_1 &pcfg_pull_none>,
2155                                         <2 9 RK_FUNC_1 &pcfg_pull_none>,
2156                                         /* cif_clkin, cif_clkout */
2157                                         <2 10 RK_FUNC_1 &pcfg_pull_none>,
2158                                         <2 11 RK_FUNC_1 &pcfg_pull_none>;
2159                         };
2160
2161                         isp_dvp_d0d1: isp-d0d1 {
2162                                 rockchip,pins =
2163                                         /* cif_data0, cif_data1 */
2164                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
2165                                         <2 13 RK_FUNC_1 &pcfg_pull_none>;
2166                         };
2167
2168                         isp_dvp_d10d11: isp-d10d11 {
2169                                 rockchip,pins =
2170                                         /* cif_data10, cif_data11 */
2171                                         <2 14 RK_FUNC_1 &pcfg_pull_none>,
2172                                         <2 15 RK_FUNC_1 &pcfg_pull_none>;
2173                         };
2174
2175                         isp_dvp_d0d7: isp-d0d7 {
2176                                 rockchip,pins =
2177                                         /* cif_data0 ... cif_data7 */
2178                                         <2 12 RK_FUNC_1 &pcfg_pull_none>,
2179                                         <2 13 RK_FUNC_1 &pcfg_pull_none>,
2180                                         <2 0 RK_FUNC_1 &pcfg_pull_none>,
2181                                         <2 1 RK_FUNC_1 &pcfg_pull_none>,
2182                                         <2 2 RK_FUNC_1 &pcfg_pull_none>,
2183                                         <2 3 RK_FUNC_1 &pcfg_pull_none>,
2184                                         <2 4 RK_FUNC_1 &pcfg_pull_none>,
2185                                         <2 5 RK_FUNC_1 &pcfg_pull_none>;
2186                         };
2187
2188                         isp_shutter: isp-shutter {
2189                                 rockchip,pins =
2190                                         /* SHUTTEREN, SHUTTERTRIG */
2191                                         <7 12 RK_FUNC_2 &pcfg_pull_none>,
2192                                         <7 15 RK_FUNC_2 &pcfg_pull_none>;
2193                         };
2194
2195                         isp_flash_trigger: isp-flash-trigger {
2196                                 rockchip,pins =
2197                                         /* ISP_FLASHTRIGOU */
2198                                         <7 13 RK_FUNC_2 &pcfg_pull_none>;
2199                         };
2200
2201                         isp_prelight: isp-prelight {
2202                                 rockchip,pins =
2203                                         /* ISP_PRELIGHTTRIG */
2204                                         <7 14 RK_FUNC_2 &pcfg_pull_none>;
2205                         };
2206
2207                         isp_flash_trigger_as_gpio: isp-flash-trigger-as-gpio {
2208                                 rockchip,pins =
2209                                         /* ISP_FLASHTRIGOU */
2210                                         <7 13 RK_FUNC_2 &pcfg_pull_none>;
2211                         };
2212                 };
2213
2214         };
2215         rockchip_suspend: rockchip-suspend {
2216                 compatible = "rockchip,pm-rk3288";
2217                 status = "disabled";
2218                 rockchip,sleep-mode-config = <
2219                         (0
2220                         |RKPM_CTR_PWR_DMNS
2221                         |RKPM_CTR_GTCLKS
2222                         |RKPM_CTR_PLLS
2223                         |RKPM_CTR_ARMOFF_LPMD
2224                         )
2225                 >;
2226                 rockchip,wakeup-config = <
2227                         (0
2228                         | RKPM_GPIO_WKUP_EN
2229                         )
2230                 >;
2231                 rockchip,pwm-regulator-config = <
2232                         (0
2233                         | PWM2_REGULATOR_EN
2234                         )
2235                 >;
2236         };
2237 };