2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
41 #include <dt-bindings/gpio/gpio.h>
42 #include <dt-bindings/interrupt-controller/irq.h>
43 #include <dt-bindings/interrupt-controller/arm-gic.h>
44 #include <dt-bindings/pinctrl/rockchip.h>
45 #include <dt-bindings/clock/rk3288-cru.h>
46 #include <dt-bindings/thermal/thermal.h>
47 #include <dt-bindings/power/rk3288-power.h>
48 #include <dt-bindings/soc/rockchip,boot-mode.h>
49 #include "skeleton.dtsi"
52 compatible = "rockchip,rk3288";
54 interrupt-parent = <&gic>;
79 compatible = "arm,cortex-a12-pmu";
80 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
84 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
90 enable-method = "rockchip,rk3066-smp";
91 rockchip,pmu = <&pmu>;
95 compatible = "arm,cortex-a12";
97 resets = <&cru SRST_CORE0>;
113 #cooling-cells = <2>; /* min followed by max */
114 clock-latency = <40000>;
115 clocks = <&cru ARMCLK>;
119 compatible = "arm,cortex-a12";
121 resets = <&cru SRST_CORE1>;
125 compatible = "arm,cortex-a12";
127 resets = <&cru SRST_CORE2>;
131 compatible = "arm,cortex-a12";
133 resets = <&cru SRST_CORE3>;
138 compatible = "arm,amba-bus";
139 #address-cells = <1>;
143 dmac_peri: dma-controller@ff250000 {
144 compatible = "arm,pl330", "arm,primecell";
145 reg = <0xff250000 0x4000>;
146 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
149 arm,pl330-broken-no-flushp;
150 peripherals-req-type-burst;
151 clocks = <&cru ACLK_DMAC2>;
152 clock-names = "apb_pclk";
155 dmac_bus_ns: dma-controller@ff600000 {
156 compatible = "arm,pl330", "arm,primecell";
157 reg = <0xff600000 0x4000>;
158 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
161 arm,pl330-broken-no-flushp;
162 peripherals-req-type-burst;
163 clocks = <&cru ACLK_DMAC1>;
164 clock-names = "apb_pclk";
168 dmac_bus_s: dma-controller@ffb20000 {
169 compatible = "arm,pl330", "arm,primecell";
170 reg = <0xffb20000 0x4000>;
171 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
172 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
174 arm,pl330-broken-no-flushp;
175 peripherals-req-type-burst;
176 clocks = <&cru ACLK_DMAC1>;
177 clock-names = "apb_pclk";
182 #address-cells = <1>;
187 * The rk3288 cannot use the memory area above 0xfe000000
188 * for dma operations for some reason. While there is
189 * probably a better solution available somewhere, we
190 * haven't found it yet and while devices with 2GB of ram
191 * are not affected, this issue prevents 4GB from booting.
192 * So to make these devices at least bootable, block
193 * this area for the time being until the real solution
196 dma-unusable@fe000000 {
197 reg = <0xfe000000 0x1000000>;
202 compatible = "fixed-clock";
203 clock-frequency = <24000000>;
204 clock-output-names = "xin24m";
209 compatible = "arm,armv7-timer";
210 arm,cpu-registers-not-fw-configured;
211 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
212 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
213 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
214 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
215 clock-frequency = <24000000>;
218 timer: timer@ff810000 {
219 compatible = "rockchip,rk3288-timer";
220 reg = <0xff810000 0x20>;
221 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&xin24m>, <&cru PCLK_TIMER>;
223 clock-names = "timer", "pclk";
227 compatible = "rockchip,display-subsystem";
228 ports = <&vopl_out>, <&vopb_out>;
231 sdmmc: dwmmc@ff0c0000 {
232 compatible = "rockchip,rk3288-dw-mshc";
233 clock-freq-min-max = <400000 150000000>;
234 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
235 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
236 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
237 fifo-depth = <0x100>;
238 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
239 reg = <0xff0c0000 0x4000>;
243 sdio0: dwmmc@ff0d0000 {
244 compatible = "rockchip,rk3288-dw-mshc";
245 clock-freq-min-max = <400000 150000000>;
246 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
247 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
248 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
249 fifo-depth = <0x100>;
250 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
251 reg = <0xff0d0000 0x4000>;
255 sdio1: dwmmc@ff0e0000 {
256 compatible = "rockchip,rk3288-dw-mshc";
257 clock-freq-min-max = <400000 150000000>;
258 clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,
259 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;
260 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
261 fifo-depth = <0x100>;
262 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
263 reg = <0xff0e0000 0x4000>;
267 emmc: dwmmc@ff0f0000 {
268 compatible = "rockchip,rk3288-dw-mshc";
269 clock-freq-min-max = <400000 150000000>;
270 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
271 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
272 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
273 fifo-depth = <0x100>;
274 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
275 reg = <0xff0f0000 0x4000>;
280 saradc: saradc@ff100000 {
281 compatible = "rockchip,saradc";
282 reg = <0xff100000 0x100>;
283 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
284 #io-channel-cells = <1>;
285 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
286 clock-names = "saradc", "apb_pclk";
287 resets = <&cru SRST_SARADC>;
288 reset-names = "saradc-apb";
293 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
294 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
295 clock-names = "spiclk", "apb_pclk";
296 dmas = <&dmac_peri 11>, <&dmac_peri 12>;
297 dma-names = "tx", "rx";
298 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
299 pinctrl-names = "default";
300 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
301 reg = <0xff110000 0x1000>;
302 #address-cells = <1>;
308 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
309 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
310 clock-names = "spiclk", "apb_pclk";
311 dmas = <&dmac_peri 13>, <&dmac_peri 14>;
312 dma-names = "tx", "rx";
313 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
316 reg = <0xff120000 0x1000>;
317 #address-cells = <1>;
323 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
324 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
325 clock-names = "spiclk", "apb_pclk";
326 dmas = <&dmac_peri 15>, <&dmac_peri 16>;
327 dma-names = "tx", "rx";
328 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
331 reg = <0xff130000 0x1000>;
332 #address-cells = <1>;
338 compatible = "rockchip,rk3288-i2c";
339 reg = <0xff140000 0x1000>;
340 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
341 #address-cells = <1>;
344 clocks = <&cru PCLK_I2C1>;
345 pinctrl-names = "default";
346 pinctrl-0 = <&i2c1_xfer>;
351 compatible = "rockchip,rk3288-i2c";
352 reg = <0xff150000 0x1000>;
353 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
354 #address-cells = <1>;
357 clocks = <&cru PCLK_I2C3>;
358 pinctrl-names = "default";
359 pinctrl-0 = <&i2c3_xfer>;
364 compatible = "rockchip,rk3288-i2c";
365 reg = <0xff160000 0x1000>;
366 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
367 #address-cells = <1>;
370 clocks = <&cru PCLK_I2C4>;
371 pinctrl-names = "default";
372 pinctrl-0 = <&i2c4_xfer>;
377 compatible = "rockchip,rk3288-i2c";
378 reg = <0xff170000 0x1000>;
379 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
380 #address-cells = <1>;
383 clocks = <&cru PCLK_I2C5>;
384 pinctrl-names = "default";
385 pinctrl-0 = <&i2c5_xfer>;
389 uart0: serial@ff180000 {
390 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
391 reg = <0xff180000 0x100>;
392 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
396 clock-names = "baudclk", "apb_pclk";
397 pinctrl-names = "default";
398 pinctrl-0 = <&uart0_xfer>;
402 uart1: serial@ff190000 {
403 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
404 reg = <0xff190000 0x100>;
405 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
408 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
409 clock-names = "baudclk", "apb_pclk";
410 pinctrl-names = "default";
411 pinctrl-0 = <&uart1_xfer>;
415 uart2: serial@ff690000 {
416 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
417 reg = <0xff690000 0x100>;
418 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
422 clock-names = "baudclk", "apb_pclk";
423 pinctrl-names = "default";
424 pinctrl-0 = <&uart2_xfer>;
428 uart3: serial@ff1b0000 {
429 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
430 reg = <0xff1b0000 0x100>;
431 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
435 clock-names = "baudclk", "apb_pclk";
436 pinctrl-names = "default";
437 pinctrl-0 = <&uart3_xfer>;
441 uart4: serial@ff1c0000 {
442 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
443 reg = <0xff1c0000 0x100>;
444 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
447 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
448 clock-names = "baudclk", "apb_pclk";
449 pinctrl-names = "default";
450 pinctrl-0 = <&uart4_xfer>;
455 reserve_thermal: reserve_thermal {
456 polling-delay-passive = <1000>; /* milliseconds */
457 polling-delay = <5000>; /* milliseconds */
459 thermal-sensors = <&tsadc 0>;
462 cpu_thermal: cpu_thermal {
463 polling-delay-passive = <100>; /* milliseconds */
464 polling-delay = <5000>; /* milliseconds */
466 thermal-sensors = <&tsadc 1>;
469 cpu_alert0: cpu_alert0 {
470 temperature = <70000>; /* millicelsius */
471 hysteresis = <2000>; /* millicelsius */
474 cpu_alert1: cpu_alert1 {
475 temperature = <75000>; /* millicelsius */
476 hysteresis = <2000>; /* millicelsius */
480 temperature = <90000>; /* millicelsius */
481 hysteresis = <2000>; /* millicelsius */
488 trip = <&cpu_alert0>;
490 <&cpu0 THERMAL_NO_LIMIT 6>;
493 trip = <&cpu_alert1>;
495 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
500 gpu_thermal: gpu_thermal {
501 polling-delay-passive = <100>; /* milliseconds */
502 polling-delay = <5000>; /* milliseconds */
504 thermal-sensors = <&tsadc 2>;
507 gpu_alert0: gpu_alert0 {
508 temperature = <70000>; /* millicelsius */
509 hysteresis = <2000>; /* millicelsius */
513 temperature = <90000>; /* millicelsius */
514 hysteresis = <2000>; /* millicelsius */
521 trip = <&gpu_alert0>;
523 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
529 tsadc: tsadc@ff280000 {
530 compatible = "rockchip,rk3288-tsadc";
531 reg = <0xff280000 0x100>;
532 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
534 clock-names = "tsadc", "apb_pclk";
535 resets = <&cru SRST_TSADC>;
536 reset-names = "tsadc-apb";
537 pinctrl-names = "init", "default", "sleep";
538 pinctrl-0 = <&otp_gpio>;
539 pinctrl-1 = <&otp_out>;
540 pinctrl-2 = <&otp_gpio>;
541 #thermal-sensor-cells = <1>;
542 rockchip,hw-tshut-temp = <95000>;
546 gmac: ethernet@ff290000 {
547 compatible = "rockchip,rk3288-gmac";
548 reg = <0xff290000 0x10000>;
549 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
550 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
551 interrupt-names = "macirq", "eth_wake_irq";
552 rockchip,grf = <&grf>;
553 clocks = <&cru SCLK_MAC>,
554 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
555 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
556 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
557 clock-names = "stmmaceth",
558 "mac_clk_rx", "mac_clk_tx",
559 "clk_mac_ref", "clk_mac_refout",
560 "aclk_mac", "pclk_mac";
561 resets = <&cru SRST_MAC>;
562 reset-names = "stmmaceth";
567 usb_host0_ehci: usb@ff500000 {
568 compatible = "generic-ehci";
569 reg = <0xff500000 0x100>;
570 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&cru HCLK_USBHOST0>;
572 clock-names = "usbhost";
578 /* NOTE: ohci@ff520000 doesn't actually work on hardware */
580 usb_host1: usb@ff540000 {
581 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
583 reg = <0xff540000 0x40000>;
584 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
585 clocks = <&cru HCLK_USBHOST1>;
589 phy-names = "usb2-phy";
593 usb_otg: usb@ff580000 {
594 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
596 reg = <0xff580000 0x40000>;
597 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&cru HCLK_OTG0>;
601 g-np-tx-fifo-size = <16>;
602 g-rx-fifo-size = <275>;
603 g-tx-fifo-size = <256 128 128 64 64 32>;
606 phy-names = "usb2-phy";
610 usb_hsic: usb@ff5c0000 {
611 compatible = "generic-ehci";
612 reg = <0xff5c0000 0x100>;
613 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
614 clocks = <&cru HCLK_HSIC>;
615 clock-names = "usbhost";
620 compatible = "rockchip,rk3288-i2c";
621 reg = <0xff650000 0x1000>;
622 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
623 #address-cells = <1>;
626 clocks = <&cru PCLK_I2C0>;
627 pinctrl-names = "default";
628 pinctrl-0 = <&i2c0_xfer>;
633 compatible = "rockchip,rk3288-i2c";
634 reg = <0xff660000 0x1000>;
635 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
636 #address-cells = <1>;
639 clocks = <&cru PCLK_I2C2>;
640 pinctrl-names = "default";
641 pinctrl-0 = <&i2c2_xfer>;
646 compatible = "rockchip,rk3288-pwm";
647 reg = <0xff680000 0x10>;
649 pinctrl-names = "default";
650 pinctrl-0 = <&pwm0_pin>;
651 clocks = <&cru PCLK_PWM>;
657 compatible = "rockchip,rk3288-pwm";
658 reg = <0xff680010 0x10>;
660 pinctrl-names = "default";
661 pinctrl-0 = <&pwm1_pin>;
662 clocks = <&cru PCLK_PWM>;
668 compatible = "rockchip,rk3288-pwm";
669 reg = <0xff680020 0x10>;
671 pinctrl-names = "default";
672 pinctrl-0 = <&pwm2_pin>;
673 clocks = <&cru PCLK_PWM>;
679 compatible = "rockchip,rk3288-pwm";
680 reg = <0xff680030 0x10>;
682 pinctrl-names = "default";
683 pinctrl-0 = <&pwm3_pin>;
684 clocks = <&cru PCLK_PWM>;
689 bus_intmem@ff700000 {
690 compatible = "mmio-sram";
691 reg = <0xff700000 0x18000>;
692 #address-cells = <1>;
694 ranges = <0 0xff700000 0x18000>;
696 compatible = "rockchip,rk3066-smp-sram";
702 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
703 reg = <0xff720000 0x1000>;
706 qos_gpu_r: qos@ffaa0000 {
707 compatible = "syscon";
708 reg = <0xffaa0000 0x20>;
711 qos_gpu_w: qos@ffaa0080 {
712 compatible = "syscon";
713 reg = <0xffaa0080 0x20>;
716 qos_vio1_vop: qos@ffad0000 {
717 compatible = "syscon";
718 reg = <0xffad0000 0x20>;
721 qos_vio1_isp_w0: qos@ffad0100 {
722 compatible = "syscon";
723 reg = <0xffad0100 0x20>;
726 qos_vio1_isp_w1: qos@ffad0180 {
727 compatible = "syscon";
728 reg = <0xffad0180 0x20>;
731 qos_vio0_vop: qos@ffad0400 {
732 compatible = "syscon";
733 reg = <0xffad0400 0x20>;
736 qos_vio0_vip: qos@ffad0480 {
737 compatible = "syscon";
738 reg = <0xffad0480 0x20>;
741 qos_vio0_iep: qos@ffad0500 {
742 compatible = "syscon";
743 reg = <0xffad0500 0x20>;
746 qos_vio2_rga_r: qos@ffad0800 {
747 compatible = "syscon";
748 reg = <0xffad0800 0x20>;
751 qos_vio2_rga_w: qos@ffad0880 {
752 compatible = "syscon";
753 reg = <0xffad0880 0x20>;
756 qos_vio1_isp_r: qos@ffad0900 {
757 compatible = "syscon";
758 reg = <0xffad0900 0x20>;
761 qos_video: qos@ffae0000 {
762 compatible = "syscon";
763 reg = <0xffae0000 0x20>;
766 qos_hevc_r: qos@ffaf0000 {
767 compatible = "syscon";
768 reg = <0xffaf0000 0x20>;
771 qos_hevc_w: qos@ffaf0080 {
772 compatible = "syscon";
773 reg = <0xffaf0080 0x20>;
776 pmu: power-management@ff730000 {
777 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
778 reg = <0xff730000 0x100>;
780 power: power-controller {
781 compatible = "rockchip,rk3288-power-controller";
782 #power-domain-cells = <1>;
783 #address-cells = <1>;
787 * Note: Although SCLK_* are the working clocks
788 * of device without including on the NOC, needed for
791 * The clocks on the which NOC:
792 * ACLK_IEP/ACLK_VIP/ACLK_VOP0 are on ACLK_VIO0_NIU.
793 * ACLK_ISP/ACLK_VOP1 are on ACLK_VIO1_NIU.
794 * ACLK_RGA is on ACLK_RGA_NIU.
795 * The others (HCLK_*,PLCK_*) are on HCLK_VIO_NIU.
797 * Which clock are device clocks:
799 * *_IEP IEP:Image Enhancement Processor
800 * *_ISP ISP:Image Signal Processing
801 * *_VIP VIP:Video Input Processor
802 * *_VOP* VOP:Visual Output Processor
809 pd_vio@RK3288_PD_VIO {
810 reg = <RK3288_PD_VIO>;
811 clocks = <&cru ACLK_IEP>,
825 <&cru PCLK_EDP_CTRL>,
826 <&cru PCLK_HDMI_CTRL>,
827 <&cru PCLK_LVDS_PHY>,
828 <&cru PCLK_MIPI_CSI>,
829 <&cru PCLK_MIPI_DSI0>,
830 <&cru PCLK_MIPI_DSI1>,
836 pm_qos = <&qos_vio0_iep>,
848 * Note: The following 3 are HEVC(H.265) clocks,
849 * and on the ACLK_HEVC_NIU (NOC).
851 pd_hevc@RK3288_PD_HEVC {
852 reg = <RK3288_PD_HEVC>;
853 clocks = <&cru ACLK_HEVC>,
854 <&cru SCLK_HEVC_CABAC>,
855 <&cru SCLK_HEVC_CORE>;
856 pm_qos = <&qos_hevc_r>,
861 * Note: ACLK_VCODEC/HCLK_VCODEC are VCODEC
862 * (video endecoder & decoder) clocks that on the
863 * ACLK_VCODEC_NIU and HCLK_VCODEC_NIU (NOC).
865 pd_video@RK3288_PD_VIDEO {
866 reg = <RK3288_PD_VIDEO>;
867 clocks = <&cru ACLK_VCODEC>,
869 pm_qos = <&qos_video>;
873 * Note: ACLK_GPU is the GPU clock,
874 * and on the ACLK_GPU_NIU (NOC).
876 pd_gpu@RK3288_PD_GPU {
877 reg = <RK3288_PD_GPU>;
878 clocks = <&cru ACLK_GPU>;
879 pm_qos = <&qos_gpu_r>,
885 compatible = "syscon-reboot-mode";
887 mode-normal = <BOOT_NORMAL>;
888 mode-recovery = <BOOT_RECOVERY>;
889 mode-bootloader = <BOOT_FASTBOOT>;
890 mode-loader = <BOOT_LOADER>;
891 mode-ums = <BOOT_UMS>;
895 sgrf: syscon@ff740000 {
896 compatible = "rockchip,rk3288-sgrf", "syscon";
897 reg = <0xff740000 0x1000>;
900 cru: clock-controller@ff760000 {
901 compatible = "rockchip,rk3288-cru";
902 reg = <0xff760000 0x1000>;
903 rockchip,grf = <&grf>;
906 assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
907 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
908 <&cru PLL_NPLL>, <&cru ACLK_CPU>,
909 <&cru HCLK_CPU>, <&cru PCLK_CPU>,
910 <&cru ACLK_PERI>, <&cru HCLK_PERI>,
912 assigned-clock-rates = <0>, <0>,
913 <594000000>, <400000000>,
914 <500000000>, <300000000>,
915 <150000000>, <75000000>,
916 <300000000>, <150000000>,
918 assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>;
921 grf: syscon@ff770000 {
922 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
923 reg = <0xff770000 0x1000>;
926 compatible = "rockchip,rk3288-dp-phy";
927 clocks = <&cru SCLK_EDP_24M>;
933 io_domains: io-domains {
934 compatible = "rockchip,rk3288-io-voltage-domain";
939 compatible = "rockchip,rk3288-usb-phy";
940 #address-cells = <1>;
944 usbphy0: usb-phy@320 {
947 clocks = <&cru SCLK_OTGPHY0>;
948 clock-names = "phyclk";
950 resets = <&cru SRST_USBOTG_PHY>;
951 reset-names = "phy-reset";
954 usbphy1: usb-phy@334 {
957 clocks = <&cru SCLK_OTGPHY1>;
958 clock-names = "phyclk";
962 usbphy2: usb-phy@348 {
965 clocks = <&cru SCLK_OTGPHY2>;
966 clock-names = "phyclk";
968 resets = <&cru SRST_USBHOST1_PHY>;
969 reset-names = "phy-reset";
974 wdt: watchdog@ff800000 {
975 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
976 reg = <0xff800000 0x100>;
977 clocks = <&cru PCLK_WDT>;
978 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
982 spdif: sound@ff88b0000 {
983 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
984 reg = <0xff8b0000 0x10000>;
985 #sound-dai-cells = <0>;
986 clock-names = "hclk", "mclk";
987 clocks = <&cru HCLK_SPDIF8CH>, <&cru SCLK_SPDIF8CH>;
988 dmas = <&dmac_bus_s 3>;
990 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
991 pinctrl-names = "default";
992 pinctrl-0 = <&spdif_tx>;
993 rockchip,grf = <&grf>;
998 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
999 reg = <0xff890000 0x10000>;
1000 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1001 #address-cells = <1>;
1003 dmas = <&dmac_bus_s 0>, <&dmac_bus_s 1>;
1004 dma-names = "tx", "rx";
1005 clock-names = "i2s_hclk", "i2s_clk";
1006 clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
1007 pinctrl-names = "default";
1008 pinctrl-0 = <&i2s0_bus>;
1009 rockchip,playback-channels = <8>;
1010 rockchip,capture-channels = <2>;
1011 status = "disabled";
1015 compatible = "rockchip,rk3288-rga";
1016 reg = <0xff920000 0x180>;
1017 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1018 interrupt-names = "rga";
1019 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA>;
1020 clock-names = "aclk", "hclk", "sclk";
1022 resets = <&cru SRST_RGA_CORE>, <&cru SRST_RGA_AXI>, <&cru SRST_RGA_AHB>;
1024 reset-names = "core", "axi", "ahb";
1025 status = "disabled";
1028 vopb: vop@ff930000 {
1029 compatible = "rockchip,rk3288-vop";
1030 reg = <0xff930000 0x19c>;
1031 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1032 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1033 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1034 power-domains = <&power RK3288_PD_VIO>;
1035 resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
1036 reset-names = "axi", "ahb", "dclk";
1037 iommus = <&vopb_mmu>;
1038 status = "disabled";
1041 #address-cells = <1>;
1044 vopb_out_hdmi: endpoint@0 {
1046 remote-endpoint = <&hdmi_in_vopb>;
1049 vopb_out_edp: endpoint@1 {
1051 remote-endpoint = <&edp_in_vopb>;
1054 vopb_out_mipi: endpoint@2 {
1056 remote-endpoint = <&mipi_in_vopb>;
1059 vopb_out_lvds: endpoint@3 {
1061 remote-endpoint = <&lvds_in_vopb>;
1066 vopb_mmu: iommu@ff930300 {
1067 compatible = "rockchip,iommu";
1068 reg = <0xff930300 0x100>;
1069 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1070 interrupt-names = "vopb_mmu";
1071 power-domains = <&power RK3288_PD_VIO>;
1073 status = "disabled";
1076 vopl: vop@ff940000 {
1077 compatible = "rockchip,rk3288-vop";
1078 reg = <0xff940000 0x19c>;
1079 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1080 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1081 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1082 power-domains = <&power RK3288_PD_VIO>;
1083 resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
1084 reset-names = "axi", "ahb", "dclk";
1085 iommus = <&vopl_mmu>;
1086 status = "disabled";
1089 #address-cells = <1>;
1092 vopl_out_hdmi: endpoint@0 {
1094 remote-endpoint = <&hdmi_in_vopl>;
1097 vopl_out_edp: endpoint@1 {
1099 remote-endpoint = <&edp_in_vopl>;
1102 vopl_out_mipi: endpoint@2 {
1104 remote-endpoint = <&mipi_in_vopl>;
1107 vopl_out_lvds: endpoint@3 {
1109 remote-endpoint = <&lvds_in_vopl>;
1115 vopl_mmu: iommu@ff940300 {
1116 compatible = "rockchip,iommu";
1117 reg = <0xff940300 0x100>;
1118 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1119 interrupt-names = "vopl_mmu";
1120 power-domains = <&power RK3288_PD_VIO>;
1122 status = "disabled";
1125 mipi_dsi: mipi@ff960000 {
1126 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1127 reg = <0xff960000 0x4000>;
1128 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1129 clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
1130 clock-names = "ref", "pclk";
1131 power-domains = <&power RK3288_PD_VIO>;
1132 rockchip,grf = <&grf>;
1133 #address-cells = <1>;
1135 status = "disabled";
1139 #address-cells = <1>;
1141 mipi_in_vopb: endpoint@0 {
1143 remote-endpoint = <&vopb_out_mipi>;
1145 mipi_in_vopl: endpoint@1 {
1147 remote-endpoint = <&vopl_out_mipi>;
1154 compatible = "rockchip,rk3288-dp";
1155 reg = <0xff970000 0x4000>;
1156 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1157 clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
1158 clock-names = "dp", "pclk";
1161 resets = <&cru SRST_EDP>;
1163 rockchip,grf = <&grf>;
1164 status = "disabled";
1167 #address-cells = <1>;
1171 #address-cells = <1>;
1173 edp_in_vopb: endpoint@0 {
1175 remote-endpoint = <&vopb_out_edp>;
1177 edp_in_vopl: endpoint@1 {
1179 remote-endpoint = <&vopl_out_edp>;
1185 lvds: lvds@ff96c000 {
1186 compatible = "rockchip,rk3288-lvds";
1187 reg = <0xff96c000 0x4000>;
1188 clocks = <&cru PCLK_LVDS_PHY>;
1189 clock-names = "pclk_lvds";
1190 pinctrl-names = "default";
1191 pinctrl-0 = <&lcdc0_ctl>;
1192 power-domains = <&power RK3288_PD_VIO>;
1193 rockchip,grf = <&grf>;
1194 status = "disabled";
1197 #address-cells = <1>;
1203 #address-cells = <1>;
1206 lvds_in_vopb: endpoint@0 {
1208 remote-endpoint = <&vopb_out_lvds>;
1210 lvds_in_vopl: endpoint@1 {
1212 remote-endpoint = <&vopl_out_lvds>;
1218 hdmi: hdmi@ff980000 {
1219 compatible = "rockchip,rk3288-dw-hdmi";
1220 reg = <0xff980000 0x20000>;
1222 rockchip,grf = <&grf>;
1223 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1224 clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
1225 clock-names = "iahb", "isfr";
1226 power-domains = <&power RK3288_PD_VIO>;
1227 status = "disabled";
1231 #address-cells = <1>;
1233 hdmi_in_vopb: endpoint@0 {
1235 remote-endpoint = <&vopb_out_hdmi>;
1237 hdmi_in_vopl: endpoint@1 {
1239 remote-endpoint = <&vopl_out_hdmi>;
1246 compatible = "arm,malit764",
1250 reg = <0xffa30000 0x10000>;
1251 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
1252 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
1253 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1254 interrupt-names = "JOB", "MMU", "GPU";
1255 clocks = <&cru ACLK_GPU>;
1256 clock-names = "clk_mali";
1257 operating-points = <
1260 /* 500000 1200000 - See crosbug.com/p/33857 */
1266 #cooling-cells = <2>; /* min followed by max */
1267 power-domains = <&power RK3288_PD_GPU>;
1268 status = "disabled";
1271 vpu: video-codec@ff9a0000 {
1272 compatible = "rockchip,rk3288-vpu";
1273 reg = <0xff9a0000 0x800>;
1274 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1275 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1276 interrupt-names = "vepu", "vdpu";
1277 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1278 clock-names = "aclk", "hclk";
1279 power-domains = <&power RK3288_PD_VIDEO>;
1280 iommus = <&vpu_mmu>;
1281 assigned-clocks = <&cru ACLK_VCODEC>;
1282 assigned-clock-rates = <400000000>;
1283 status = "disabled";
1286 vpu_service: vpu-service@ff9a0000 {
1287 compatible = "rockchip,vpu_service";
1288 reg = <0xff9a0000 0x800>;
1289 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
1290 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1291 interrupt-names = "irq_enc", "irq_dec";
1292 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1293 clock-names = "aclk_vcodec", "hclk_vcodec";
1294 power-domains = <&power RK3288_PD_VIDEO>;
1295 rockchip,grf = <&grf>;
1296 resets = <&cru SRST_VCODEC_AXI>, <&cru SRST_VCODEC_AHB>;
1297 reset-names = "video_a", "video_h";
1298 iommus = <&vpu_mmu>;
1299 iommu_enabled = <1>;
1301 status = "disabled";
1302 /* 0 means ion, 1 means drm */
1306 vpu_mmu: iommu@ff9a0800 {
1307 compatible = "rockchip,iommu";
1308 reg = <0xff9a0800 0x100>;
1309 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1310 interrupt-names = "vpu_mmu";
1311 power-domains = <&power RK3288_PD_VIDEO>;
1315 hevc_service: hevc-service@ff9c0000 {
1316 compatible = "rockchip,hevc_service";
1317 reg = <0xff9c0000 0x400>;
1318 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1319 interrupt-names = "irq_dec";
1320 clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1321 <&cru SCLK_HEVC_CORE>,
1322 <&cru SCLK_HEVC_CABAC>;
1323 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core",
1326 * The 4K hevc would also work well with 500/125/300/300,
1327 * no more err irq and reset request.
1329 assigned-clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
1330 <&cru SCLK_HEVC_CORE>,
1331 <&cru SCLK_HEVC_CABAC>;
1332 assigned-clock-rates = <400000000>, <100000000>,
1333 <300000000>, <300000000>;
1335 resets = <&cru SRST_HEVC>;
1336 reset-names = "video";
1337 power-domains = <&power RK3288_PD_HEVC>;
1338 rockchip,grf = <&grf>;
1340 iommus = <&hevc_mmu>;
1341 iommu_enabled = <1>;
1342 status = "disabled";
1343 /* 0 means ion, 1 means drm */
1347 hevc_mmu: iommu@ff9c0440 {
1348 compatible = "rockchip,iommu";
1349 reg = <0xff9c0440 0x40>, <0xff9c0480 0x40>;
1350 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1351 interrupt-names = "hevc_mmu";
1352 power-domains = <&power RK3288_PD_HEVC>;
1356 gic: interrupt-controller@ffc01000 {
1357 compatible = "arm,gic-400";
1358 interrupt-controller;
1359 #interrupt-cells = <3>;
1360 #address-cells = <0>;
1362 reg = <0xffc01000 0x1000>,
1363 <0xffc02000 0x1000>,
1364 <0xffc04000 0x2000>,
1365 <0xffc06000 0x2000>;
1366 interrupts = <GIC_PPI 9 0xf04>;
1369 efuse: efuse@ffb40000 {
1370 compatible = "rockchip,rockchip-efuse";
1371 reg = <0xffb40000 0x20>;
1372 #address-cells = <1>;
1374 clocks = <&cru PCLK_EFUSE256>;
1375 clock-names = "pclk_efuse";
1377 cpu_leakage: cpu_leakage@17 {
1382 cif_isp0: cif_isp@ff910000 {
1383 compatible = "rockchip,rk3288-cif-isp";
1384 rockchip,grf = <&grf>;
1385 reg = <0xff910000 0x10000>, <0xff968000 0x4000>;
1386 reg-names = "register", "csihost-register";
1387 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>,
1388 <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
1389 <&cru PCLK_MIPI_CSI>, <&cru PCLK_ISP_IN>,
1390 <&cru SCLK_MIPIDSI_24M>;
1391 clock-names = "aclk_isp", "hclk_isp",
1392 "sclk_isp", "sclk_isp_jpe",
1393 "pclk_mipi_csi", "pclk_isp_in",
1395 resets = <&cru SRST_ISP>;
1396 reset-names = "rst_isp";
1397 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1398 interrupt-names = "cif_isp10_irq";
1399 status = "disabled";
1403 compatible = "rockchip,rk3288-pinctrl";
1404 rockchip,grf = <&grf>;
1405 rockchip,pmu = <&pmu>;
1406 #address-cells = <1>;
1410 gpio0: gpio0@ff750000 {
1411 compatible = "rockchip,gpio-bank";
1412 reg = <0xff750000 0x100>;
1413 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1414 clocks = <&cru PCLK_GPIO0>;
1419 interrupt-controller;
1420 #interrupt-cells = <2>;
1423 gpio1: gpio1@ff780000 {
1424 compatible = "rockchip,gpio-bank";
1425 reg = <0xff780000 0x100>;
1426 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1427 clocks = <&cru PCLK_GPIO1>;
1432 interrupt-controller;
1433 #interrupt-cells = <2>;
1436 gpio2: gpio2@ff790000 {
1437 compatible = "rockchip,gpio-bank";
1438 reg = <0xff790000 0x100>;
1439 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
1440 clocks = <&cru PCLK_GPIO2>;
1445 interrupt-controller;
1446 #interrupt-cells = <2>;
1449 gpio3: gpio3@ff7a0000 {
1450 compatible = "rockchip,gpio-bank";
1451 reg = <0xff7a0000 0x100>;
1452 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1453 clocks = <&cru PCLK_GPIO3>;
1458 interrupt-controller;
1459 #interrupt-cells = <2>;
1462 gpio4: gpio4@ff7b0000 {
1463 compatible = "rockchip,gpio-bank";
1464 reg = <0xff7b0000 0x100>;
1465 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1466 clocks = <&cru PCLK_GPIO4>;
1471 interrupt-controller;
1472 #interrupt-cells = <2>;
1475 gpio5: gpio5@ff7c0000 {
1476 compatible = "rockchip,gpio-bank";
1477 reg = <0xff7c0000 0x100>;
1478 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1479 clocks = <&cru PCLK_GPIO5>;
1484 interrupt-controller;
1485 #interrupt-cells = <2>;
1488 gpio6: gpio6@ff7d0000 {
1489 compatible = "rockchip,gpio-bank";
1490 reg = <0xff7d0000 0x100>;
1491 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1492 clocks = <&cru PCLK_GPIO6>;
1497 interrupt-controller;
1498 #interrupt-cells = <2>;
1501 gpio7: gpio7@ff7e0000 {
1502 compatible = "rockchip,gpio-bank";
1503 reg = <0xff7e0000 0x100>;
1504 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1505 clocks = <&cru PCLK_GPIO7>;
1510 interrupt-controller;
1511 #interrupt-cells = <2>;
1514 gpio8: gpio8@ff7f0000 {
1515 compatible = "rockchip,gpio-bank";
1516 reg = <0xff7f0000 0x100>;
1517 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1518 clocks = <&cru PCLK_GPIO8>;
1523 interrupt-controller;
1524 #interrupt-cells = <2>;
1528 hdmi_ddc: hdmi-ddc {
1529 rockchip,pins = <7 19 RK_FUNC_2 &pcfg_pull_none>,
1530 <7 20 RK_FUNC_2 &pcfg_pull_none>;
1534 pcfg_pull_up: pcfg-pull-up {
1538 pcfg_pull_down: pcfg-pull-down {
1542 pcfg_pull_none: pcfg-pull-none {
1546 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1548 drive-strength = <12>;
1552 global_pwroff: global-pwroff {
1553 rockchip,pins = <0 0 RK_FUNC_1 &pcfg_pull_none>;
1556 ddrio_pwroff: ddrio-pwroff {
1557 rockchip,pins = <0 1 RK_FUNC_1 &pcfg_pull_none>;
1560 ddr0_retention: ddr0-retention {
1561 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_up>;
1564 ddr1_retention: ddr1-retention {
1565 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_up>;
1571 rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_down>;
1576 i2c0_xfer: i2c0-xfer {
1577 rockchip,pins = <0 15 RK_FUNC_1 &pcfg_pull_none>,
1578 <0 16 RK_FUNC_1 &pcfg_pull_none>;
1583 i2c1_xfer: i2c1-xfer {
1584 rockchip,pins = <8 4 RK_FUNC_1 &pcfg_pull_none>,
1585 <8 5 RK_FUNC_1 &pcfg_pull_none>;
1590 i2c2_xfer: i2c2-xfer {
1591 rockchip,pins = <6 9 RK_FUNC_1 &pcfg_pull_none>,
1592 <6 10 RK_FUNC_1 &pcfg_pull_none>;
1597 i2c3_xfer: i2c3-xfer {
1598 rockchip,pins = <2 16 RK_FUNC_1 &pcfg_pull_none>,
1599 <2 17 RK_FUNC_1 &pcfg_pull_none>;
1604 i2c4_xfer: i2c4-xfer {
1605 rockchip,pins = <7 17 RK_FUNC_1 &pcfg_pull_none>,
1606 <7 18 RK_FUNC_1 &pcfg_pull_none>;
1611 i2c5_xfer: i2c5-xfer {
1612 rockchip,pins = <7 19 RK_FUNC_1 &pcfg_pull_none>,
1613 <7 20 RK_FUNC_1 &pcfg_pull_none>;
1618 i2s0_bus: i2s0-bus {
1619 rockchip,pins = <6 0 RK_FUNC_1 &pcfg_pull_none>,
1620 <6 1 RK_FUNC_1 &pcfg_pull_none>,
1621 <6 2 RK_FUNC_1 &pcfg_pull_none>,
1622 <6 3 RK_FUNC_1 &pcfg_pull_none>,
1623 <6 4 RK_FUNC_1 &pcfg_pull_none>,
1624 <6 8 RK_FUNC_1 &pcfg_pull_none>;
1629 lcdc0_ctl: lcdc0-ctl {
1630 rockchip,pins = <1 24 RK_FUNC_1 &pcfg_pull_none>,
1631 <1 25 RK_FUNC_1 &pcfg_pull_none>,
1632 <1 26 RK_FUNC_1 &pcfg_pull_none>,
1633 <1 27 RK_FUNC_1 &pcfg_pull_none>;
1638 sdmmc_clk: sdmmc-clk {
1639 rockchip,pins = <6 20 RK_FUNC_1 &pcfg_pull_none>;
1642 sdmmc_cmd: sdmmc-cmd {
1643 rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
1646 sdmmc_cd: sdmcc-cd {
1647 rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
1650 sdmmc_bus1: sdmmc-bus1 {
1651 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>;
1654 sdmmc_bus4: sdmmc-bus4 {
1655 rockchip,pins = <6 16 RK_FUNC_1 &pcfg_pull_up>,
1656 <6 17 RK_FUNC_1 &pcfg_pull_up>,
1657 <6 18 RK_FUNC_1 &pcfg_pull_up>,
1658 <6 19 RK_FUNC_1 &pcfg_pull_up>;
1663 sdio0_bus1: sdio0-bus1 {
1664 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>;
1667 sdio0_bus4: sdio0-bus4 {
1668 rockchip,pins = <4 20 RK_FUNC_1 &pcfg_pull_up>,
1669 <4 21 RK_FUNC_1 &pcfg_pull_up>,
1670 <4 22 RK_FUNC_1 &pcfg_pull_up>,
1671 <4 23 RK_FUNC_1 &pcfg_pull_up>;
1674 sdio0_cmd: sdio0-cmd {
1675 rockchip,pins = <4 24 RK_FUNC_1 &pcfg_pull_up>;
1678 sdio0_clk: sdio0-clk {
1679 rockchip,pins = <4 25 RK_FUNC_1 &pcfg_pull_none>;
1682 sdio0_cd: sdio0-cd {
1683 rockchip,pins = <4 26 RK_FUNC_1 &pcfg_pull_up>;
1686 sdio0_wp: sdio0-wp {
1687 rockchip,pins = <4 27 RK_FUNC_1 &pcfg_pull_up>;
1690 sdio0_pwr: sdio0-pwr {
1691 rockchip,pins = <4 28 RK_FUNC_1 &pcfg_pull_up>;
1694 sdio0_bkpwr: sdio0-bkpwr {
1695 rockchip,pins = <4 29 RK_FUNC_1 &pcfg_pull_up>;
1698 sdio0_int: sdio0-int {
1699 rockchip,pins = <4 30 RK_FUNC_1 &pcfg_pull_up>;
1704 sdio1_bus1: sdio1-bus1 {
1705 rockchip,pins = <3 24 4 &pcfg_pull_up>;
1708 sdio1_bus4: sdio1-bus4 {
1709 rockchip,pins = <3 24 4 &pcfg_pull_up>,
1710 <3 25 4 &pcfg_pull_up>,
1711 <3 26 4 &pcfg_pull_up>,
1712 <3 27 4 &pcfg_pull_up>;
1715 sdio1_cd: sdio1-cd {
1716 rockchip,pins = <3 28 4 &pcfg_pull_up>;
1719 sdio1_wp: sdio1-wp {
1720 rockchip,pins = <3 29 4 &pcfg_pull_up>;
1723 sdio1_bkpwr: sdio1-bkpwr {
1724 rockchip,pins = <3 30 4 &pcfg_pull_up>;
1727 sdio1_int: sdio1-int {
1728 rockchip,pins = <3 31 4 &pcfg_pull_up>;
1731 sdio1_cmd: sdio1-cmd {
1732 rockchip,pins = <4 6 4 &pcfg_pull_up>;
1735 sdio1_clk: sdio1-clk {
1736 rockchip,pins = <4 7 4 &pcfg_pull_none>;
1739 sdio1_pwr: sdio1-pwr {
1740 rockchip,pins = <4 9 4 &pcfg_pull_up>;
1745 emmc_clk: emmc-clk {
1746 rockchip,pins = <3 18 RK_FUNC_2 &pcfg_pull_none>;
1749 emmc_cmd: emmc-cmd {
1750 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_up>;
1753 emmc_pwr: emmc-pwr {
1754 rockchip,pins = <3 9 RK_FUNC_2 &pcfg_pull_up>;
1757 emmc_bus1: emmc-bus1 {
1758 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>;
1761 emmc_bus4: emmc-bus4 {
1762 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1763 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1764 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1765 <3 3 RK_FUNC_2 &pcfg_pull_up>;
1768 emmc_bus8: emmc-bus8 {
1769 rockchip,pins = <3 0 RK_FUNC_2 &pcfg_pull_up>,
1770 <3 1 RK_FUNC_2 &pcfg_pull_up>,
1771 <3 2 RK_FUNC_2 &pcfg_pull_up>,
1772 <3 3 RK_FUNC_2 &pcfg_pull_up>,
1773 <3 4 RK_FUNC_2 &pcfg_pull_up>,
1774 <3 5 RK_FUNC_2 &pcfg_pull_up>,
1775 <3 6 RK_FUNC_2 &pcfg_pull_up>,
1776 <3 7 RK_FUNC_2 &pcfg_pull_up>;
1781 spi0_clk: spi0-clk {
1782 rockchip,pins = <5 12 RK_FUNC_1 &pcfg_pull_up>;
1784 spi0_cs0: spi0-cs0 {
1785 rockchip,pins = <5 13 RK_FUNC_1 &pcfg_pull_up>;
1788 rockchip,pins = <5 14 RK_FUNC_1 &pcfg_pull_up>;
1791 rockchip,pins = <5 15 RK_FUNC_1 &pcfg_pull_up>;
1793 spi0_cs1: spi0-cs1 {
1794 rockchip,pins = <5 16 RK_FUNC_1 &pcfg_pull_up>;
1798 spi1_clk: spi1-clk {
1799 rockchip,pins = <7 12 RK_FUNC_2 &pcfg_pull_up>;
1801 spi1_cs0: spi1-cs0 {
1802 rockchip,pins = <7 13 RK_FUNC_2 &pcfg_pull_up>;
1805 rockchip,pins = <7 14 RK_FUNC_2 &pcfg_pull_up>;
1808 rockchip,pins = <7 15 RK_FUNC_2 &pcfg_pull_up>;
1813 spi2_cs1: spi2-cs1 {
1814 rockchip,pins = <8 3 RK_FUNC_1 &pcfg_pull_up>;
1816 spi2_clk: spi2-clk {
1817 rockchip,pins = <8 6 RK_FUNC_1 &pcfg_pull_up>;
1819 spi2_cs0: spi2-cs0 {
1820 rockchip,pins = <8 7 RK_FUNC_1 &pcfg_pull_up>;
1823 rockchip,pins = <8 8 RK_FUNC_1 &pcfg_pull_up>;
1826 rockchip,pins = <8 9 RK_FUNC_1 &pcfg_pull_up>;
1831 uart0_xfer: uart0-xfer {
1832 rockchip,pins = <4 16 RK_FUNC_1 &pcfg_pull_up>,
1833 <4 17 RK_FUNC_1 &pcfg_pull_none>;
1836 uart0_cts: uart0-cts {
1837 rockchip,pins = <4 18 RK_FUNC_1 &pcfg_pull_up>;
1840 uart0_rts: uart0-rts {
1841 rockchip,pins = <4 19 RK_FUNC_1 &pcfg_pull_none>;
1846 uart1_xfer: uart1-xfer {
1847 rockchip,pins = <5 8 RK_FUNC_1 &pcfg_pull_up>,
1848 <5 9 RK_FUNC_1 &pcfg_pull_none>;
1851 uart1_cts: uart1-cts {
1852 rockchip,pins = <5 10 RK_FUNC_1 &pcfg_pull_up>;
1855 uart1_rts: uart1-rts {
1856 rockchip,pins = <5 11 RK_FUNC_1 &pcfg_pull_none>;
1861 uart2_xfer: uart2-xfer {
1862 rockchip,pins = <7 22 RK_FUNC_1 &pcfg_pull_up>,
1863 <7 23 RK_FUNC_1 &pcfg_pull_none>;
1865 /* no rts / cts for uart2 */
1869 uart3_xfer: uart3-xfer {
1870 rockchip,pins = <7 7 RK_FUNC_1 &pcfg_pull_up>,
1871 <7 8 RK_FUNC_1 &pcfg_pull_none>;
1874 uart3_cts: uart3-cts {
1875 rockchip,pins = <7 9 RK_FUNC_1 &pcfg_pull_up>;
1878 uart3_rts: uart3-rts {
1879 rockchip,pins = <7 10 RK_FUNC_1 &pcfg_pull_none>;
1884 uart4_xfer: uart4-xfer {
1885 rockchip,pins = <5 12 3 &pcfg_pull_up>,
1886 <5 13 3 &pcfg_pull_none>;
1889 uart4_cts: uart4-cts {
1890 rockchip,pins = <5 14 3 &pcfg_pull_up>;
1893 uart4_rts: uart4-rts {
1894 rockchip,pins = <5 15 3 &pcfg_pull_none>;
1899 otp_gpio: otp-gpio {
1900 rockchip,pins = <0 10 RK_FUNC_GPIO &pcfg_pull_none>;
1904 rockchip,pins = <0 10 RK_FUNC_1 &pcfg_pull_none>;
1909 pwm0_pin: pwm0-pin {
1910 rockchip,pins = <7 0 RK_FUNC_1 &pcfg_pull_none>;
1915 pwm1_pin: pwm1-pin {
1916 rockchip,pins = <7 1 RK_FUNC_1 &pcfg_pull_none>;
1921 pwm2_pin: pwm2-pin {
1922 rockchip,pins = <7 22 3 &pcfg_pull_none>;
1927 pwm3_pin: pwm3-pin {
1928 rockchip,pins = <7 23 3 &pcfg_pull_none>;
1933 rgmii_pins: rgmii-pins {
1934 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1935 <3 31 3 &pcfg_pull_none>,
1936 <3 26 3 &pcfg_pull_none>,
1937 <3 27 3 &pcfg_pull_none>,
1938 <3 28 3 &pcfg_pull_none_12ma>,
1939 <3 29 3 &pcfg_pull_none_12ma>,
1940 <3 24 3 &pcfg_pull_none_12ma>,
1941 <3 25 3 &pcfg_pull_none_12ma>,
1942 <4 0 3 &pcfg_pull_none>,
1943 <4 5 3 &pcfg_pull_none>,
1944 <4 6 3 &pcfg_pull_none>,
1945 <4 9 3 &pcfg_pull_none_12ma>,
1946 <4 4 3 &pcfg_pull_none_12ma>,
1947 <4 1 3 &pcfg_pull_none>,
1948 <4 3 3 &pcfg_pull_none>;
1951 rmii_pins: rmii-pins {
1952 rockchip,pins = <3 30 3 &pcfg_pull_none>,
1953 <3 31 3 &pcfg_pull_none>,
1954 <3 28 3 &pcfg_pull_none>,
1955 <3 29 3 &pcfg_pull_none>,
1956 <4 0 3 &pcfg_pull_none>,
1957 <4 5 3 &pcfg_pull_none>,
1958 <4 4 3 &pcfg_pull_none>,
1959 <4 1 3 &pcfg_pull_none>,
1960 <4 2 3 &pcfg_pull_none>,
1961 <4 3 3 &pcfg_pull_none>;
1966 spdif_tx: spdif-tx {
1967 rockchip,pins = <RK_GPIO6 11 RK_FUNC_1 &pcfg_pull_none>;
1972 cif_dvp_d2d9: cif-dvp-d2d9 {
1973 rockchip,pins = <2 0 RK_FUNC_1 &pcfg_pull_none>,
1974 <2 1 RK_FUNC_1 &pcfg_pull_none>,
1975 <2 2 RK_FUNC_1 &pcfg_pull_none>,
1976 <2 3 RK_FUNC_1 &pcfg_pull_none>,
1977 <2 4 RK_FUNC_1 &pcfg_pull_none>,
1978 <2 5 RK_FUNC_1 &pcfg_pull_none>,
1979 <2 6 RK_FUNC_1 &pcfg_pull_none>,
1980 <2 7 RK_FUNC_1 &pcfg_pull_none>,
1981 <2 8 RK_FUNC_1 &pcfg_pull_none>,
1982 <2 9 RK_FUNC_1 &pcfg_pull_none>,
1983 <2 11 RK_FUNC_1 &pcfg_pull_none>;