2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This file is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
44 #include <dt-bindings/interrupt-controller/irq.h>
45 #include <dt-bindings/interrupt-controller/arm-gic.h>
46 #include <dt-bindings/soc/rockchip,boot-mode.h>
47 #include "skeleton.dtsi"
50 interrupt-parent = <&gic>;
70 compatible = "arm,amba-bus";
75 dmac1_s: dma-controller@20018000 {
76 compatible = "arm,pl330", "arm,primecell";
77 reg = <0x20018000 0x4000>;
78 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
81 arm,pl330-broken-no-flushp;
82 clocks = <&cru ACLK_DMA1>;
83 clock-names = "apb_pclk";
86 dmac1_ns: dma-controller@2001c000 {
87 compatible = "arm,pl330", "arm,primecell";
88 reg = <0x2001c000 0x4000>;
89 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
90 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
92 arm,pl330-broken-no-flushp;
93 clocks = <&cru ACLK_DMA1>;
94 clock-names = "apb_pclk";
98 dmac2: dma-controller@20078000 {
99 compatible = "arm,pl330", "arm,primecell";
100 reg = <0x20078000 0x4000>;
101 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
104 arm,pl330-broken-no-flushp;
105 clocks = <&cru ACLK_DMA2>;
106 clock-names = "apb_pclk";
111 compatible = "fixed-clock";
112 clock-frequency = <24000000>;
114 clock-output-names = "xin24m";
117 L2: l2-cache-controller@10138000 {
118 compatible = "arm,pl310-cache";
119 reg = <0x10138000 0x1000>;
125 compatible = "arm,cortex-a9-scu";
126 reg = <0x1013c000 0x100>;
129 global_timer: global-timer@1013c200 {
130 compatible = "arm,cortex-a9-global-timer";
131 reg = <0x1013c200 0x20>;
132 interrupts = <GIC_PPI 11 0x304>;
133 clocks = <&cru CORE_PERI>;
136 local_timer: local-timer@1013c600 {
137 compatible = "arm,cortex-a9-twd-timer";
138 reg = <0x1013c600 0x20>;
139 interrupts = <GIC_PPI 13 0x304>;
140 clocks = <&cru CORE_PERI>;
143 gic: interrupt-controller@1013d000 {
144 compatible = "arm,cortex-a9-gic";
145 interrupt-controller;
146 #interrupt-cells = <3>;
147 reg = <0x1013d000 0x1000>,
151 uart0: serial@10124000 {
152 compatible = "snps,dw-apb-uart";
153 reg = <0x10124000 0x400>;
154 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
157 clock-names = "baudclk", "apb_pclk";
158 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
162 uart1: serial@10126000 {
163 compatible = "snps,dw-apb-uart";
164 reg = <0x10126000 0x400>;
165 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
168 clock-names = "baudclk", "apb_pclk";
169 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
173 usb_otg: usb@10180000 {
174 compatible = "rockchip,rk3066-usb", "snps,dwc2";
175 reg = <0x10180000 0x40000>;
176 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
177 clocks = <&cru HCLK_OTG0>;
180 g-np-tx-fifo-size = <16>;
181 g-rx-fifo-size = <275>;
182 g-tx-fifo-size = <256 128 128 64 64 32>;
185 phy-names = "usb2-phy";
189 usb_host: usb@101c0000 {
190 compatible = "snps,dwc2";
191 reg = <0x101c0000 0x40000>;
192 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
193 clocks = <&cru HCLK_OTG1>;
197 phy-names = "usb2-phy";
201 emac: ethernet@10204000 {
202 compatible = "snps,arc-emac";
203 reg = <0x10204000 0x3c>;
204 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
205 #address-cells = <1>;
208 rockchip,grf = <&grf>;
210 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
211 clock-names = "hclk", "macref";
218 mmc0: dwmmc@10214000 {
219 compatible = "rockchip,rk2928-dw-mshc";
220 reg = <0x10214000 0x1000>;
221 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
223 clock-names = "biu", "ciu";
228 mmc1: dwmmc@10218000 {
229 compatible = "rockchip,rk2928-dw-mshc";
230 reg = <0x10218000 0x1000>;
231 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
232 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
233 clock-names = "biu", "ciu";
238 emmc: dwmmc@1021c000 {
239 compatible = "rockchip,rk2928-dw-mshc";
240 reg = <0x1021c000 0x1000>;
241 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
243 clock-names = "biu", "ciu";
249 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
250 reg = <0x20004000 0x100>;
253 compatible = "syscon-reboot-mode";
255 mode-normal = <BOOT_NORMAL>;
256 mode-recovery = <BOOT_RECOVERY>;
257 mode-bootloader = <BOOT_FASTBOOT>;
258 mode-loader = <BOOT_BL_DOWNLOAD>;
259 mode-ums = <BOOT_UMS>;
264 compatible = "syscon";
265 reg = <0x20008000 0x200>;
269 compatible = "rockchip,rk3066-i2c";
270 reg = <0x2002d000 0x1000>;
271 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
272 #address-cells = <1>;
275 rockchip,grf = <&grf>;
278 clocks = <&cru PCLK_I2C0>;
284 compatible = "rockchip,rk3066-i2c";
285 reg = <0x2002f000 0x1000>;
286 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
287 #address-cells = <1>;
290 rockchip,grf = <&grf>;
292 clocks = <&cru PCLK_I2C1>;
299 compatible = "rockchip,rk2928-pwm";
300 reg = <0x20030000 0x10>;
302 clocks = <&cru PCLK_PWM01>;
307 compatible = "rockchip,rk2928-pwm";
308 reg = <0x20030010 0x10>;
310 clocks = <&cru PCLK_PWM01>;
314 wdt: watchdog@2004c000 {
315 compatible = "snps,dw-wdt";
316 reg = <0x2004c000 0x100>;
317 clocks = <&cru PCLK_WDT>;
318 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
323 compatible = "rockchip,rk2928-pwm";
324 reg = <0x20050020 0x10>;
326 clocks = <&cru PCLK_PWM23>;
331 compatible = "rockchip,rk2928-pwm";
332 reg = <0x20050030 0x10>;
334 clocks = <&cru PCLK_PWM23>;
339 compatible = "rockchip,rk3066-i2c";
340 reg = <0x20056000 0x1000>;
341 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
342 #address-cells = <1>;
345 rockchip,grf = <&grf>;
347 clocks = <&cru PCLK_I2C2>;
354 compatible = "rockchip,rk3066-i2c";
355 reg = <0x2005a000 0x1000>;
356 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
357 #address-cells = <1>;
360 rockchip,grf = <&grf>;
362 clocks = <&cru PCLK_I2C3>;
369 compatible = "rockchip,rk3066-i2c";
370 reg = <0x2005e000 0x1000>;
371 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
372 #address-cells = <1>;
375 rockchip,grf = <&grf>;
377 clocks = <&cru PCLK_I2C4>;
383 uart2: serial@20064000 {
384 compatible = "snps,dw-apb-uart";
385 reg = <0x20064000 0x400>;
386 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
389 clock-names = "baudclk", "apb_pclk";
390 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
394 uart3: serial@20068000 {
395 compatible = "snps,dw-apb-uart";
396 reg = <0x20068000 0x400>;
397 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
400 clock-names = "baudclk", "apb_pclk";
401 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
405 saradc: saradc@2006c000 {
406 compatible = "rockchip,saradc";
407 reg = <0x2006c000 0x100>;
408 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
409 #io-channel-cells = <1>;
410 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
411 clock-names = "saradc", "apb_pclk";
412 resets = <&cru SRST_SARADC>;
413 reset-names = "saradc-apb";
418 compatible = "rockchip,rk3066-spi";
419 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
420 clock-names = "spiclk", "apb_pclk";
421 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
422 reg = <0x20070000 0x1000>;
423 #address-cells = <1>;
425 dmas = <&dmac2 10>, <&dmac2 11>;
426 dma-names = "tx", "rx";
431 compatible = "rockchip,rk3066-spi";
432 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
433 clock-names = "spiclk", "apb_pclk";
434 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
435 reg = <0x20074000 0x1000>;
436 #address-cells = <1>;
438 dmas = <&dmac2 12>, <&dmac2 13>;
439 dma-names = "tx", "rx";