2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include "skeleton.dtsi"
21 interrupt-parent = <&gic>;
41 compatible = "arm,amba-bus";
46 dmac1_s: dma-controller@20018000 {
47 compatible = "arm,pl330", "arm,primecell";
48 reg = <0x20018000 0x4000>;
49 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
50 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
52 clocks = <&cru ACLK_DMA1>;
53 clock-names = "apb_pclk";
56 dmac1_ns: dma-controller@2001c000 {
57 compatible = "arm,pl330", "arm,primecell";
58 reg = <0x2001c000 0x4000>;
59 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
62 clocks = <&cru ACLK_DMA1>;
63 clock-names = "apb_pclk";
67 dmac2: dma-controller@20078000 {
68 compatible = "arm,pl330", "arm,primecell";
69 reg = <0x20078000 0x4000>;
70 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
73 clocks = <&cru ACLK_DMA2>;
74 clock-names = "apb_pclk";
79 compatible = "fixed-clock";
80 clock-frequency = <24000000>;
82 clock-output-names = "xin24m";
85 L2: l2-cache-controller@10138000 {
86 compatible = "arm,pl310-cache";
87 reg = <0x10138000 0x1000>;
93 compatible = "arm,cortex-a9-scu";
94 reg = <0x1013c000 0x100>;
97 global_timer: global-timer@1013c200 {
98 compatible = "arm,cortex-a9-global-timer";
99 reg = <0x1013c200 0x20>;
100 interrupts = <GIC_PPI 11 0x304>;
101 clocks = <&cru CORE_PERI>;
104 local_timer: local-timer@1013c600 {
105 compatible = "arm,cortex-a9-twd-timer";
106 reg = <0x1013c600 0x20>;
107 interrupts = <GIC_PPI 13 0x304>;
108 clocks = <&cru CORE_PERI>;
111 gic: interrupt-controller@1013d000 {
112 compatible = "arm,cortex-a9-gic";
113 interrupt-controller;
114 #interrupt-cells = <3>;
115 reg = <0x1013d000 0x1000>,
119 uart0: serial@10124000 {
120 compatible = "snps,dw-apb-uart";
121 reg = <0x10124000 0x400>;
122 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
125 clock-names = "baudclk", "apb_pclk";
126 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
130 uart1: serial@10126000 {
131 compatible = "snps,dw-apb-uart";
132 reg = <0x10126000 0x400>;
133 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
136 clock-names = "baudclk", "apb_pclk";
137 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
141 usb_otg: usb@10180000 {
142 compatible = "rockchip,rk3066-usb", "snps,dwc2";
143 reg = <0x10180000 0x40000>;
144 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&cru HCLK_OTG0>;
150 usb_host: usb@101c0000 {
151 compatible = "snps,dwc2";
152 reg = <0x101c0000 0x40000>;
153 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
154 clocks = <&cru HCLK_OTG1>;
159 emac: ethernet@10204000 {
160 compatible = "snps,arc-emac";
161 reg = <0x10204000 0x3c>;
162 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
163 #address-cells = <1>;
166 rockchip,grf = <&grf>;
168 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
169 clock-names = "hclk", "macref";
176 mmc0: dwmmc@10214000 {
177 compatible = "rockchip,rk2928-dw-mshc";
178 reg = <0x10214000 0x1000>;
179 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
180 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
181 clock-names = "biu", "ciu";
186 mmc1: dwmmc@10218000 {
187 compatible = "rockchip,rk2928-dw-mshc";
188 reg = <0x10218000 0x1000>;
189 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
190 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
191 clock-names = "biu", "ciu";
196 emmc: dwmmc@1021c000 {
197 compatible = "rockchip,rk2928-dw-mshc";
198 reg = <0x1021c000 0x1000>;
199 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
201 clock-names = "biu", "ciu";
207 compatible = "rockchip,rk3066-pmu", "syscon";
208 reg = <0x20004000 0x100>;
212 compatible = "syscon";
213 reg = <0x20008000 0x200>;
217 compatible = "rockchip,rk3066-i2c";
218 reg = <0x2002d000 0x1000>;
219 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
220 #address-cells = <1>;
223 rockchip,grf = <&grf>;
226 clocks = <&cru PCLK_I2C0>;
232 compatible = "rockchip,rk3066-i2c";
233 reg = <0x2002f000 0x1000>;
234 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
235 #address-cells = <1>;
238 rockchip,grf = <&grf>;
240 clocks = <&cru PCLK_I2C1>;
247 compatible = "rockchip,rk2928-pwm";
248 reg = <0x20030000 0x10>;
250 clocks = <&cru PCLK_PWM01>;
255 compatible = "rockchip,rk2928-pwm";
256 reg = <0x20030010 0x10>;
258 clocks = <&cru PCLK_PWM01>;
262 wdt: watchdog@2004c000 {
263 compatible = "snps,dw-wdt";
264 reg = <0x2004c000 0x100>;
265 clocks = <&cru PCLK_WDT>;
266 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
271 compatible = "rockchip,rk2928-pwm";
272 reg = <0x20050020 0x10>;
274 clocks = <&cru PCLK_PWM23>;
279 compatible = "rockchip,rk2928-pwm";
280 reg = <0x20050030 0x10>;
282 clocks = <&cru PCLK_PWM23>;
287 compatible = "rockchip,rk3066-i2c";
288 reg = <0x20056000 0x1000>;
289 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
290 #address-cells = <1>;
293 rockchip,grf = <&grf>;
295 clocks = <&cru PCLK_I2C2>;
302 compatible = "rockchip,rk3066-i2c";
303 reg = <0x2005a000 0x1000>;
304 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
305 #address-cells = <1>;
308 rockchip,grf = <&grf>;
310 clocks = <&cru PCLK_I2C3>;
317 compatible = "rockchip,rk3066-i2c";
318 reg = <0x2005e000 0x1000>;
319 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
320 #address-cells = <1>;
323 rockchip,grf = <&grf>;
325 clocks = <&cru PCLK_I2C4>;
331 uart2: serial@20064000 {
332 compatible = "snps,dw-apb-uart";
333 reg = <0x20064000 0x400>;
334 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
337 clock-names = "baudclk", "apb_pclk";
338 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
342 uart3: serial@20068000 {
343 compatible = "snps,dw-apb-uart";
344 reg = <0x20068000 0x400>;
345 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
348 clock-names = "baudclk", "apb_pclk";
349 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
353 saradc: saradc@2006c000 {
354 compatible = "rockchip,saradc";
355 reg = <0x2006c000 0x100>;
356 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
357 #io-channel-cells = <1>;
358 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
359 clock-names = "saradc", "apb_pclk";
364 compatible = "rockchip,rk3066-spi";
365 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
366 clock-names = "spiclk", "apb_pclk";
367 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
368 reg = <0x20070000 0x1000>;
369 #address-cells = <1>;
371 dmas = <&dmac2 10>, <&dmac2 11>;
372 dma-names = "tx", "rx";
377 compatible = "rockchip,rk3066-spi";
378 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
379 clock-names = "spiclk", "apb_pclk";
380 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
381 reg = <0x20074000 0x1000>;
382 #address-cells = <1>;
384 dmas = <&dmac2 12>, <&dmac2 13>;
385 dma-names = "tx", "rx";