2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include "skeleton.dtsi"
21 interrupt-parent = <&gic>;
24 compatible = "fixed-clock";
25 clock-frequency = <24000000>;
27 clock-output-names = "xin24m";
31 compatible = "arm,cortex-a9-scu";
32 reg = <0x1013c000 0x100>;
36 compatible = "rockchip,rk3066-pmu", "syscon";
37 reg = <0x20004000 0x100>;
41 compatible = "syscon";
42 reg = <0x20008000 0x200>;
45 gic: interrupt-controller@1013d000 {
46 compatible = "arm,cortex-a9-gic";
48 #interrupt-cells = <3>;
49 reg = <0x1013d000 0x1000>,
53 L2: l2-cache-controller@10138000 {
54 compatible = "arm,pl310-cache";
55 reg = <0x10138000 0x1000>;
60 global_timer: global-timer@1013c200 {
61 compatible = "arm,cortex-a9-global-timer";
62 reg = <0x1013c200 0x20>;
63 interrupts = <GIC_PPI 11 0x304>;
64 clocks = <&cru CORE_PERI>;
67 local_timer: local-timer@1013c600 {
68 compatible = "arm,cortex-a9-twd-timer";
69 reg = <0x1013c600 0x20>;
70 interrupts = <GIC_PPI 13 0x304>;
71 clocks = <&cru CORE_PERI>;
74 uart0: serial@10124000 {
75 compatible = "snps,dw-apb-uart";
76 reg = <0x10124000 0x400>;
77 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
80 clocks = <&cru SCLK_UART0>;
84 uart1: serial@10126000 {
85 compatible = "snps,dw-apb-uart";
86 reg = <0x10126000 0x400>;
87 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
90 clocks = <&cru SCLK_UART1>;
94 uart2: serial@20064000 {
95 compatible = "snps,dw-apb-uart";
96 reg = <0x20064000 0x400>;
97 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
100 clocks = <&cru SCLK_UART2>;
104 uart3: serial@20068000 {
105 compatible = "snps,dw-apb-uart";
106 reg = <0x20068000 0x400>;
107 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&cru SCLK_UART3>;
114 mmc0: dwmmc@10214000 {
115 compatible = "rockchip,rk2928-dw-mshc";
116 reg = <0x10214000 0x1000>;
117 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
118 #address-cells = <1>;
121 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
122 clock-names = "biu", "ciu";
127 mmc1: dwmmc@10218000 {
128 compatible = "rockchip,rk2928-dw-mshc";
129 reg = <0x10218000 0x1000>;
130 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
131 #address-cells = <1>;
134 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>;
135 clock-names = "biu", "ciu";