arch/arm/boot/dts/sama5d4.dtsi

   1 /*
   2  * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
   3  *
   4  *  Copyright (C) 2014 Atmel,
   5  *                2014 Nicolas Ferre <nicolas.ferre@atmel.com>
   6  *
   7  * This file is dual-licensed: you can use it either under the terms
   8  * of the GPL or the X11 license, at your option. Note that this dual
   9  * licensing only applies to this file, and not this project as a
  10  * whole.
  11  *
  12  *  a) This file is free software; you can redistribute it and/or
  13  *     modify it under the terms of the GNU General Public License as
  14  *     published by the Free Software Foundation; either version 2 of the
  15  *     License, or (at your option) any later version.
  16  *
  17  *     This file is distributed in the hope that it will be useful,
  18  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *     GNU General Public License for more details.
  21  *
  22  * Or, alternatively,
  23  *
  24  *  b) Permission is hereby granted, free of charge, to any person
  25  *     obtaining a copy of this software and associated documentation
  26  *     files (the "Software"), to deal in the Software without
  27  *     restriction, including without limitation the rights to use,
  28  *     copy, modify, merge, publish, distribute, sublicense, and/or
  29  *     sell copies of the Software, and to permit persons to whom the
  30  *     Software is furnished to do so, subject to the following
  31  *     conditions:
  32  *
  33  *     The above copyright notice and this permission notice shall be
  34  *     included in all copies or substantial portions of the Software.
  35  *
  36  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  37  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  38  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  39  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  40  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  41  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  42  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  43  *     OTHER DEALINGS IN THE SOFTWARE.
  44  */
  45
  46 #include "skeleton.dtsi"
  47 #include <dt-bindings/clock/at91.h>
  48 #include <dt-bindings/dma/at91.h>
  49 #include <dt-bindings/pinctrl/at91.h>
  50 #include <dt-bindings/interrupt-controller/irq.h>
  51 #include <dt-bindings/gpio/gpio.h>
  52
  53 / {
  54         model = "Atmel SAMA5D4 family SoC";
  55         compatible = "atmel,sama5d4";
  56         interrupt-parent = <&aic>;
  57
  58         aliases {
  59                 serial0 = &usart3;
  60                 serial1 = &usart4;
  61                 serial2 = &usart2;
  62                 serial3 = &usart0;
  63                 serial4 = &usart1;
  64                 serial5 = &uart0;
  65                 serial6 = &uart1;
  66                 gpio0 = &pioA;
  67                 gpio1 = &pioB;
  68                 gpio2 = &pioC;
  69                 gpio3 = &pioD;
  70                 gpio4 = &pioE;
  71                 pwm0 = &pwm0;
  72                 ssc0 = &ssc0;
  73                 ssc1 = &ssc1;
  74                 tcb0 = &tcb0;
  75                 tcb1 = &tcb1;
  76                 i2c0 = &i2c0;
  77                 i2c1 = &i2c1;
  78                 i2c2 = &i2c2;
  79         };
  80         cpus {
  81                 #address-cells = <1>;
  82                 #size-cells = <0>;
  83
  84                 cpu@0 {
  85                         device_type = "cpu";
  86                         compatible = "arm,cortex-a5";
  87                         reg = <0>;
  88                         next-level-cache = <&L2>;
  89                 };
  90         };
  91
  92         memory {
  93                 reg = <0x20000000 0x20000000>;
  94         };
  95
  96         clocks {
  97                 slow_xtal: slow_xtal {
  98                         compatible = "fixed-clock";
  99                         #clock-cells = <0>;
 100                         clock-frequency = <0>;
 101                 };
 102
 103                 main_xtal: main_xtal {
 104                         compatible = "fixed-clock";
 105                         #clock-cells = <0>;
 106                         clock-frequency = <0>;
 107                 };
 108
 109                 adc_op_clk: adc_op_clk{
 110                         compatible = "fixed-clock";
 111                         #clock-cells = <0>;
 112                         clock-frequency = <1000000>;
 113                 };
 114         };
 115
 116         ns_sram: sram@00210000 {
 117                 compatible = "mmio-sram";
 118                 reg = <0x00210000 0x10000>;
 119         };
 120
 121         ahb {
 122                 compatible = "simple-bus";
 123                 #address-cells = <1>;
 124                 #size-cells = <1>;
 125                 ranges;
 126
 127                 usb0: gadget@00400000 {
 128                         #address-cells = <1>;
 129                         #size-cells = <0>;
 130                         compatible = "atmel,at91sam9rl-udc";
 131                         reg = <0x00400000 0x100000
 132                                0xfc02c000 0x4000>;
 133                         interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
 134                         clocks = <&udphs_clk>, <&utmi>;
 135                         clock-names = "pclk", "hclk";
 136                         status = "disabled";
 137
 138                         ep0 {
 139                                 reg = <0>;
 140                                 atmel,fifo-size = <64>;
 141                                 atmel,nb-banks = <1>;
 142                         };
 143
 144                         ep1 {
 145                                 reg = <1>;
 146                                 atmel,fifo-size = <1024>;
 147                                 atmel,nb-banks = <3>;
 148                                 atmel,can-dma;
 149                                 atmel,can-isoc;
 150                         };
 151
 152                         ep2 {
 153                                 reg = <2>;
 154                                 atmel,fifo-size = <1024>;
 155                                 atmel,nb-banks = <3>;
 156                                 atmel,can-dma;
 157                                 atmel,can-isoc;
 158                         };
 159
 160                         ep3 {
 161                                 reg = <3>;
 162                                 atmel,fifo-size = <1024>;
 163                                 atmel,nb-banks = <2>;
 164                                 atmel,can-dma;
 165                                 atmel,can-isoc;
 166                         };
 167
 168                         ep4 {
 169                                 reg = <4>;
 170                                 atmel,fifo-size = <1024>;
 171                                 atmel,nb-banks = <2>;
 172                                 atmel,can-dma;
 173                                 atmel,can-isoc;
 174                         };
 175
 176                         ep5 {
 177                                 reg = <5>;
 178                                 atmel,fifo-size = <1024>;
 179                                 atmel,nb-banks = <2>;
 180                                 atmel,can-dma;
 181                                 atmel,can-isoc;
 182                         };
 183
 184                         ep6 {
 185                                 reg = <6>;
 186                                 atmel,fifo-size = <1024>;
 187                                 atmel,nb-banks = <2>;
 188                                 atmel,can-dma;
 189                                 atmel,can-isoc;
 190                         };
 191
 192                         ep7 {
 193                                 reg = <7>;
 194                                 atmel,fifo-size = <1024>;
 195                                 atmel,nb-banks = <2>;
 196                                 atmel,can-dma;
 197                                 atmel,can-isoc;
 198                         };
 199
 200                         ep8 {
 201                                 reg = <8>;
 202                                 atmel,fifo-size = <1024>;
 203                                 atmel,nb-banks = <2>;
 204                                 atmel,can-isoc;
 205                         };
 206
 207                         ep9 {
 208                                 reg = <9>;
 209                                 atmel,fifo-size = <1024>;
 210                                 atmel,nb-banks = <2>;
 211                                 atmel,can-isoc;
 212                         };
 213
 214                         ep10 {
 215                                 reg = <10>;
 216                                 atmel,fifo-size = <1024>;
 217                                 atmel,nb-banks = <2>;
 218                                 atmel,can-isoc;
 219                         };
 220
 221                         ep11 {
 222                                 reg = <11>;
 223                                 atmel,fifo-size = <1024>;
 224                                 atmel,nb-banks = <2>;
 225                                 atmel,can-isoc;
 226                         };
 227
 228                         ep12 {
 229                                 reg = <12>;
 230                                 atmel,fifo-size = <1024>;
 231                                 atmel,nb-banks = <2>;
 232                                 atmel,can-isoc;
 233                         };
 234
 235                         ep13 {
 236                                 reg = <13>;
 237                                 atmel,fifo-size = <1024>;
 238                                 atmel,nb-banks = <2>;
 239                                 atmel,can-isoc;
 240                         };
 241
 242                         ep14 {
 243                                 reg = <14>;
 244                                 atmel,fifo-size = <1024>;
 245                                 atmel,nb-banks = <2>;
 246                                 atmel,can-isoc;
 247                         };
 248
 249                         ep15 {
 250                                 reg = <15>;
 251                                 atmel,fifo-size = <1024>;
 252                                 atmel,nb-banks = <2>;
 253                                 atmel,can-isoc;
 254                         };
 255                 };
 256
 257                 usb1: ohci@00500000 {
 258                         compatible = "atmel,at91rm9200-ohci", "usb-ohci";
 259                         reg = <0x00500000 0x100000>;
 260                         interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
 261                         clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
 262                                  <&uhpck>;
 263                         clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
 264                         status = "disabled";
 265                 };
 266
 267                 usb2: ehci@00600000 {
 268                         compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
 269                         reg = <0x00600000 0x100000>;
 270                         interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
 271                         clocks = <&utmi>, <&uhphs_clk>, <&uhpck>;
 272                         clock-names = "usb_clk", "ehci_clk", "uhpck";
 273                         status = "disabled";
 274                 };
 275
 276                 L2: cache-controller@00a00000 {
 277                         compatible = "arm,pl310-cache";
 278                         reg = <0x00a00000 0x1000>;
 279                         interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
 280                         cache-unified;
 281                         cache-level = <2>;
 282                 };
 283
 284                 nand0: nand@80000000 {
 285                         compatible = "atmel,sama5d4-nand", "atmel,at91rm9200-nand";
 286                         #address-cells = <1>;
 287                         #size-cells = <1>;
 288                         ranges;
 289                         reg = < 0x80000000 0x08000000   /* EBI CS3 */
 290                                 0xfc05c070 0x00000490   /* SMC PMECC regs */
 291                                 0xfc05c500 0x00000100   /* SMC PMECC Error Location regs */
 292                                 >;
 293                         interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
 294                         atmel,nand-addr-offset = <21>;
 295                         atmel,nand-cmd-offset = <22>;
 296                         atmel,nand-has-dma;
 297                         pinctrl-names = "default";
 298                         pinctrl-0 = <&pinctrl_nand>;
 299                         status = "disabled";
 300
 301                         nfc@90000000 {
 302                                 compatible = "atmel,sama5d3-nfc";
 303                                 #address-cells = <1>;
 304                                 #size-cells = <1>;
 305                                 reg = <
 306                                         0x90000000 0x08000000   /* NFC Command Registers */
 307                                         0xfc05c000 0x00000070   /* NFC HSMC regs */
 308                                         0x00100000 0x00100000   /* NFC SRAM banks */
 309                                          >;
 310                                 clocks = <&hsmc_clk>;
 311                                 atmel,write-by-sram;
 312                         };
 313                 };
 314
 315                 apb {
 316                         compatible = "simple-bus";
 317                         #address-cells = <1>;
 318                         #size-cells = <1>;
 319                         ranges;
 320
 321                         hlcdc: hlcdc@f0000000 {
 322                                 compatible = "atmel,sama5d4-hlcdc";
 323                                 reg = <0xf0000000 0x4000>;
 324                                 interrupts = <51 IRQ_TYPE_LEVEL_HIGH 0>;
 325                                 clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
 326                                 clock-names = "periph_clk","sys_clk", "slow_clk";
 327                                 status = "disabled";
 328
 329                                 hlcdc-display-controller {
 330                                         compatible = "atmel,hlcdc-display-controller";
 331                                         #address-cells = <1>;
 332                                         #size-cells = <0>;
 333
 334                                         port@0 {
 335                                                 #address-cells = <1>;
 336                                                 #size-cells = <0>;
 337                                                 reg = <0>;
 338                                         };
 339                                 };
 340
 341                                 hlcdc_pwm: hlcdc-pwm {
 342                                         compatible = "atmel,hlcdc-pwm";
 343                                         pinctrl-names = "default";
 344                                         pinctrl-0 = <&pinctrl_lcd_pwm>;
 345                                         #pwm-cells = <3>;
 346                                 };
 347                         };
 348
 349                         dma1: dma-controller@f0004000 {
 350                                 compatible = "atmel,sama5d4-dma";
 351                                 reg = <0xf0004000 0x200>;
 352                                 interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>;
 353                                 #dma-cells = <1>;
 354                                 clocks = <&dma1_clk>;
 355                                 clock-names = "dma_clk";
 356                         };
 357
 358                         isi: isi@f0008000 {
 359                                 compatible = "atmel,at91sam9g45-isi";
 360                                 reg = <0xf0008000 0x4000>;
 361                                 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 5>;
 362                                 pinctrl-names = "default";
 363                                 pinctrl-0 = <&pinctrl_isi_data_0_7>;
 364                                 clocks = <&isi_clk>;
 365                                 clock-names = "isi_clk";
 366                                 status = "disabled";
 367                                 port {
 368                                         #address-cells = <1>;
 369                                         #size-cells = <0>;
 370                                 };
 371                         };
 372
 373                         ramc0: ramc@f0010000 {
 374                                 compatible = "atmel,sama5d3-ddramc";
 375                                 reg = <0xf0010000 0x200>;
 376                                 clocks = <&ddrck>, <&mpddr_clk>;
 377                                 clock-names = "ddrck", "mpddr";
 378                         };
 379
 380                         dma0: dma-controller@f0014000 {
 381                                 compatible = "atmel,sama5d4-dma";
 382                                 reg = <0xf0014000 0x200>;
 383                                 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>;
 384                                 #dma-cells = <1>;
 385                                 clocks = <&dma0_clk>;
 386                                 clock-names = "dma_clk";
 387                         };
 388
 389                         pmc: pmc@f0018000 {
 390                                 compatible = "atmel,sama5d3-pmc";
 391                                 reg = <0xf0018000 0x120>;
 392                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 393                                 interrupt-controller;
 394                                 #address-cells = <1>;
 395                                 #size-cells = <0>;
 396                                 #interrupt-cells = <1>;
 397
 398                                 main_rc_osc: main_rc_osc {
 399                                         compatible = "atmel,at91sam9x5-clk-main-rc-osc";
 400                                         #clock-cells = <0>;
 401                                         interrupt-parent = <&pmc>;
 402                                         interrupts = <AT91_PMC_MOSCRCS>;
 403                                         clock-frequency = <12000000>;
 404                                         clock-accuracy = <100000000>;
 405                                 };
 406
 407                                 main_osc: main_osc {
 408                                         compatible = "atmel,at91rm9200-clk-main-osc";
 409                                         #clock-cells = <0>;
 410                                         interrupt-parent = <&pmc>;
 411                                         interrupts = <AT91_PMC_MOSCS>;
 412                                         clocks = <&main_xtal>;
 413                                 };
 414
 415                                 main: mainck {
 416                                         compatible = "atmel,at91sam9x5-clk-main";
 417                                         #clock-cells = <0>;
 418                                         interrupt-parent = <&pmc>;
 419                                         interrupts = <AT91_PMC_MOSCSELS>;
 420                                         clocks = <&main_rc_osc &main_osc>;
 421                                 };
 422
 423                                 plla: pllack {
 424                                         compatible = "atmel,sama5d3-clk-pll";
 425                                         #clock-cells = <0>;
 426                                         interrupt-parent = <&pmc>;
 427                                         interrupts = <AT91_PMC_LOCKA>;
 428                                         clocks = <&main>;
 429                                         reg = <0>;
 430                                         atmel,clk-input-range = <12000000 12000000>;
 431                                         #atmel,pll-clk-output-range-cells = <4>;
 432                                         atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
 433                                 };
 434
 435                                 plladiv: plladivck {
 436                                         compatible = "atmel,at91sam9x5-clk-plldiv";
 437                                         #clock-cells = <0>;
 438                                         clocks = <&plla>;
 439                                 };
 440
 441                                 utmi: utmick {
 442                                         compatible = "atmel,at91sam9x5-clk-utmi";
 443                                         #clock-cells = <0>;
 444                                         interrupt-parent = <&pmc>;
 445                                         interrupts = <AT91_PMC_LOCKU>;
 446                                         clocks = <&main>;
 447                                 };
 448
 449                                 mck: masterck {
 450                                         compatible = "atmel,at91sam9x5-clk-master";
 451                                         #clock-cells = <0>;
 452                                         interrupt-parent = <&pmc>;
 453                                         interrupts = <AT91_PMC_MCKRDY>;
 454                                         clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
 455                                         atmel,clk-output-range = <125000000 177000000>;
 456                                         atmel,clk-divisors = <1 2 4 3>;
 457                                 };
 458
 459                                 h32ck: h32mxck {
 460                                         #clock-cells = <0>;
 461                                         compatible = "atmel,sama5d4-clk-h32mx";
 462                                         clocks = <&mck>;
 463                                 };
 464
 465                                 usb: usbck {
 466                                         compatible = "atmel,at91sam9x5-clk-usb";
 467                                         #clock-cells = <0>;
 468                                         clocks = <&plladiv>, <&utmi>;
 469                                 };
 470
 471                                 prog: progck {
 472                                         compatible = "atmel,at91sam9x5-clk-programmable";
 473                                         #address-cells = <1>;
 474                                         #size-cells = <0>;
 475                                         interrupt-parent = <&pmc>;
 476                                         clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
 477
 478                                         prog0: prog0 {
 479                                                 #clock-cells = <0>;
 480                                                 reg = <0>;
 481                                                 interrupts = <AT91_PMC_PCKRDY(0)>;
 482                                         };
 483
 484                                         prog1: prog1 {
 485                                                 #clock-cells = <0>;
 486                                                 reg = <1>;
 487                                                 interrupts = <AT91_PMC_PCKRDY(1)>;
 488                                         };
 489
 490                                         prog2: prog2 {
 491                                                 #clock-cells = <0>;
 492                                                 reg = <2>;
 493                                                 interrupts = <AT91_PMC_PCKRDY(2)>;
 494                                         };
 495                                 };
 496
 497                                 smd: smdclk {
 498                                         compatible = "atmel,at91sam9x5-clk-smd";
 499                                         #clock-cells = <0>;
 500                                         clocks = <&plladiv>, <&utmi>;
 501                                 };
 502
 503                                 systemck {
 504                                         compatible = "atmel,at91rm9200-clk-system";
 505                                         #address-cells = <1>;
 506                                         #size-cells = <0>;
 507
 508                                         ddrck: ddrck {
 509                                                 #clock-cells = <0>;
 510                                                 reg = <2>;
 511                                                 clocks = <&mck>;
 512                                         };
 513
 514                                         lcdck: lcdck {
 515                                                 #clock-cells = <0>;
 516                                                 reg = <3>;
 517                                                 clocks = <&mck>;
 518                                         };
 519
 520                                         smdck: smdck {
 521                                                 #clock-cells = <0>;
 522                                                 reg = <4>;
 523                                                 clocks = <&smd>;
 524                                         };
 525
 526                                         uhpck: uhpck {
 527                                                 #clock-cells = <0>;
 528                                                 reg = <6>;
 529                                                 clocks = <&usb>;
 530                                         };
 531
 532                                         udpck: udpck {
 533                                                 #clock-cells = <0>;
 534                                                 reg = <7>;
 535                                                 clocks = <&usb>;
 536                                         };
 537
 538                                         pck0: pck0 {
 539                                                 #clock-cells = <0>;
 540                                                 reg = <8>;
 541                                                 clocks = <&prog0>;
 542                                         };
 543
 544                                         pck1: pck1 {
 545                                                 #clock-cells = <0>;
 546                                                 reg = <9>;
 547                                                 clocks = <&prog1>;
 548                                         };
 549
 550                                         pck2: pck2 {
 551                                                 #clock-cells = <0>;
 552                                                 reg = <10>;
 553                                                 clocks = <&prog2>;
 554                                         };
 555                                 };
 556
 557                                 periph32ck {
 558                                         compatible = "atmel,at91sam9x5-clk-peripheral";
 559                                         #address-cells = <1>;
 560                                         #size-cells = <0>;
 561                                         clocks = <&h32ck>;
 562
 563                                         pioD_clk: pioD_clk {
 564                                                 #clock-cells = <0>;
 565                                                 reg = <5>;
 566                                         };
 567
 568                                         usart0_clk: usart0_clk {
 569                                                 #clock-cells = <0>;
 570                                                 reg = <6>;
 571                                         };
 572
 573                                         usart1_clk: usart1_clk {
 574                                                 #clock-cells = <0>;
 575                                                 reg = <7>;
 576                                         };
 577
 578                                         icm_clk: icm_clk {
 579                                                 #clock-cells = <0>;
 580                                                 reg = <9>;
 581                                         };
 582
 583                                         aes_clk: aes_clk {
 584                                                 #clock-cells = <0>;
 585                                                 reg = <12>;
 586                                         };
 587
 588                                         tdes_clk: tdes_clk {
 589                                                 #clock-cells = <0>;
 590                                                 reg = <14>;
 591                                         };
 592
 593                                         sha_clk: sha_clk {
 594                                                 #clock-cells = <0>;
 595                                                 reg = <15>;
 596                                         };
 597
 598                                         matrix1_clk: matrix1_clk {
 599                                                 #clock-cells = <0>;
 600                                                 reg = <17>;
 601                                         };
 602
 603                                         hsmc_clk: hsmc_clk {
 604                                                 #clock-cells = <0>;
 605                                                 reg = <22>;
 606                                         };
 607
 608                                         pioA_clk: pioA_clk {
 609                                                 #clock-cells = <0>;
 610                                                 reg = <23>;
 611                                         };
 612
 613                                         pioB_clk: pioB_clk {
 614                                                 #clock-cells = <0>;
 615                                                 reg = <24>;
 616                                         };
 617
 618                                         pioC_clk: pioC_clk {
 619                                                 #clock-cells = <0>;
 620                                                 reg = <25>;
 621                                         };
 622
 623                                         pioE_clk: pioE_clk {
 624                                                 #clock-cells = <0>;
 625                                                 reg = <26>;
 626                                         };
 627
 628                                         uart0_clk: uart0_clk {
 629                                                 #clock-cells = <0>;
 630                                                 reg = <27>;
 631                                         };
 632
 633                                         uart1_clk: uart1_clk {
 634                                                 #clock-cells = <0>;
 635                                                 reg = <28>;
 636                                         };
 637
 638                                         usart2_clk: usart2_clk {
 639                                                 #clock-cells = <0>;
 640                                                 reg = <29>;
 641                                         };
 642
 643                                         usart3_clk: usart3_clk {
 644                                                 #clock-cells = <0>;
 645                                                 reg = <30>;
 646                                         };
 647
 648                                         usart4_clk: usart4_clk {
 649                                                 #clock-cells = <0>;
 650                                                 reg = <31>;
 651                                         };
 652
 653                                         twi0_clk: twi0_clk {
 654                                                 reg = <32>;
 655                                                 #clock-cells = <0>;
 656                                         };
 657
 658                                         twi1_clk: twi1_clk {
 659                                                 #clock-cells = <0>;
 660                                                 reg = <33>;
 661                                         };
 662
 663                                         twi2_clk: twi2_clk {
 664                                                 #clock-cells = <0>;
 665                                                 reg = <34>;
 666                                         };
 667
 668                                         mci0_clk: mci0_clk {
 669                                                 #clock-cells = <0>;
 670                                                 reg = <35>;
 671                                         };
 672
 673                                         mci1_clk: mci1_clk {
 674                                                 #clock-cells = <0>;
 675                                                 reg = <36>;
 676                                         };
 677
 678                                         spi0_clk: spi0_clk {
 679                                                 #clock-cells = <0>;
 680                                                 reg = <37>;
 681                                         };
 682
 683                                         spi1_clk: spi1_clk {
 684                                                 #clock-cells = <0>;
 685                                                 reg = <38>;
 686                                         };
 687
 688                                         spi2_clk: spi2_clk {
 689                                                 #clock-cells = <0>;
 690                                                 reg = <39>;
 691                                         };
 692
 693                                         tcb0_clk: tcb0_clk {
 694                                                 #clock-cells = <0>;
 695                                                 reg = <40>;
 696                                         };
 697
 698                                         tcb1_clk: tcb1_clk {
 699                                                 #clock-cells = <0>;
 700                                                 reg = <41>;
 701                                         };
 702
 703                                         tcb2_clk: tcb2_clk {
 704                                                 #clock-cells = <0>;
 705                                                 reg = <42>;
 706                                         };
 707
 708                                         pwm_clk: pwm_clk {
 709                                                 #clock-cells = <0>;
 710                                                 reg = <43>;
 711                                         };
 712
 713                                         adc_clk: adc_clk {
 714                                                 #clock-cells = <0>;
 715                                                 reg = <44>;
 716                                         };
 717
 718                                         dbgu_clk: dbgu_clk {
 719                                                 #clock-cells = <0>;
 720                                                 reg = <45>;
 721                                         };
 722
 723                                         uhphs_clk: uhphs_clk {
 724                                                 #clock-cells = <0>;
 725                                                 reg = <46>;
 726                                         };
 727
 728                                         udphs_clk: udphs_clk {
 729                                                 #clock-cells = <0>;
 730                                                 reg = <47>;
 731                                         };
 732
 733                                         ssc0_clk: ssc0_clk {
 734                                                 #clock-cells = <0>;
 735                                                 reg = <48>;
 736                                         };
 737
 738                                         ssc1_clk: ssc1_clk {
 739                                                 #clock-cells = <0>;
 740                                                 reg = <49>;
 741                                         };
 742
 743                                         trng_clk: trng_clk {
 744                                                 #clock-cells = <0>;
 745                                                 reg = <53>;
 746                                         };
 747
 748                                         macb0_clk: macb0_clk {
 749                                                 #clock-cells = <0>;
 750                                                 reg = <54>;
 751                                         };
 752
 753                                         macb1_clk: macb1_clk {
 754                                                 #clock-cells = <0>;
 755                                                 reg = <55>;
 756                                         };
 757
 758                                         fuse_clk: fuse_clk {
 759                                                 #clock-cells = <0>;
 760                                                 reg = <57>;
 761                                         };
 762
 763                                         securam_clk: securam_clk {
 764                                                 #clock-cells = <0>;
 765                                                 reg = <59>;
 766                                         };
 767
 768                                         smd_clk: smd_clk {
 769                                                 #clock-cells = <0>;
 770                                                 reg = <61>;
 771                                         };
 772
 773                                         twi3_clk: twi3_clk {
 774                                                 #clock-cells = <0>;
 775                                                 reg = <62>;
 776                                         };
 777
 778                                         catb_clk: catb_clk {
 779                                                 #clock-cells = <0>;
 780                                                 reg = <63>;
 781                                         };
 782                                 };
 783
 784                                 periph64ck {
 785                                         compatible = "atmel,at91sam9x5-clk-peripheral";
 786                                         #address-cells = <1>;
 787                                         #size-cells = <0>;
 788                                         clocks = <&mck>;
 789
 790                                         dma0_clk: dma0_clk {
 791                                                 #clock-cells = <0>;
 792                                                 reg = <8>;
 793                                         };
 794
 795                                         cpkcc_clk: cpkcc_clk {
 796                                                 #clock-cells = <0>;
 797                                                 reg = <10>;
 798                                         };
 799
 800                                         aesb_clk: aesb_clk {
 801                                                 #clock-cells = <0>;
 802                                                 reg = <13>;
 803                                         };
 804
 805                                         mpddr_clk: mpddr_clk {
 806                                                 #clock-cells = <0>;
 807                                                 reg = <16>;
 808                                         };
 809
 810                                         matrix0_clk: matrix0_clk {
 811                                                 #clock-cells = <0>;
 812                                                 reg = <18>;
 813                                         };
 814
 815                                         vdec_clk: vdec_clk {
 816                                                 #clock-cells = <0>;
 817                                                 reg = <19>;
 818                                         };
 819
 820                                         dma1_clk: dma1_clk {
 821                                                 #clock-cells = <0>;
 822                                                 reg = <50>;
 823                                         };
 824
 825                                         lcdc_clk: lcdc_clk {
 826                                                 #clock-cells = <0>;
 827                                                 reg = <51>;
 828                                         };
 829
 830                                         isi_clk: isi_clk {
 831                                                 #clock-cells = <0>;
 832                                                 reg = <52>;
 833                                         };
 834                                 };
 835                         };
 836
 837                         mmc0: mmc@f8000000 {
 838                                 compatible = "atmel,hsmci";
 839                                 reg = <0xf8000000 0x600>;
 840                                 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
 841                                 dmas = <&dma1
 842                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 843                                         | AT91_XDMAC_DT_PERID(0))>;
 844                                 dma-names = "rxtx";
 845                                 pinctrl-names = "default";
 846                                 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
 847                                 status = "disabled";
 848                                 #address-cells = <1>;
 849                                 #size-cells = <0>;
 850                                 clocks = <&mci0_clk>;
 851                                 clock-names = "mci_clk";
 852                         };
 853
 854                         uart0: serial@f8004000 {
 855                                 compatible = "atmel,at91sam9260-usart";
 856                                 reg = <0xf8004000 0x100>;
 857                                 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 5>;
 858                                 dmas = <&dma1
 859                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 860                                         | AT91_XDMAC_DT_PERID(22))>,
 861                                        <&dma1
 862                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 863                                         | AT91_XDMAC_DT_PERID(23))>;
 864                                 dma-names = "tx", "rx";
 865                                 pinctrl-names = "default";
 866                                 pinctrl-0 = <&pinctrl_uart0>;
 867                                 clocks = <&uart0_clk>;
 868                                 clock-names = "usart";
 869                                 status = "disabled";
 870                         };
 871
 872                         ssc0: ssc@f8008000 {
 873                                 compatible = "atmel,at91sam9g45-ssc";
 874                                 reg = <0xf8008000 0x4000>;
 875                                 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 0>;
 876                                 pinctrl-names = "default";
 877                                 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
 878                                 dmas = <&dma1
 879                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 880                                         | AT91_XDMAC_DT_PERID(26))>,
 881                                        <&dma1
 882                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 883                                         | AT91_XDMAC_DT_PERID(27))>;
 884                                 dma-names = "tx", "rx";
 885                                 clocks = <&ssc0_clk>;
 886                                 clock-names = "pclk";
 887                                 status = "disabled";
 888                         };
 889
 890                         pwm0: pwm@f800c000 {
 891                                 compatible = "atmel,sama5d3-pwm";
 892                                 reg = <0xf800c000 0x300>;
 893                                 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
 894                                 #pwm-cells = <3>;
 895                                 clocks = <&pwm_clk>;
 896                                 status = "disabled";
 897                         };
 898
 899                         spi0: spi@f8010000 {
 900                                 #address-cells = <1>;
 901                                 #size-cells = <0>;
 902                                 compatible = "atmel,at91rm9200-spi";
 903                                 reg = <0xf8010000 0x100>;
 904                                 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
 905                                 dmas = <&dma1
 906                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 907                                         | AT91_XDMAC_DT_PERID(10))>,
 908                                        <&dma1
 909                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 910                                         | AT91_XDMAC_DT_PERID(11))>;
 911                                 dma-names = "tx", "rx";
 912                                 pinctrl-names = "default";
 913                                 pinctrl-0 = <&pinctrl_spi0>;
 914                                 clocks = <&spi0_clk>;
 915                                 clock-names = "spi_clk";
 916                                 status = "disabled";
 917                         };
 918
 919                         i2c0: i2c@f8014000 {
 920                                 compatible = "atmel,at91sam9x5-i2c";
 921                                 reg = <0xf8014000 0x4000>;
 922                                 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
 923                                 dmas = <&dma1
 924                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 925                                         | AT91_XDMAC_DT_PERID(2))>,
 926                                        <&dma1
 927                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 928                                         | AT91_XDMAC_DT_PERID(3))>;
 929                                 dma-names = "tx", "rx";
 930                                 pinctrl-names = "default";
 931                                 pinctrl-0 = <&pinctrl_i2c0>;
 932                                 #address-cells = <1>;
 933                                 #size-cells = <0>;
 934                                 clocks = <&twi0_clk>;
 935                                 status = "disabled";
 936                         };
 937
 938                         i2c1: i2c@f8018000 {
 939                                 compatible = "atmel,at91sam9x5-i2c";
 940                                 reg = <0xf8018000 0x4000>;
 941                                 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 6>;
 942                                 dmas = <&dma1
 943                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
 944                                         AT91_XDMAC_DT_PERID(4)>,
 945                                        <&dma1
 946                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
 947                                         AT91_XDMAC_DT_PERID(5)>;
 948                                 dma-names = "tx", "rx";
 949                                 pinctrl-names = "default";
 950                                 pinctrl-0 = <&pinctrl_i2c1>;
 951                                 #address-cells = <1>;
 952                                 #size-cells = <0>;
 953                                 clocks = <&twi1_clk>;
 954                                 status = "disabled";
 955                         };
 956
 957                         tcb0: timer@f801c000 {
 958                                 compatible = "atmel,at91sam9x5-tcb";
 959                                 reg = <0xf801c000 0x100>;
 960                                 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
 961                                 clocks = <&tcb0_clk>;
 962                                 clock-names = "t0_clk";
 963                         };
 964
 965                         macb0: ethernet@f8020000 {
 966                                 compatible = "atmel,sama5d4-gem";
 967                                 reg = <0xf8020000 0x100>;
 968                                 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
 969                                 pinctrl-names = "default";
 970                                 pinctrl-0 = <&pinctrl_macb0_rmii>;
 971                                 #address-cells = <1>;
 972                                 #size-cells = <0>;
 973                                 clocks = <&macb0_clk>, <&macb0_clk>;
 974                                 clock-names = "hclk", "pclk";
 975                                 status = "disabled";
 976                         };
 977
 978                         i2c2: i2c@f8024000 {
 979                                 compatible = "atmel,at91sam9x5-i2c";
 980                                 reg = <0xf8024000 0x4000>;
 981                                 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
 982                                 dmas = <&dma1
 983                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 984                                         | AT91_XDMAC_DT_PERID(6))>,
 985                                        <&dma1
 986                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
 987                                         | AT91_XDMAC_DT_PERID(7))>;
 988                                 dma-names = "tx", "rx";
 989                                 pinctrl-names = "default";
 990                                 pinctrl-0 = <&pinctrl_i2c2>;
 991                                 #address-cells = <1>;
 992                                 #size-cells = <0>;
 993                                 clocks = <&twi2_clk>;
 994                                 status = "disabled";
 995                         };
 996
 997                         sfr: sfr@f8028000 {
 998                                 compatible = "atmel,sama5d4-sfr", "syscon";
 999                                 reg = <0xf8028000 0x60>;
1000                         };
1001
1002                         usart0: serial@f802c000 {
1003                                 compatible = "atmel,at91sam9260-usart";
1004                                 reg = <0xf802c000 0x100>;
1005                                 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
1006                                 dmas = <&dma0
1007                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1008                                         | AT91_XDMAC_DT_PERID(36))>,
1009                                        <&dma0
1010                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1011                                         | AT91_XDMAC_DT_PERID(37))>;
1012                                 dma-names = "tx", "rx";
1013                                 pinctrl-names = "default";
1014                                 pinctrl-0 = <&pinctrl_usart0 &pinctrl_usart0_rts &pinctrl_usart0_cts>;
1015                                 clocks = <&usart0_clk>;
1016                                 clock-names = "usart";
1017                                 status = "disabled";
1018                         };
1019
1020                         usart1: serial@f8030000 {
1021                                 compatible = "atmel,at91sam9260-usart";
1022                                 reg = <0xf8030000 0x100>;
1023                                 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
1024                                 dmas = <&dma0
1025                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1026                                         | AT91_XDMAC_DT_PERID(38))>,
1027                                        <&dma0
1028                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1029                                         | AT91_XDMAC_DT_PERID(39))>;
1030                                 dma-names = "tx", "rx";
1031                                 pinctrl-names = "default";
1032                                 pinctrl-0 = <&pinctrl_usart1 &pinctrl_usart1_rts &pinctrl_usart1_cts>;
1033                                 clocks = <&usart1_clk>;
1034                                 clock-names = "usart";
1035                                 status = "disabled";
1036                         };
1037
1038                         mmc1: mmc@fc000000 {
1039                                 compatible = "atmel,hsmci";
1040                                 reg = <0xfc000000 0x600>;
1041                                 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
1042                                 dmas = <&dma1
1043                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1044                                         | AT91_XDMAC_DT_PERID(1))>;
1045                                 dma-names = "rxtx";
1046                                 pinctrl-names = "default";
1047                                 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
1048                                 status = "disabled";
1049                                 #address-cells = <1>;
1050                                 #size-cells = <0>;
1051                                 clocks = <&mci1_clk>;
1052                                 clock-names = "mci_clk";
1053                         };
1054
1055                         uart1: serial@fc004000 {
1056                                 compatible = "atmel,at91sam9260-usart";
1057                                 reg = <0xfc004000 0x100>;
1058                                 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>;
1059                                 dmas = <&dma1
1060                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1061                                         | AT91_XDMAC_DT_PERID(24))>,
1062                                        <&dma1
1063                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1064                                         | AT91_XDMAC_DT_PERID(25))>;
1065                                 dma-names = "tx", "rx";
1066                                 pinctrl-names = "default";
1067                                 pinctrl-0 = <&pinctrl_uart1>;
1068                                 clocks = <&uart1_clk>;
1069                                 clock-names = "usart";
1070                                 status = "disabled";
1071                         };
1072
1073                         usart2: serial@fc008000 {
1074                                 compatible = "atmel,at91sam9260-usart";
1075                                 reg = <0xfc008000 0x100>;
1076                                 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
1077                                 dmas = <&dma1
1078                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1079                                         | AT91_XDMAC_DT_PERID(16))>,
1080                                        <&dma1
1081                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1082                                         | AT91_XDMAC_DT_PERID(17))>;
1083                                 dma-names = "tx", "rx";
1084                                 pinctrl-names = "default";
1085                                 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
1086                                 clocks = <&usart2_clk>;
1087                                 clock-names = "usart";
1088                                 status = "disabled";
1089                         };
1090
1091                         usart3: serial@fc00c000 {
1092                                 compatible = "atmel,at91sam9260-usart";
1093                                 reg = <0xfc00c000 0x100>;
1094                                 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
1095                                 dmas = <&dma1
1096                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1097                                         | AT91_XDMAC_DT_PERID(18))>,
1098                                        <&dma1
1099                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1100                                         | AT91_XDMAC_DT_PERID(19))>;
1101                                 dma-names = "tx", "rx";
1102                                 pinctrl-names = "default";
1103                                 pinctrl-0 = <&pinctrl_usart3>;
1104                                 clocks = <&usart3_clk>;
1105                                 clock-names = "usart";
1106                                 status = "disabled";
1107                         };
1108
1109                         usart4: serial@fc010000 {
1110                                 compatible = "atmel,at91sam9260-usart";
1111                                 reg = <0xfc010000 0x100>;
1112                                 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
1113                                 dmas = <&dma1
1114                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1115                                         | AT91_XDMAC_DT_PERID(20))>,
1116                                        <&dma1
1117                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1118                                         | AT91_XDMAC_DT_PERID(21))>;
1119                                 dma-names = "tx", "rx";
1120                                 pinctrl-names = "default";
1121                                 pinctrl-0 = <&pinctrl_usart4>;
1122                                 clocks = <&usart4_clk>;
1123                                 clock-names = "usart";
1124                                 status = "disabled";
1125                         };
1126
1127                         ssc1: ssc@fc014000 {
1128                                 compatible = "atmel,at91sam9g45-ssc";
1129                                 reg = <0xfc014000 0x4000>;
1130                                 interrupts = <49 IRQ_TYPE_LEVEL_HIGH 0>;
1131                                 pinctrl-names = "default";
1132                                 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
1133                                 dmas = <&dma1
1134                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1135                                         | AT91_XDMAC_DT_PERID(28))>,
1136                                        <&dma1
1137                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1138                                         | AT91_XDMAC_DT_PERID(29))>;
1139                                 dma-names = "tx", "rx";
1140                                 clocks = <&ssc1_clk>;
1141                                 clock-names = "pclk";
1142                                 status = "disabled";
1143                         };
1144
1145                         spi1: spi@fc018000 {
1146                                 #address-cells = <1>;
1147                                 #size-cells = <0>;
1148                                 compatible = "atmel,at91rm9200-spi";
1149                                 reg = <0xfc018000 0x100>;
1150                                 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 3>;
1151                                 dmas = <&dma1
1152                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1153                                         | AT91_XDMAC_DT_PERID(12))>,
1154                                        <&dma1
1155                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1156                                         | AT91_XDMAC_DT_PERID(13))>;
1157                                 dma-names = "tx", "rx";
1158                                 pinctrl-names = "default";
1159                                 pinctrl-0 = <&pinctrl_spi1>;
1160                                 clocks = <&spi1_clk>;
1161                                 clock-names = "spi_clk";
1162                                 status = "disabled";
1163                         };
1164
1165                         spi2: spi@fc01c000 {
1166                                 #address-cells = <1>;
1167                                 #size-cells = <0>;
1168                                 compatible = "atmel,at91rm9200-spi";
1169                                 reg = <0xfc01c000 0x100>;
1170                                 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 3>;
1171                                 dmas = <&dma1
1172                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1173                                         | AT91_XDMAC_DT_PERID(14))>,
1174                                        <&dma1
1175                                         (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1176                                         | AT91_XDMAC_DT_PERID(15))>;
1177                                 dma-names = "tx", "rx";
1178                                 pinctrl-names = "default";
1179                                 pinctrl-0 = <&pinctrl_spi2>;
1180                                 clocks = <&spi2_clk>;
1181                                 clock-names = "spi_clk";
1182                                 status = "disabled";
1183                         };
1184
1185                         tcb1: timer@fc020000 {
1186                                 compatible = "atmel,at91sam9x5-tcb";
1187                                 reg = <0xfc020000 0x100>;
1188                                 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
1189                                 clocks = <&tcb1_clk>;
1190                                 clock-names = "t0_clk";
1191                         };
1192
1193                         adc0: adc@fc034000 {
1194                                 compatible = "atmel,at91sam9x5-adc";
1195                                 reg = <0xfc034000 0x100>;
1196                                 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
1197                                 pinctrl-names = "default";
1198                                 pinctrl-0 = <
1199                                         /* external trigger is conflict with USBA_VBUS */
1200                                         &pinctrl_adc0_ad0
1201                                         &pinctrl_adc0_ad1
1202                                         &pinctrl_adc0_ad2
1203                                         &pinctrl_adc0_ad3
1204                                         &pinctrl_adc0_ad4
1205                                         >;
1206                                 clocks = <&adc_clk>,
1207                                          <&adc_op_clk>;
1208                                 clock-names = "adc_clk", "adc_op_clk";
1209                                 atmel,adc-channels-used = <0x01f>;
1210                                 atmel,adc-startup-time = <40>;
1211                                 atmel,adc-use-external;
1212                                 atmel,adc-vref = <3000>;
1213                                 atmel,adc-res = <8 10>;
1214                                 atmel,adc-sample-hold-time = <11>;
1215                                 atmel,adc-res-names = "lowres", "highres";
1216                                 atmel,adc-ts-pressure-threshold = <10000>;
1217                                 status = "disabled";
1218
1219                                 trigger@0 {
1220                                         trigger-name = "external-rising";
1221                                         trigger-value = <0x1>;
1222                                         trigger-external;
1223                                 };
1224                                 trigger@1 {
1225                                         trigger-name = "external-falling";
1226                                         trigger-value = <0x2>;
1227                                         trigger-external;
1228                                 };
1229                                 trigger@2 {
1230                                         trigger-name = "external-any";
1231                                         trigger-value = <0x3>;
1232                                         trigger-external;
1233                                 };
1234                                 trigger@3 {
1235                                         trigger-name = "continuous";
1236                                         trigger-value = <0x6>;
1237                                 };
1238                         };
1239
1240                         aes@fc044000 {
1241                                 compatible = "atmel,at91sam9g46-aes";
1242                                 reg = <0xfc044000 0x100>;
1243                                 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
1244                                 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
1245                                         AT91_XDMAC_DT_PERID(41)>,
1246                                        <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
1247                                         AT91_XDMAC_DT_PERID(40)>;
1248                                 dma-names = "tx", "rx";
1249                                 clocks = <&aes_clk>;
1250                                 clock-names = "aes_clk";
1251                                 status = "disabled";
1252                         };
1253
1254                         tdes@fc04c000 {
1255                                 compatible = "atmel,at91sam9g46-tdes";
1256                                 reg = <0xfc04c000 0x100>;
1257                                 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 0>;
1258                                 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
1259                                         AT91_XDMAC_DT_PERID(42)>,
1260                                        <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
1261                                         AT91_XDMAC_DT_PERID(43)>;
1262                                 dma-names = "tx", "rx";
1263                                 clocks = <&tdes_clk>;
1264                                 clock-names = "tdes_clk";
1265                                 status = "disabled";
1266                         };
1267
1268                         sha@fc050000 {
1269                                 compatible = "atmel,at91sam9g46-sha";
1270                                 reg = <0xfc050000 0x100>;
1271                                 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 0>;
1272                                 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1))
1273                                         AT91_XDMAC_DT_PERID(44)>;
1274                                 dma-names = "tx";
1275                                 clocks = <&sha_clk>;
1276                                 clock-names = "sha_clk";
1277                                 status = "disabled";
1278                         };
1279
1280                         rstc@fc068600 {
1281                                 compatible = "atmel,at91sam9g45-rstc";
1282                                 reg = <0xfc068600 0x10>;
1283                         };
1284
1285                         shdwc@fc068610 {
1286                                 compatible = "atmel,at91sam9x5-shdwc";
1287                                 reg = <0xfc068610 0x10>;
1288                         };
1289
1290                         pit: timer@fc068630 {
1291                                 compatible = "atmel,at91sam9260-pit";
1292                                 reg = <0xfc068630 0x10>;
1293                                 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1294                                 clocks = <&h32ck>;
1295                         };
1296
1297                         watchdog@fc068640 {
1298                                 compatible = "atmel,at91sam9260-wdt";
1299                                 reg = <0xfc068640 0x10>;
1300                                 status = "disabled";
1301                         };
1302
1303                         sckc@fc068650 {
1304                                 compatible = "atmel,at91sam9x5-sckc";
1305                                 reg = <0xfc068650 0x4>;
1306
1307                                 slow_rc_osc: slow_rc_osc {
1308                                         compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1309                                         #clock-cells = <0>;
1310                                         clock-frequency = <32768>;
1311                                         clock-accuracy = <250000000>;
1312                                         atmel,startup-time-usec = <75>;
1313                                 };
1314
1315                                 slow_osc: slow_osc {
1316                                         compatible = "atmel,at91sam9x5-clk-slow-osc";
1317                                         #clock-cells = <0>;
1318                                         clocks = <&slow_xtal>;
1319                                         atmel,startup-time-usec = <1200000>;
1320                                 };
1321
1322                                 clk32k: slowck {
1323                                         compatible = "atmel,at91sam9x5-clk-slow";
1324                                         #clock-cells = <0>;
1325                                         clocks = <&slow_rc_osc &slow_osc>;
1326                                 };
1327                         };
1328
1329                         rtc@fc0686b0 {
1330                                 compatible = "atmel,at91rm9200-rtc";
1331                                 reg = <0xfc0686b0 0x30>;
1332                                 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1333                         };
1334
1335                         dbgu: serial@fc069000 {
1336                                 compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
1337                                 reg = <0xfc069000 0x200>;
1338                                 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
1339                                 pinctrl-names = "default";
1340                                 pinctrl-0 = <&pinctrl_dbgu>;
1341                                 clocks = <&dbgu_clk>;
1342                                 clock-names = "usart";
1343                                 status = "disabled";
1344                         };
1345
1346
1347                         pinctrl@fc06a000 {
1348                                 #address-cells = <1>;
1349                                 #size-cells = <1>;
1350                                 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
1351                                 ranges = <0xfc068000 0xfc068000 0x100
1352                                           0xfc06a000 0xfc06a000 0x4000>;
1353                                 /* WARNING: revisit as pin spec has changed */
1354                                 atmel,mux-mask = <
1355                                         /*   A          B          C  */
1356                                         0xffffffff 0x3ffcfe7c 0x1c010101        /* pioA */
1357                                         0x7fffffff 0xfffccc3a 0x3f00cc3a        /* pioB */
1358                                         0xffffffff 0x3ff83fff 0xff00ffff        /* pioC */
1359                                         0x00000000 0x00000000 0x00000000        /* pioD */
1360                                         0xffffffff 0x7fffffff 0x76fff1bf        /* pioE */
1361                                         >;
1362
1363                                 pioA: gpio@fc06a000 {
1364                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1365                                         reg = <0xfc06a000 0x100>;
1366                                         interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
1367                                         #gpio-cells = <2>;
1368                                         gpio-controller;
1369                                         interrupt-controller;
1370                                         #interrupt-cells = <2>;
1371                                         clocks = <&pioA_clk>;
1372                                 };
1373
1374                                 pioB: gpio@fc06b000 {
1375                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1376                                         reg = <0xfc06b000 0x100>;
1377                                         interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
1378                                         #gpio-cells = <2>;
1379                                         gpio-controller;
1380                                         interrupt-controller;
1381                                         #interrupt-cells = <2>;
1382                                         clocks = <&pioB_clk>;
1383                                 };
1384
1385                                 pioC: gpio@fc06c000 {
1386                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1387                                         reg = <0xfc06c000 0x100>;
1388                                         interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
1389                                         #gpio-cells = <2>;
1390                                         gpio-controller;
1391                                         interrupt-controller;
1392                                         #interrupt-cells = <2>;
1393                                         clocks = <&pioC_clk>;
1394                                 };
1395
1396                                 pioD: gpio@fc068000 {
1397                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1398                                         reg = <0xfc068000 0x100>;
1399                                         interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
1400                                         #gpio-cells = <2>;
1401                                         gpio-controller;
1402                                         interrupt-controller;
1403                                         #interrupt-cells = <2>;
1404                                         clocks = <&pioD_clk>;
1405                                         status = "disabled";
1406                                 };
1407
1408                                 pioE: gpio@fc06d000 {
1409                                         compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1410                                         reg = <0xfc06d000 0x100>;
1411                                         interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
1412                                         #gpio-cells = <2>;
1413                                         gpio-controller;
1414                                         interrupt-controller;
1415                                         #interrupt-cells = <2>;
1416                                         clocks = <&pioE_clk>;
1417                                 };
1418
1419                                 /* pinctrl pin settings */
1420                                 adc0 {
1421                                         pinctrl_adc0_adtrg: adc0_adtrg {
1422                                                 atmel,pins =
1423                                                         <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */
1424                                         };
1425                                         pinctrl_adc0_ad0: adc0_ad0 {
1426                                                 atmel,pins =
1427                                                         <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1428                                         };
1429                                         pinctrl_adc0_ad1: adc0_ad1 {
1430                                                 atmel,pins =
1431                                                         <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1432                                         };
1433                                         pinctrl_adc0_ad2: adc0_ad2 {
1434                                                 atmel,pins =
1435                                                         <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1436                                         };
1437                                         pinctrl_adc0_ad3: adc0_ad3 {
1438                                                 atmel,pins =
1439                                                         <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1440                                         };
1441                                         pinctrl_adc0_ad4: adc0_ad4 {
1442                                                 atmel,pins =
1443                                                         <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1444                                         };
1445                                 };
1446
1447                                 dbgu {
1448                                         pinctrl_dbgu: dbgu-0 {
1449                                                 atmel,pins =
1450                                                         <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>,     /* conflicts with D14 and TDI */
1451                                                         <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;  /* conflicts with D15 and TDO */
1452                                         };
1453                                 };
1454
1455                                 i2c0 {
1456                                         pinctrl_i2c0: i2c0-0 {
1457                                                 atmel,pins =
1458                                                         <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
1459                                                          AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1460                                         };
1461                                 };
1462
1463                                 i2c1 {
1464                                         pinctrl_i2c1: i2c1-0 {
1465                                                 atmel,pins =
1466                                                         <AT91_PIOE 29 AT91_PERIPH_C AT91_PINCTRL_NONE   /* TWD1, conflicts with UART0 RX and DIBP */
1467                                                          AT91_PIOE 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* TWCK1, conflicts with UART0 TX and DIBN */
1468                                         };
1469                                 };
1470
1471                                 i2c2 {
1472                                         pinctrl_i2c2: i2c2-0 {
1473                                                 atmel,pins =
1474                                                         <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* TWD2, conflicts with RD0 and PWML1 */
1475                                                          AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
1476                                         };
1477                                 };
1478
1479                                 isi {
1480                                         pinctrl_isi_data_0_7: isi-0-data-0-7 {
1481                                                 atmel,pins =
1482                                                         <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D0 */
1483                                                          AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D1 */
1484                                                          AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D2 */
1485                                                          AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D3 */
1486                                                          AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D4 */
1487                                                          AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D5 */
1488                                                          AT91_PIOC 25 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D6 */
1489                                                          AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE   /* ISI_D7 */
1490                                                          AT91_PIOB  1 AT91_PERIPH_C AT91_PINCTRL_NONE   /* ISI_PCK, conflict with G0_RXCK */
1491                                                          AT91_PIOB  3 AT91_PERIPH_C AT91_PINCTRL_NONE   /* ISI_VSYNC */
1492                                                          AT91_PIOB  4 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* ISI_HSYNC */
1493                                         };
1494                                         pinctrl_isi_data_8_9: isi-0-data-8-9 {
1495                                                 atmel,pins =
1496                                                         <AT91_PIOC 0 AT91_PERIPH_C AT91_PINCTRL_NONE    /* ISI_D8, conflicts with SPI0_MISO, PWMH2 */
1497                                                          AT91_PIOC 1 AT91_PERIPH_C AT91_PINCTRL_NONE>;  /* ISI_D9, conflicts with SPI0_MOSI, PWML2 */
1498                                         };
1499                                         pinctrl_isi_data_10_11: isi-0-data-10-11 {
1500                                                 atmel,pins =
1501                                                         <AT91_PIOC 2 AT91_PERIPH_C AT91_PINCTRL_NONE    /* ISI_D10, conflicts with SPI0_SPCK, PWMH3 */
1502                                                          AT91_PIOC 3 AT91_PERIPH_C AT91_PINCTRL_NONE>;  /* ISI_D11, conflicts with SPI0_NPCS0, PWML3 */
1503                                         };
1504                                 };
1505
1506                                 lcd {
1507                                         pinctrl_lcd_base: lcd-base-0 {
1508                                                 atmel,pins =
1509                                                         <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDVSYNC */
1510                                                          AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDHSYNC */
1511                                                          AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDDEN */
1512                                                          AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDPCK */
1513                                         };
1514                                         pinctrl_lcd_pwm: lcd-pwm-0 {
1515                                                 atmel,pins = <AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_NONE>;    /* LCDPWM */
1516                                         };
1517                                         pinctrl_lcd_rgb444: lcd-rgb-0 {
1518                                                 atmel,pins =
1519                                                         <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
1520                                                          AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
1521                                                          AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
1522                                                          AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
1523                                                          AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
1524                                                          AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
1525                                                          AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
1526                                                          AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
1527                                                          AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
1528                                                          AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
1529                                                          AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
1530                                                          AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD11 pin */
1531                                         };
1532                                         pinctrl_lcd_rgb565: lcd-rgb-1 {
1533                                                 atmel,pins =
1534                                                         <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
1535                                                          AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
1536                                                          AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
1537                                                          AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
1538                                                          AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
1539                                                          AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
1540                                                          AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
1541                                                          AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
1542                                                          AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
1543                                                          AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
1544                                                          AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
1545                                                          AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
1546                                                          AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
1547                                                          AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
1548                                                          AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
1549                                                          AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD15 pin */
1550                                         };
1551                                         pinctrl_lcd_rgb666: lcd-rgb-2 {
1552                                                 atmel,pins =
1553                                                         <AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
1554                                                          AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
1555                                                          AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
1556                                                          AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
1557                                                          AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
1558                                                          AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
1559                                                          AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
1560                                                          AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
1561                                                          AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
1562                                                          AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
1563                                                          AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
1564                                                          AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD15 pin */
1565                                                          AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD18 pin */
1566                                                          AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD19 pin */
1567                                                          AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD20 pin */
1568                                                          AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD21 pin */
1569                                                          AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD22 pin */
1570                                                          AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1571                                         };
1572                                         pinctrl_lcd_rgb777: lcd-rgb-3 {
1573                                                 atmel,pins =
1574                                                          /* LCDDAT0 conflicts with TMS */
1575                                                         <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
1576                                                          AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
1577                                                          AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
1578                                                          AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
1579                                                          AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
1580                                                          AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
1581                                                          AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
1582                                                          /* LCDDAT8 conflicts with TCK */
1583                                                          AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
1584                                                          AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
1585                                                          AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
1586                                                          AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
1587                                                          AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
1588                                                          AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
1589                                                          AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD15 pin */
1590                                                          /* LCDDAT16 conflicts with NTRST */
1591                                                          AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD17 pin */
1592                                                          AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD18 pin */
1593                                                          AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD19 pin */
1594                                                          AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD20 pin */
1595                                                          AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD21 pin */
1596                                                          AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD22 pin */
1597                                                          AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1598                                         };
1599                                         pinctrl_lcd_rgb888: lcd-rgb-4 {
1600                                                 atmel,pins =
1601                                                         <AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD0 pin */
1602                                                          AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD1 pin */
1603                                                          AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD2 pin */
1604                                                          AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD3 pin */
1605                                                          AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD4 pin */
1606                                                          AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD5 pin */
1607                                                          AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD6 pin */
1608                                                          AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD7 pin */
1609                                                          AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD8 pin */
1610                                                          AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* LCDD9 pin */
1611                                                          AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD10 pin */
1612                                                          AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD11 pin */
1613                                                          AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD12 pin */
1614                                                          AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD13 pin */
1615                                                          AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD14 pin */
1616                                                          AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD15 pin */
1617                                                          AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD16 pin */
1618                                                          AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD17 pin */
1619                                                          AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD18 pin */
1620                                                          AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD19 pin */
1621                                                          AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD20 pin */
1622                                                          AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD21 pin */
1623                                                          AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_NONE   /* LCDD22 pin */
1624                                                          AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* LCDD23 pin */
1625                                         };
1626                                 };
1627
1628                                 macb0 {
1629                                         pinctrl_macb0_rmii: macb0_rmii-0 {
1630                                                 atmel,pins =
1631                                                         <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_TX0 */
1632                                                          AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_TX1 */
1633                                                          AT91_PIOB  8 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_RX0 */
1634                                                          AT91_PIOB  9 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_RX1 */
1635                                                          AT91_PIOB  6 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_RXDV */
1636                                                          AT91_PIOB  7 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_RXER */
1637                                                          AT91_PIOB  2 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_TXEN */
1638                                                          AT91_PIOB  0 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_TXCK */
1639                                                          AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_MDC */
1640                                                          AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE   /* G0_MDIO */
1641                                                         >;
1642                                         };
1643                                 };
1644
1645                                 mmc0 {
1646                                         pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
1647                                                 atmel,pins =
1648                                                         <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE    /* MCI0_CK, conflict with PCK1(ISI_MCK) */
1649                                                          AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDB, conflict with NAND_D0 */
1650                                                          AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB0, conflict with NAND_D1 */
1651                                                         >;
1652                                         };
1653                                         pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
1654                                                 atmel,pins =
1655                                                         <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB1, conflict with NAND_D2 */
1656                                                          AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB2, conflict with NAND_D3 */
1657                                                          AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB3, conflict with NAND_D4 */
1658                                                         >;
1659                                         };
1660                                 };
1661
1662                                 mmc1 {
1663                                         pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
1664                                                 atmel,pins =
1665                                                         <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE           /* MCI1_CK */
1666                                                          AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* MCI1_CDA */
1667                                                          AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* MCI1_DA0 */
1668                                                         >;
1669                                         };
1670                                         pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
1671                                                 atmel,pins =
1672                                                         <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* MCI1_DA1 */
1673                                                          AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* MCI1_DA2 */
1674                                                          AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* MCI1_DA3 */
1675                                                         >;
1676                                         };
1677                                 };
1678
1679                                 nand0 {
1680                                         pinctrl_nand: nand-0 {
1681                                                 atmel,pins =
1682                                                         <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC13 periph A Read Enable */
1683                                                          AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC14 periph A Write Enable */
1684
1685                                                          AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PC17 ALE */
1686                                                          AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PC18 CLE */
1687
1688                                                          AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PC15 NCS3/Chip Enable */
1689                                                          AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* PC16 NANDRDY */
1690                                                          AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC5 Data bit 0 */
1691                                                          AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC6 Data bit 1 */
1692                                                          AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC7 Data bit 2 */
1693                                                          AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC8 Data bit 3 */
1694                                                          AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE    /* PC9 Data bit 4 */
1695                                                          AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC10 Data bit 5 */
1696                                                          AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE   /* PC11 periph A Data bit 6 */
1697                                                          AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */
1698                                         };
1699                                 };
1700
1701                                 spi0 {
1702                                         pinctrl_spi0: spi0-0 {
1703                                                 atmel,pins =
1704                                                         <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE    /* SPI0_MISO */
1705                                                          AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE    /* SPI0_MOSI */
1706                                                          AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE    /* SPI0_SPCK */
1707                                                         >;
1708                                         };
1709                                 };
1710
1711                                 ssc0 {
1712                                         pinctrl_ssc0_tx: ssc0_tx {
1713                                                 atmel,pins =
1714                                                         <AT91_PIOB 27 AT91_PERIPH_B AT91_PINCTRL_NONE   /* TK0 */
1715                                                          AT91_PIOB 31 AT91_PERIPH_B AT91_PINCTRL_NONE   /* TF0 */
1716                                                          AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD0 */
1717                                         };
1718
1719                                         pinctrl_ssc0_rx: ssc0_rx {
1720                                                 atmel,pins =
1721                                                         <AT91_PIOB 26 AT91_PERIPH_B AT91_PINCTRL_NONE   /* RK0 */
1722                                                          AT91_PIOB 30 AT91_PERIPH_B AT91_PINCTRL_NONE   /* RF0 */
1723                                                          AT91_PIOB 29 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD0 */
1724                                         };
1725                                 };
1726
1727                                 ssc1 {
1728                                         pinctrl_ssc1_tx: ssc1_tx {
1729                                                 atmel,pins =
1730                                                         <AT91_PIOC 19 AT91_PERIPH_B AT91_PINCTRL_NONE   /* TK1 */
1731                                                          AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE   /* TF1 */
1732                                                          AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TD1 */
1733                                         };
1734
1735                                         pinctrl_ssc1_rx: ssc1_rx {
1736                                                 atmel,pins =
1737                                                         <AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE   /* RK1 */
1738                                                          AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE   /* RF1 */
1739                                                          AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* RD1 */
1740                                         };
1741                                 };
1742
1743                                 spi1 {
1744                                         pinctrl_spi1: spi1-0 {
1745                                                 atmel,pins =
1746                                                         <AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE   /* SPI1_MISO */
1747                                                          AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_NONE   /* SPI1_MOSI */
1748                                                          AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE   /* SPI1_SPCK */
1749                                                         >;
1750                                         };
1751                                 };
1752
1753                                 spi2 {
1754                                         pinctrl_spi2: spi2-0 {
1755                                                 atmel,pins =
1756                                                         <AT91_PIOD 11 AT91_PERIPH_B AT91_PINCTRL_NONE   /* SPI2_MISO conflicts with RTS0 */
1757                                                          AT91_PIOD 13 AT91_PERIPH_B AT91_PINCTRL_NONE   /* SPI2_MOSI conflicts with TXD0 */
1758                                                          AT91_PIOD 15 AT91_PERIPH_B AT91_PINCTRL_NONE   /* SPI2_SPCK conflicts with RTS1 */
1759                                                         >;
1760                                         };
1761                                 };
1762
1763                                 uart0 {
1764                                         pinctrl_uart0: uart0-0 {
1765                                                 atmel,pins =
1766                                                         <AT91_PIOE 29 AT91_PERIPH_B AT91_PINCTRL_NONE           /* RXD */
1767                                                          AT91_PIOE 30 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* TXD */
1768                                                         >;
1769                                         };
1770                                 };
1771
1772                                 uart1 {
1773                                         pinctrl_uart1: uart1-0 {
1774                                                 atmel,pins =
1775                                                         <AT91_PIOC 25 AT91_PERIPH_C AT91_PINCTRL_NONE           /* RXD */
1776                                                          AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_PULL_UP        /* TXD */
1777                                                         >;
1778                                         };
1779                                 };
1780
1781                                 usart0 {
1782                                         pinctrl_usart0: usart0-0 {
1783                                                 atmel,pins =
1784                                                         <AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE           /* RXD */
1785                                                          AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* TXD */
1786                                                         >;
1787                                         };
1788                                         pinctrl_usart0_rts: usart0_rts-0 {
1789                                                 atmel,pins = <AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1790                                         };
1791                                         pinctrl_usart0_cts: usart0_cts-0 {
1792                                                 atmel,pins = <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1793                                         };
1794                                 };
1795
1796                                 usart1 {
1797                                         pinctrl_usart1: usart1-0 {
1798                                                 atmel,pins =
1799                                                         <AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE           /* RXD */
1800                                                          AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP        /* TXD */
1801                                                         >;
1802                                         };
1803                                         pinctrl_usart1_rts: usart1_rts-0 {
1804                                                 atmel,pins = <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1805                                         };
1806                                         pinctrl_usart1_cts: usart1_cts-0 {
1807                                                 atmel,pins = <AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1808                                         };
1809                                 };
1810
1811                                 usart2 {
1812                                         pinctrl_usart2: usart2-0 {
1813                                                 atmel,pins =
1814                                                         <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE            /* RXD - conflicts with G0_CRS, ISI_HSYNC */
1815                                                          AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP         /* TXD - conflicts with G0_COL, PCK2 */
1816                                                         >;
1817                                         };
1818                                         pinctrl_usart2_rts: usart2_rts-0 {
1819                                                 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;    /* conflicts with G0_RX3, PWMH1 */
1820                                         };
1821                                         pinctrl_usart2_cts: usart2_cts-0 {
1822                                                 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;     /* conflicts with G0_TXER, ISI_VSYNC */
1823                                         };
1824                                 };
1825
1826                                 usart3 {
1827                                         pinctrl_usart3: usart3-0 {
1828                                                 atmel,pins =
1829                                                         <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE           /* RXD */
1830                                                          AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* TXD */
1831                                                         >;
1832                                         };
1833                                 };
1834
1835                                 usart4 {
1836                                         pinctrl_usart4: usart4-0 {
1837                                                 atmel,pins =
1838                                                         <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE           /* RXD */
1839                                                          AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP        /* TXD */
1840                                                         >;
1841                                         };
1842                                         pinctrl_usart4_rts: usart4_rts-0 {
1843                                                 atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;    /* conflicts with NWAIT, A19 */
1844                                         };
1845                                         pinctrl_usart4_cts: usart4_cts-0 {
1846                                                 atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>;     /* conflicts with A0/NBS0, MCI0_CDB */
1847                                         };
1848                                 };
1849                         };
1850
1851                         aic: interrupt-controller@fc06e000 {
1852                                 #interrupt-cells = <3>;
1853                                 compatible = "atmel,sama5d4-aic";
1854                                 interrupt-controller;
1855                                 reg = <0xfc06e000 0x200>;
1856                                 atmel,external-irqs = <56>;
1857                         };
1858                 };
1859         };
1860 };