arch/arm/boot/dts/sh73a0.dtsi

   1 /*
   2  * Device Tree Source for the SH73A0 SoC
   3  *
   4  * Copyright (C) 2012 Renesas Solutions Corp.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2.  This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 /include/ "skeleton.dtsi"
  12
  13 #include <dt-bindings/clock/sh73a0-clock.h>
  14 #include <dt-bindings/interrupt-controller/arm-gic.h>
  15 #include <dt-bindings/interrupt-controller/irq.h>
  16
  17 / {
  18         compatible = "renesas,sh73a0";
  19         interrupt-parent = <&gic>;
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu@0 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a9";
  28                         reg = <0>;
  29                         clock-frequency = <1196000000>;
  30                         power-domains = <&pd_a2sl>;
  31                 };
  32                 cpu@1 {
  33                         device_type = "cpu";
  34                         compatible = "arm,cortex-a9";
  35                         reg = <1>;
  36                         clock-frequency = <1196000000>;
  37                         power-domains = <&pd_a2sl>;
  38                 };
  39         };
  40
  41         timer@f0000600 {
  42                 compatible = "arm,cortex-a9-twd-timer";
  43                 reg = <0xf0000600 0x20>;
  44                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
  45                 clocks = <&twd_clk>;
  46         };
  47
  48         gic: interrupt-controller@f0001000 {
  49                 compatible = "arm,cortex-a9-gic";
  50                 #interrupt-cells = <3>;
  51                 interrupt-controller;
  52                 reg = <0xf0001000 0x1000>,
  53                       <0xf0000100 0x100>;
  54         };
  55
  56         sbsc2: memory-controller@fb400000 {
  57                 compatible = "renesas,sbsc-sh73a0";
  58                 reg = <0xfb400000 0x400>;
  59                 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
  60                              <0 38 IRQ_TYPE_LEVEL_HIGH>;
  61                 interrupt-names = "sec", "temp";
  62                 power-domains = <&pd_a4bc1>;
  63         };
  64
  65         sbsc1: memory-controller@fe400000 {
  66                 compatible = "renesas,sbsc-sh73a0";
  67                 reg = <0xfe400000 0x400>;
  68                 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>,
  69                              <0 36 IRQ_TYPE_LEVEL_HIGH>;
  70                 interrupt-names = "sec", "temp";
  71                 power-domains = <&pd_a4bc0>;
  72         };
  73
  74         pmu {
  75                 compatible = "arm,cortex-a9-pmu";
  76                 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>,
  77                              <0 56 IRQ_TYPE_LEVEL_HIGH>;
  78         };
  79
  80         cmt1: timer@e6138000 {
  81                 compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
  82                 reg = <0xe6138000 0x200>;
  83                 interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
  84                 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
  85                 clock-names = "fck";
  86                 power-domains = <&pd_c5>;
  87
  88                 renesas,channels-mask = <0x3f>;
  89
  90                 status = "disabled";
  91         };
  92
  93         irqpin0: irqpin@e6900000 {
  94                 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
  95                 #interrupt-cells = <2>;
  96                 interrupt-controller;
  97                 reg = <0xe6900000 4>,
  98                         <0xe6900010 4>,
  99                         <0xe6900020 1>,
 100                         <0xe6900040 1>,
 101                         <0xe6900060 1>;
 102                 interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH
 103                               0 2 IRQ_TYPE_LEVEL_HIGH
 104                               0 3 IRQ_TYPE_LEVEL_HIGH
 105                               0 4 IRQ_TYPE_LEVEL_HIGH
 106                               0 5 IRQ_TYPE_LEVEL_HIGH
 107                               0 6 IRQ_TYPE_LEVEL_HIGH
 108                               0 7 IRQ_TYPE_LEVEL_HIGH
 109                               0 8 IRQ_TYPE_LEVEL_HIGH>;
 110                 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
 111                 power-domains = <&pd_a4s>;
 112                 control-parent;
 113         };
 114
 115         irqpin1: irqpin@e6900004 {
 116                 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
 117                 #interrupt-cells = <2>;
 118                 interrupt-controller;
 119                 reg = <0xe6900004 4>,
 120                         <0xe6900014 4>,
 121                         <0xe6900024 1>,
 122                         <0xe6900044 1>,
 123                         <0xe6900064 1>;
 124                 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH
 125                               0 10 IRQ_TYPE_LEVEL_HIGH
 126                               0 11 IRQ_TYPE_LEVEL_HIGH
 127                               0 12 IRQ_TYPE_LEVEL_HIGH
 128                               0 13 IRQ_TYPE_LEVEL_HIGH
 129                               0 14 IRQ_TYPE_LEVEL_HIGH
 130                               0 15 IRQ_TYPE_LEVEL_HIGH
 131                               0 16 IRQ_TYPE_LEVEL_HIGH>;
 132                 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
 133                 power-domains = <&pd_a4s>;
 134                 control-parent;
 135         };
 136
 137         irqpin2: irqpin@e6900008 {
 138                 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
 139                 #interrupt-cells = <2>;
 140                 interrupt-controller;
 141                 reg = <0xe6900008 4>,
 142                         <0xe6900018 4>,
 143                         <0xe6900028 1>,
 144                         <0xe6900048 1>,
 145                         <0xe6900068 1>;
 146                 interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH
 147                               0 18 IRQ_TYPE_LEVEL_HIGH
 148                               0 19 IRQ_TYPE_LEVEL_HIGH
 149                               0 20 IRQ_TYPE_LEVEL_HIGH
 150                               0 21 IRQ_TYPE_LEVEL_HIGH
 151                               0 22 IRQ_TYPE_LEVEL_HIGH
 152                               0 23 IRQ_TYPE_LEVEL_HIGH
 153                               0 24 IRQ_TYPE_LEVEL_HIGH>;
 154                 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
 155                 power-domains = <&pd_a4s>;
 156                 control-parent;
 157         };
 158
 159         irqpin3: irqpin@e690000c {
 160                 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
 161                 #interrupt-cells = <2>;
 162                 interrupt-controller;
 163                 reg = <0xe690000c 4>,
 164                         <0xe690001c 4>,
 165                         <0xe690002c 1>,
 166                         <0xe690004c 1>,
 167                         <0xe690006c 1>;
 168                 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH
 169                               0 26 IRQ_TYPE_LEVEL_HIGH
 170                               0 27 IRQ_TYPE_LEVEL_HIGH
 171                               0 28 IRQ_TYPE_LEVEL_HIGH
 172                               0 29 IRQ_TYPE_LEVEL_HIGH
 173                               0 30 IRQ_TYPE_LEVEL_HIGH
 174                               0 31 IRQ_TYPE_LEVEL_HIGH
 175                               0 32 IRQ_TYPE_LEVEL_HIGH>;
 176                 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
 177                 power-domains = <&pd_a4s>;
 178                 control-parent;
 179         };
 180
 181         i2c0: i2c@e6820000 {
 182                 #address-cells = <1>;
 183                 #size-cells = <0>;
 184                 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 185                 reg = <0xe6820000 0x425>;
 186                 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH
 187                               0 168 IRQ_TYPE_LEVEL_HIGH
 188                               0 169 IRQ_TYPE_LEVEL_HIGH
 189                               0 170 IRQ_TYPE_LEVEL_HIGH>;
 190                 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
 191                 power-domains = <&pd_a3sp>;
 192                 status = "disabled";
 193         };
 194
 195         i2c1: i2c@e6822000 {
 196                 #address-cells = <1>;
 197                 #size-cells = <0>;
 198                 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 199                 reg = <0xe6822000 0x425>;
 200                 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH
 201                               0 52 IRQ_TYPE_LEVEL_HIGH
 202                               0 53 IRQ_TYPE_LEVEL_HIGH
 203                               0 54 IRQ_TYPE_LEVEL_HIGH>;
 204                 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
 205                 power-domains = <&pd_a3sp>;
 206                 status = "disabled";
 207         };
 208
 209         i2c2: i2c@e6824000 {
 210                 #address-cells = <1>;
 211                 #size-cells = <0>;
 212                 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 213                 reg = <0xe6824000 0x425>;
 214                 interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH
 215                               0 172 IRQ_TYPE_LEVEL_HIGH
 216                               0 173 IRQ_TYPE_LEVEL_HIGH
 217                               0 174 IRQ_TYPE_LEVEL_HIGH>;
 218                 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
 219                 power-domains = <&pd_a3sp>;
 220                 status = "disabled";
 221         };
 222
 223         i2c3: i2c@e6826000 {
 224                 #address-cells = <1>;
 225                 #size-cells = <0>;
 226                 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 227                 reg = <0xe6826000 0x425>;
 228                 interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH
 229                               0 184 IRQ_TYPE_LEVEL_HIGH
 230                               0 185 IRQ_TYPE_LEVEL_HIGH
 231                               0 186 IRQ_TYPE_LEVEL_HIGH>;
 232                 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
 233                 power-domains = <&pd_a3sp>;
 234                 status = "disabled";
 235         };
 236
 237         i2c4: i2c@e6828000 {
 238                 #address-cells = <1>;
 239                 #size-cells = <0>;
 240                 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
 241                 reg = <0xe6828000 0x425>;
 242                 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH
 243                               0 188 IRQ_TYPE_LEVEL_HIGH
 244                               0 189 IRQ_TYPE_LEVEL_HIGH
 245                               0 190 IRQ_TYPE_LEVEL_HIGH>;
 246                 clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
 247                 power-domains = <&pd_c5>;
 248                 status = "disabled";
 249         };
 250
 251         mmcif: mmc@e6bd0000 {
 252                 compatible = "renesas,sh-mmcif";
 253                 reg = <0xe6bd0000 0x100>;
 254                 interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
 255                               0 141 IRQ_TYPE_LEVEL_HIGH>;
 256                 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
 257                 power-domains = <&pd_a3sp>;
 258                 reg-io-width = <4>;
 259                 status = "disabled";
 260         };
 261
 262         sdhi0: sd@ee100000 {
 263                 compatible = "renesas,sdhi-sh73a0";
 264                 reg = <0xee100000 0x100>;
 265                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH
 266                               0 84 IRQ_TYPE_LEVEL_HIGH
 267                               0 85 IRQ_TYPE_LEVEL_HIGH>;
 268                 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
 269                 power-domains = <&pd_a3sp>;
 270                 cap-sd-highspeed;
 271                 status = "disabled";
 272         };
 273
 274         /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
 275         sdhi1: sd@ee120000 {
 276                 compatible = "renesas,sdhi-sh73a0";
 277                 reg = <0xee120000 0x100>;
 278                 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
 279                               0 89 IRQ_TYPE_LEVEL_HIGH>;
 280                 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
 281                 power-domains = <&pd_a3sp>;
 282                 toshiba,mmc-wrprotect-disable;
 283                 cap-sd-highspeed;
 284                 status = "disabled";
 285         };
 286
 287         sdhi2: sd@ee140000 {
 288                 compatible = "renesas,sdhi-sh73a0";
 289                 reg = <0xee140000 0x100>;
 290                 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
 291                               0 105 IRQ_TYPE_LEVEL_HIGH>;
 292                 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
 293                 power-domains = <&pd_a3sp>;
 294                 toshiba,mmc-wrprotect-disable;
 295                 cap-sd-highspeed;
 296                 status = "disabled";
 297         };
 298
 299         scifa0: serial@e6c40000 {
 300                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 301                 reg = <0xe6c40000 0x100>;
 302                 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
 303                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
 304                 clock-names = "sci_ick";
 305                 power-domains = <&pd_a3sp>;
 306                 status = "disabled";
 307         };
 308
 309         scifa1: serial@e6c50000 {
 310                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 311                 reg = <0xe6c50000 0x100>;
 312                 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
 313                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
 314                 clock-names = "sci_ick";
 315                 power-domains = <&pd_a3sp>;
 316                 status = "disabled";
 317         };
 318
 319         scifa2: serial@e6c60000 {
 320                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 321                 reg = <0xe6c60000 0x100>;
 322                 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
 323                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
 324                 clock-names = "sci_ick";
 325                 power-domains = <&pd_a3sp>;
 326                 status = "disabled";
 327         };
 328
 329         scifa3: serial@e6c70000 {
 330                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 331                 reg = <0xe6c70000 0x100>;
 332                 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
 333                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
 334                 clock-names = "sci_ick";
 335                 power-domains = <&pd_a3sp>;
 336                 status = "disabled";
 337         };
 338
 339         scifa4: serial@e6c80000 {
 340                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 341                 reg = <0xe6c80000 0x100>;
 342                 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
 343                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
 344                 clock-names = "sci_ick";
 345                 power-domains = <&pd_a3sp>;
 346                 status = "disabled";
 347         };
 348
 349         scifa5: serial@e6cb0000 {
 350                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 351                 reg = <0xe6cb0000 0x100>;
 352                 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
 353                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
 354                 clock-names = "sci_ick";
 355                 power-domains = <&pd_a3sp>;
 356                 status = "disabled";
 357         };
 358
 359         scifa6: serial@e6cc0000 {
 360                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 361                 reg = <0xe6cc0000 0x100>;
 362                 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
 363                 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
 364                 clock-names = "sci_ick";
 365                 power-domains = <&pd_a3sp>;
 366                 status = "disabled";
 367         };
 368
 369         scifa7: serial@e6cd0000 {
 370                 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
 371                 reg = <0xe6cd0000 0x100>;
 372                 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
 373                 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
 374                 clock-names = "sci_ick";
 375                 power-domains = <&pd_a3sp>;
 376                 status = "disabled";
 377         };
 378
 379         scifb8: serial@e6c30000 {
 380                 compatible = "renesas,scifb-sh73a0", "renesas,scifb";
 381                 reg = <0xe6c30000 0x100>;
 382                 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
 383                 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
 384                 clock-names = "sci_ick";
 385                 power-domains = <&pd_a3sp>;
 386                 status = "disabled";
 387         };
 388
 389         pfc: pfc@e6050000 {
 390                 compatible = "renesas,pfc-sh73a0";
 391                 reg = <0xe6050000 0x8000>,
 392                       <0xe605801c 0x1c>;
 393                 gpio-controller;
 394                 #gpio-cells = <2>;
 395                 interrupts-extended =
 396                         <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
 397                         <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
 398                         <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
 399                         <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
 400                         <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
 401                         <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
 402                         <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
 403                         <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
 404                 power-domains = <&pd_c5>;
 405         };
 406
 407         sysc: system-controller@e6180000 {
 408                 compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
 409                 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
 410
 411                 pm-domains {
 412                         pd_c5: c5 {
 413                                 #address-cells = <1>;
 414                                 #size-cells = <0>;
 415                                 #power-domain-cells = <0>;
 416
 417                                 pd_c4: c4@0 {
 418                                         reg = <0>;
 419                                         #power-domain-cells = <0>;
 420                                 };
 421
 422                                 pd_d4: d4@1 {
 423                                         reg = <1>;
 424                                         #power-domain-cells = <0>;
 425                                 };
 426
 427                                 pd_a4bc0: a4bc0@4 {
 428                                         reg = <4>;
 429                                         #power-domain-cells = <0>;
 430                                 };
 431
 432                                 pd_a4bc1: a4bc1@5 {
 433                                         reg = <5>;
 434                                         #power-domain-cells = <0>;
 435                                 };
 436
 437                                 pd_a4lc0: a4lc0@6 {
 438                                         reg = <6>;
 439                                         #power-domain-cells = <0>;
 440                                 };
 441
 442                                 pd_a4lc1: a4lc1@7 {
 443                                         reg = <7>;
 444                                         #power-domain-cells = <0>;
 445                                 };
 446
 447                                 pd_a4mp: a4mp@8 {
 448                                         reg = <8>;
 449                                         #address-cells = <1>;
 450                                         #size-cells = <0>;
 451                                         #power-domain-cells = <0>;
 452
 453                                         pd_a3mp: a3mp@9 {
 454                                                 reg = <9>;
 455                                                 #power-domain-cells = <0>;
 456                                         };
 457
 458                                         pd_a3vc: a3vc@10 {
 459                                                 reg = <10>;
 460                                                 #power-domain-cells = <0>;
 461                                         };
 462                                 };
 463
 464                                 pd_a4rm: a4rm@12 {
 465                                         reg = <12>;
 466                                         #address-cells = <1>;
 467                                         #size-cells = <0>;
 468                                         #power-domain-cells = <0>;
 469
 470                                         pd_a3r: a3r@13 {
 471                                                 reg = <13>;
 472                                                 #address-cells = <1>;
 473                                                 #size-cells = <0>;
 474                                                 #power-domain-cells = <0>;
 475
 476                                                 pd_a2rv: a2rv@14 {
 477                                                         reg = <14>;
 478                                                         #address-cells = <1>;
 479                                                         #size-cells = <0>;
 480                                                         #power-domain-cells = <0>;
 481                                                 };
 482                                         };
 483                                 };
 484
 485                                 pd_a4s: a4s@16 {
 486                                         reg = <16>;
 487                                         #address-cells = <1>;
 488                                         #size-cells = <0>;
 489                                         #power-domain-cells = <0>;
 490
 491                                         pd_a3sp: a3sp@17 {
 492                                                 reg = <17>;
 493                                                 #power-domain-cells = <0>;
 494                                         };
 495
 496                                         pd_a3sg: a3sg@18 {
 497                                                 reg = <18>;
 498                                                 #power-domain-cells = <0>;
 499                                         };
 500
 501                                         pd_a3sm: a3sm@19 {
 502                                                 reg = <19>;
 503                                                 #address-cells = <1>;
 504                                                 #size-cells = <0>;
 505                                                 #power-domain-cells = <0>;
 506
 507                                                 pd_a2sl: a2sl@20 {
 508                                                         reg = <20>;
 509                                                         #power-domain-cells = <0>;
 510                                                 };
 511                                         };
 512                                 };
 513                         };
 514                 };
 515         };
 516
 517         sh_fsi2: sound@ec230000 {
 518                 #sound-dai-cells = <1>;
 519                 compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
 520                 reg = <0xec230000 0x400>;
 521                 interrupts = <0 146 0x4>;
 522                 power-domains = <&pd_a4mp>;
 523                 status = "disabled";
 524         };
 525
 526         bsc: bus@fec10000 {
 527                 compatible = "renesas,bsc-sh73a0", "renesas,bsc",
 528                              "simple-pm-bus";
 529                 #address-cells = <1>;
 530                 #size-cells = <1>;
 531                 ranges = <0 0 0x20000000>;
 532                 reg = <0xfec10000 0x400>;
 533                 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 534                 clocks = <&zb_clk>;
 535                 power-domains = <&pd_a4s>;
 536         };
 537
 538         clocks {
 539                 #address-cells = <1>;
 540                 #size-cells = <1>;
 541                 ranges;
 542
 543                 /* External root clocks */
 544                 extalr_clk: extalr_clk {
 545                         compatible = "fixed-clock";
 546                         #clock-cells = <0>;
 547                         clock-frequency = <32768>;
 548                         clock-output-names = "extalr";
 549                 };
 550                 extal1_clk: extal1_clk {
 551                         compatible = "fixed-clock";
 552                         #clock-cells = <0>;
 553                         clock-frequency = <26000000>;
 554                         clock-output-names = "extal1";
 555                 };
 556                 extal2_clk: extal2_clk {
 557                         compatible = "fixed-clock";
 558                         #clock-cells = <0>;
 559                         clock-output-names = "extal2";
 560                 };
 561                 extcki_clk: extcki_clk {
 562                         compatible = "fixed-clock";
 563                         #clock-cells = <0>;
 564                         clock-output-names = "extcki";
 565                 };
 566                 fsiack_clk: fsiack_clk {
 567                         compatible = "fixed-clock";
 568                         #clock-cells = <0>;
 569                         clock-frequency = <0>;
 570                         clock-output-names = "fsiack";
 571                 };
 572                 fsibck_clk: fsibck_clk {
 573                         compatible = "fixed-clock";
 574                         #clock-cells = <0>;
 575                         clock-frequency = <0>;
 576                         clock-output-names = "fsibck";
 577                 };
 578
 579                 /* Special CPG clocks */
 580                 cpg_clocks: cpg_clocks@e6150000 {
 581                         compatible = "renesas,sh73a0-cpg-clocks";
 582                         reg = <0xe6150000 0x10000>;
 583                         clocks = <&extal1_clk>, <&extal2_clk>;
 584                         #clock-cells = <1>;
 585                         clock-output-names = "main", "pll0", "pll1", "pll2",
 586                                              "pll3", "dsi0phy", "dsi1phy",
 587                                              "zg", "m3", "b", "m1", "m2",
 588                                              "z", "zx", "hp";
 589                 };
 590
 591                 /* Variable factor clocks (DIV6) */
 592                 vclk1_clk: vclk1_clk@e6150008 {
 593                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 594                         reg = <0xe6150008 4>;
 595                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 596                                  <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
 597                                  <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
 598                                  <0>;
 599                         #clock-cells = <0>;
 600                         clock-output-names = "vclk1";
 601                 };
 602                 vclk2_clk: vclk2_clk@e615000c {
 603                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 604                         reg = <0xe615000c 4>;
 605                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 606                                  <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
 607                                  <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
 608                                  <0>;
 609                         #clock-cells = <0>;
 610                         clock-output-names = "vclk2";
 611                 };
 612                 vclk3_clk: vclk3_clk@e615001c {
 613                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 614                         reg = <0xe615001c 4>;
 615                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 616                                  <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
 617                                  <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
 618                                  <0>;
 619                         #clock-cells = <0>;
 620                         clock-output-names = "vclk3";
 621                 };
 622                 zb_clk: zb_clk@e6150010 {
 623                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 624                         reg = <0xe6150010 4>;
 625                         clocks = <&pll1_div2_clk>, <0>,
 626                                  <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 627                         #clock-cells = <0>;
 628                         clock-output-names = "zb";
 629                 };
 630                 flctl_clk: flctl_clk@e6150014 {
 631                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 632                         reg = <0xe6150014 4>;
 633                         clocks = <&pll1_div2_clk>, <0>,
 634                                  <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 635                         #clock-cells = <0>;
 636                         clock-output-names = "flctlck";
 637                 };
 638                 sdhi0_clk: sdhi0_clk@e6150074 {
 639                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 640                         reg = <0xe6150074 4>;
 641                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 642                                  <&pll1_div13_clk>, <0>;
 643                         #clock-cells = <0>;
 644                         clock-output-names = "sdhi0ck";
 645                 };
 646                 sdhi1_clk: sdhi1_clk@e6150078 {
 647                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 648                         reg = <0xe6150078 4>;
 649                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 650                                  <&pll1_div13_clk>, <0>;
 651                         #clock-cells = <0>;
 652                         clock-output-names = "sdhi1ck";
 653                 };
 654                 sdhi2_clk: sdhi2_clk@e615007c {
 655                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 656                         reg = <0xe615007c 4>;
 657                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 658                                  <&pll1_div13_clk>, <0>;
 659                         #clock-cells = <0>;
 660                         clock-output-names = "sdhi2ck";
 661                 };
 662                 fsia_clk: fsia_clk@e6150018 {
 663                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 664                         reg = <0xe6150018 4>;
 665                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 666                                  <&fsiack_clk>, <&fsiack_clk>;
 667                         #clock-cells = <0>;
 668                         clock-output-names = "fsia";
 669                 };
 670                 fsib_clk: fsib_clk@e6150090 {
 671                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 672                         reg = <0xe6150090 4>;
 673                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 674                                  <&fsibck_clk>, <&fsibck_clk>;
 675                         #clock-cells = <0>;
 676                         clock-output-names = "fsib";
 677                 };
 678                 sub_clk: sub_clk@e6150080 {
 679                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 680                         reg = <0xe6150080 4>;
 681                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 682                                  <&extal2_clk>, <&extal2_clk>;
 683                         #clock-cells = <0>;
 684                         clock-output-names = "sub";
 685                 };
 686                 spua_clk: spua_clk@e6150084 {
 687                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 688                         reg = <0xe6150084 4>;
 689                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 690                                  <&extal2_clk>, <&extal2_clk>;
 691                         #clock-cells = <0>;
 692                         clock-output-names = "spua";
 693                 };
 694                 spuv_clk: spuv_clk@e6150094 {
 695                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 696                         reg = <0xe6150094 4>;
 697                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 698                                  <&extal2_clk>, <&extal2_clk>;
 699                         #clock-cells = <0>;
 700                         clock-output-names = "spuv";
 701                 };
 702                 msu_clk: msu_clk@e6150088 {
 703                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 704                         reg = <0xe6150088 4>;
 705                         clocks = <&pll1_div2_clk>, <0>,
 706                                  <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 707                         #clock-cells = <0>;
 708                         clock-output-names = "msu";
 709                 };
 710                 hsi_clk: hsi_clk@e615008c {
 711                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 712                         reg = <0xe615008c 4>;
 713                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 714                                  <&pll1_div7_clk>, <0>;
 715                         #clock-cells = <0>;
 716                         clock-output-names = "hsi";
 717                 };
 718                 mfg1_clk: mfg1_clk@e6150098 {
 719                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 720                         reg = <0xe6150098 4>;
 721                         clocks = <&pll1_div2_clk>, <0>,
 722                                  <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 723                         #clock-cells = <0>;
 724                         clock-output-names = "mfg1";
 725                 };
 726                 mfg2_clk: mfg2_clk@e615009c {
 727                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 728                         reg = <0xe615009c 4>;
 729                         clocks = <&pll1_div2_clk>, <0>,
 730                                  <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 731                         #clock-cells = <0>;
 732                         clock-output-names = "mfg2";
 733                 };
 734                 dsit_clk: dsit_clk@e6150060 {
 735                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 736                         reg = <0xe6150060 4>;
 737                         clocks = <&pll1_div2_clk>, <0>,
 738                                  <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
 739                         #clock-cells = <0>;
 740                         clock-output-names = "dsit";
 741                 };
 742                 dsi0p_clk: dsi0p_clk@e6150064 {
 743                         compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
 744                         reg = <0xe6150064 4>;
 745                         clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
 746                                  <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
 747                                  <&extcki_clk>, <0>, <0>, <0>;
 748                         #clock-cells = <0>;
 749                         clock-output-names = "dsi0pck";
 750                 };
 751
 752                 /* Fixed factor clocks */
 753                 main_div2_clk: main_div2_clk {
 754                         compatible = "fixed-factor-clock";
 755                         clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
 756                         #clock-cells = <0>;
 757                         clock-div = <2>;
 758                         clock-mult = <1>;
 759                         clock-output-names = "main_div2";
 760                 };
 761                 pll1_div2_clk: pll1_div2_clk {
 762                         compatible = "fixed-factor-clock";
 763                         clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
 764                         #clock-cells = <0>;
 765                         clock-div = <2>;
 766                         clock-mult = <1>;
 767                         clock-output-names = "pll1_div2";
 768                 };
 769                 pll1_div7_clk: pll1_div7_clk {
 770                         compatible = "fixed-factor-clock";
 771                         clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
 772                         #clock-cells = <0>;
 773                         clock-div = <7>;
 774                         clock-mult = <1>;
 775                         clock-output-names = "pll1_div7";
 776                 };
 777                 pll1_div13_clk: pll1_div13_clk {
 778                         compatible = "fixed-factor-clock";
 779                         clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
 780                         #clock-cells = <0>;
 781                         clock-div = <13>;
 782                         clock-mult = <1>;
 783                         clock-output-names = "pll1_div13";
 784                 };
 785                 twd_clk: twd_clk {
 786                         compatible = "fixed-factor-clock";
 787                         clocks = <&cpg_clocks SH73A0_CLK_Z>;
 788                         #clock-cells = <0>;
 789                         clock-div = <4>;
 790                         clock-mult = <1>;
 791                         clock-output-names = "twd";
 792                 };
 793
 794                 /* Gate clocks */
 795                 mstp0_clks: mstp0_clks@e6150130 {
 796                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 797                         reg = <0xe6150130 4>, <0xe6150030 4>;
 798                         clocks = <&cpg_clocks SH73A0_CLK_HP>;
 799                         #clock-cells = <1>;
 800                         clock-indices = <
 801                                 SH73A0_CLK_IIC2
 802                         >;
 803                         clock-output-names =
 804                                 "iic2";
 805                 };
 806                 mstp1_clks: mstp1_clks@e6150134 {
 807                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 808                         reg = <0xe6150134 4>, <0xe6150038 4>;
 809                         clocks = <&cpg_clocks SH73A0_CLK_B>,
 810                                  <&cpg_clocks SH73A0_CLK_B>,
 811                                  <&cpg_clocks SH73A0_CLK_B>,
 812                                  <&cpg_clocks SH73A0_CLK_B>,
 813                                  <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>,
 814                                  <&cpg_clocks SH73A0_CLK_HP>,
 815                                  <&cpg_clocks SH73A0_CLK_ZG>,
 816                                  <&cpg_clocks SH73A0_CLK_B>;
 817                         #clock-cells = <1>;
 818                         clock-indices = <
 819                                 SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1
 820                                 SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0
 821                                 SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0
 822                                 SH73A0_CLK_IIC0 SH73A0_CLK_SGX
 823                                 SH73A0_CLK_LCDC0
 824                         >;
 825                         clock-output-names =
 826                                 "ceu1", "csi2_rx1", "ceu0", "csi2_rx0",
 827                                 "tmu0", "dsitx0", "iic0", "sgx", "lcdc0";
 828                 };
 829                 mstp2_clks: mstp2_clks@e6150138 {
 830                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 831                         reg = <0xe6150138 4>, <0xe6150040 4>;
 832                         clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
 833                                  <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
 834                                  <&sub_clk>, <&sub_clk>, <&sub_clk>, <&sub_clk>,
 835                                  <&sub_clk>, <&sub_clk>;
 836                         #clock-cells = <1>;
 837                         clock-indices = <
 838                                 SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC
 839                                 SH73A0_CLK_MP_DMAC SH73A0_CLK_SCIFA5
 840                                 SH73A0_CLK_SCIFB SH73A0_CLK_SCIFA0
 841                                 SH73A0_CLK_SCIFA1 SH73A0_CLK_SCIFA2
 842                                 SH73A0_CLK_SCIFA3 SH73A0_CLK_SCIFA4
 843                         >;
 844                         clock-output-names =
 845                                 "scifa7", "sy_dmac", "mp_dmac", "scifa5",
 846                                 "scifb", "scifa0", "scifa1", "scifa2",
 847                                 "scifa3", "scifa4";
 848                 };
 849                 mstp3_clks: mstp3_clks@e615013c {
 850                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 851                         reg = <0xe615013c 4>, <0xe6150048 4>;
 852                         clocks = <&sub_clk>, <&extalr_clk>,
 853                                  <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
 854                                  <&cpg_clocks SH73A0_CLK_HP>,
 855                                  <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>,
 856                                  <&sdhi0_clk>, <&sdhi1_clk>,
 857                                  <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>,
 858                                  <&main_div2_clk>, <&main_div2_clk>,
 859                                  <&main_div2_clk>, <&main_div2_clk>,
 860                                  <&main_div2_clk>;
 861                         #clock-cells = <1>;
 862                         clock-indices = <
 863                                 SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1
 864                                 SH73A0_CLK_FSI SH73A0_CLK_IRDA
 865                                 SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL
 866                                 SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1
 867                                 SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2
 868                                 SH73A0_CLK_TPU0 SH73A0_CLK_TPU1
 869                                 SH73A0_CLK_TPU2 SH73A0_CLK_TPU3
 870                                 SH73A0_CLK_TPU4
 871                         >;
 872                         clock-output-names =
 873                                 "scifa6", "cmt1", "fsi", "irda", "iic1",
 874                                 "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2",
 875                                 "tpu0", "tpu1", "tpu2", "tpu3", "tpu4";
 876                 };
 877                 mstp4_clks: mstp4_clks@e6150140 {
 878                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 879                         reg = <0xe6150140 4>, <0xe615004c 4>;
 880                         clocks = <&cpg_clocks SH73A0_CLK_HP>,
 881                                  <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>;
 882                         #clock-cells = <1>;
 883                         clock-indices = <
 884                                 SH73A0_CLK_IIC3 SH73A0_CLK_IIC4
 885                                 SH73A0_CLK_KEYSC
 886                         >;
 887                         clock-output-names =
 888                                 "iic3", "iic4", "keysc";
 889                 };
 890                 mstp5_clks: mstp5_clks@e6150144 {
 891                         compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
 892                         reg = <0xe6150144 4>, <0xe615003c 4>;
 893                         clocks = <&cpg_clocks SH73A0_CLK_HP>;
 894                         #clock-cells = <1>;
 895                         clock-indices = <
 896                                 SH73A0_CLK_INTCA0
 897                         >;
 898                         clock-output-names =
 899                                 "intca0";
 900                 };
 901         };
 902 };