2 * Copyright Altera Corporation (C) 2014. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program. If not, see <http://www.gnu.org/licenses/>.
17 #include "skeleton.dtsi"
18 #include <dt-bindings/interrupt-controller/arm-gic.h>
29 compatible = "arm,cortex-a9";
32 next-level-cache = <&L2>;
35 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
43 compatible = "arm,cortex-a9-gic";
44 #interrupt-cells = <3>;
46 reg = <0xffffd000 0x1000>,
53 compatible = "simple-bus";
55 interrupt-parent = <&intc>;
59 compatible = "arm,amba-bus";
65 compatible = "arm,pl330", "arm,primecell";
66 reg = <0xffda1000 0x1000>;
67 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
68 <0 84 IRQ_TYPE_LEVEL_HIGH>,
69 <0 85 IRQ_TYPE_LEVEL_HIGH>,
70 <0 86 IRQ_TYPE_LEVEL_HIGH>,
71 <0 87 IRQ_TYPE_LEVEL_HIGH>,
72 <0 88 IRQ_TYPE_LEVEL_HIGH>,
73 <0 89 IRQ_TYPE_LEVEL_HIGH>,
74 <0 90 IRQ_TYPE_LEVEL_HIGH>;
82 compatible = "altr,clk-mgr";
83 reg = <0xffd04000 0x1000>;
89 cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
91 compatible = "fixed-clock";
94 cb_intosc_ls_clk: cb_intosc_ls_clk {
96 compatible = "fixed-clock";
99 f2s_free_clk: f2s_free_clk {
101 compatible = "fixed-clock";
106 compatible = "fixed-clock";
110 #address-cells = <1>;
113 compatible = "altr,socfpga-a10-pll-clock";
114 clocks = <&osc1>, <&cb_intosc_ls_clk>,
118 main_mpu_base_clk: main_mpu_base_clk {
120 compatible = "altr,socfpga-a10-perip-clk";
121 clocks = <&main_pll>;
122 div-reg = <0x140 0 11>;
125 main_noc_base_clk: main_noc_base_clk {
127 compatible = "altr,socfpga-a10-perip-clk";
128 clocks = <&main_pll>;
129 div-reg = <0x144 0 11>;
132 main_emaca_clk: main_emaca_clk {
134 compatible = "altr,socfpga-a10-perip-clk";
135 clocks = <&main_pll>;
139 main_emacb_clk: main_emacb_clk {
141 compatible = "altr,socfpga-a10-perip-clk";
142 clocks = <&main_pll>;
146 main_emac_ptp_clk: main_emac_ptp_clk {
148 compatible = "altr,socfpga-a10-perip-clk";
149 clocks = <&main_pll>;
153 main_gpio_db_clk: main_gpio_db_clk {
155 compatible = "altr,socfpga-a10-perip-clk";
156 clocks = <&main_pll>;
160 main_sdmmc_clk: main_sdmmc_clk {
162 compatible = "altr,socfpga-a10-perip-clk"
164 clocks = <&main_pll>;
168 main_s2f_usr0_clk: main_s2f_usr0_clk {
170 compatible = "altr,socfpga-a10-perip-clk";
171 clocks = <&main_pll>;
175 main_s2f_usr1_clk: main_s2f_usr1_clk {
177 compatible = "altr,socfpga-a10-perip-clk";
178 clocks = <&main_pll>;
182 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk {
184 compatible = "altr,socfpga-a10-perip-clk";
185 clocks = <&main_pll>;
189 main_periph_ref_clk: main_periph_ref_clk {
191 compatible = "altr,socfpga-a10-perip-clk";
192 clocks = <&main_pll>;
197 periph_pll: periph_pll {
198 #address-cells = <1>;
201 compatible = "altr,socfpga-a10-pll-clock";
202 clocks = <&osc1>, <&cb_intosc_ls_clk>,
203 <&f2s_free_clk>, <&main_periph_ref_clk>;
206 peri_mpu_base_clk: peri_mpu_base_clk {
208 compatible = "altr,socfpga-a10-perip-clk";
209 clocks = <&periph_pll>;
210 div-reg = <0x140 16 11>;
213 peri_noc_base_clk: peri_noc_base_clk {
215 compatible = "altr,socfpga-a10-perip-clk";
216 clocks = <&periph_pll>;
217 div-reg = <0x144 16 11>;
220 peri_emaca_clk: peri_emaca_clk {
222 compatible = "altr,socfpga-a10-perip-clk";
223 clocks = <&periph_pll>;
227 peri_emacb_clk: peri_emacb_clk {
229 compatible = "altr,socfpga-a10-perip-clk";
230 clocks = <&periph_pll>;
234 peri_emac_ptp_clk: peri_emac_ptp_clk {
236 compatible = "altr,socfpga-a10-perip-clk";
237 clocks = <&periph_pll>;
241 peri_gpio_db_clk: peri_gpio_db_clk {
243 compatible = "altr,socfpga-a10-perip-clk";
244 clocks = <&periph_pll>;
248 peri_sdmmc_clk: peri_sdmmc_clk {
250 compatible = "altr,socfpga-a10-perip-clk";
251 clocks = <&periph_pll>;
255 peri_s2f_usr0_clk: peri_s2f_usr0_clk {
257 compatible = "altr,socfpga-a10-perip-clk";
258 clocks = <&periph_pll>;
262 peri_s2f_usr1_clk: peri_s2f_usr1_clk {
264 compatible = "altr,socfpga-a10-perip-clk";
265 clocks = <&periph_pll>;
269 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk {
271 compatible = "altr,socfpga-a10-perip-clk";
272 clocks = <&periph_pll>;
277 mpu_free_clk: mpu_free_clk {
279 compatible = "altr,socfpga-a10-perip-clk";
280 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
281 <&osc1>, <&cb_intosc_hs_div2_clk>,
286 noc_free_clk: noc_free_clk {
288 compatible = "altr,socfpga-a10-perip-clk";
289 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
290 <&osc1>, <&cb_intosc_hs_div2_clk>,
295 s2f_user1_free_clk: s2f_user1_free_clk {
297 compatible = "altr,socfpga-a10-perip-clk";
298 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
299 <&osc1>, <&cb_intosc_hs_div2_clk>,
304 sdmmc_free_clk: sdmmc_free_clk {
306 compatible = "altr,socfpga-a10-perip-clk";
307 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
308 <&osc1>, <&cb_intosc_hs_div2_clk>,
314 l4_sys_free_clk: l4_sys_free_clk {
316 compatible = "altr,socfpga-a10-perip-clk";
317 clocks = <&noc_free_clk>;
321 l4_main_clk: l4_main_clk {
323 compatible = "altr,socfpga-a10-gate-clk";
324 clocks = <&noc_free_clk>;
325 div-reg = <0xA8 0 2>;
329 l4_mp_clk: l4_mp_clk {
331 compatible = "altr,socfpga-a10-gate-clk";
332 clocks = <&noc_free_clk>;
333 div-reg = <0xA8 8 2>;
337 l4_sp_clk: l4_sp_clk {
339 compatible = "altr,socfpga-a10-gate-clk";
340 clocks = <&noc_free_clk>;
341 div-reg = <0xA8 16 2>;
345 mpu_periph_clk: mpu_periph_clk {
347 compatible = "altr,socfpga-a10-gate-clk";
348 clocks = <&mpu_free_clk>;
353 sdmmc_clk: sdmmc_clk {
355 compatible = "altr,socfpga-a10-gate-clk";
356 clocks = <&sdmmc_free_clk>;
362 compatible = "altr,socfpga-a10-gate-clk";
363 clocks = <&l4_main_clk>;
364 clk-gate = <0xC8 11>;
369 compatible = "altr,socfpga-a10-gate-clk";
370 clocks = <&l4_mp_clk>;
371 clk-gate = <0xC8 10>;
374 spi_m_clk: spi_m_clk {
376 compatible = "altr,socfpga-a10-gate-clk";
377 clocks = <&l4_main_clk>;
383 compatible = "altr,socfpga-a10-gate-clk";
384 clocks = <&l4_mp_clk>;
388 s2f_usr1_clk: s2f_usr1_clk {
390 compatible = "altr,socfpga-a10-gate-clk";
391 clocks = <&peri_s2f_usr1_clk>;
397 gmac0: ethernet@ff800000 {
398 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
399 reg = <0xff800000 0x2000>;
400 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
401 interrupt-names = "macirq";
402 /* Filled in by bootloader */
403 mac-address = [00 00 00 00 00 00];
404 snps,multicast-filter-bins = <256>;
405 snps,perfect-filter-entries = <128>;
409 gmac1: ethernet@ff802000 {
410 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
411 reg = <0xff802000 0x2000>;
412 interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
413 interrupt-names = "macirq";
414 /* Filled in by bootloader */
415 mac-address = [00 00 00 00 00 00];
416 snps,multicast-filter-bins = <256>;
417 snps,perfect-filter-entries = <128>;
418 tx-fifo-depth = <4096>;
419 rx-fifo-depth = <16384>;
423 gmac2: ethernet@ff804000 {
424 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
425 reg = <0xff804000 0x2000>;
426 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
427 interrupt-names = "macirq";
428 /* Filled in by bootloader */
429 mac-address = [00 00 00 00 00 00];
430 snps,multicast-filter-bins = <256>;
431 snps,perfect-filter-entries = <128>;
432 tx-fifo-depth = <4096>;
433 rx-fifo-depth = <16384>;
437 gpio0: gpio@ffc02900 {
438 #address-cells = <1>;
440 compatible = "snps,dw-apb-gpio";
441 reg = <0xffc02900 0x100>;
444 porta: gpio-controller@0 {
445 compatible = "snps,dw-apb-gpio-port";
448 snps,nr-gpios = <29>;
450 interrupt-controller;
451 #interrupt-cells = <2>;
452 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
456 gpio1: gpio@ffc02a00 {
457 #address-cells = <1>;
459 compatible = "snps,dw-apb-gpio";
460 reg = <0xffc02a00 0x100>;
463 portb: gpio-controller@0 {
464 compatible = "snps,dw-apb-gpio-port";
467 snps,nr-gpios = <29>;
469 interrupt-controller;
470 #interrupt-cells = <2>;
471 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
475 gpio2: gpio@ffc02b00 {
476 #address-cells = <1>;
478 compatible = "snps,dw-apb-gpio";
479 reg = <0xffc02b00 0x100>;
482 portc: gpio-controller@0 {
483 compatible = "snps,dw-apb-gpio-port";
486 snps,nr-gpios = <27>;
488 interrupt-controller;
489 #interrupt-cells = <2>;
490 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
495 #address-cells = <1>;
497 compatible = "snps,designware-i2c";
498 reg = <0xffc02200 0x100>;
499 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
504 #address-cells = <1>;
506 compatible = "snps,designware-i2c";
507 reg = <0xffc02300 0x100>;
508 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
513 #address-cells = <1>;
515 compatible = "snps,designware-i2c";
516 reg = <0xffc02400 0x100>;
517 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
522 #address-cells = <1>;
524 compatible = "snps,designware-i2c";
525 reg = <0xffc02500 0x100>;
526 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
531 #address-cells = <1>;
533 compatible = "snps,designware-i2c";
534 reg = <0xffc02600 0x100>;
535 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
539 L2: l2-cache@fffff000 {
540 compatible = "arm,pl310-cache";
541 reg = <0xfffff000 0x1000>;
542 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
547 mmc: dwmmc0@ff808000 {
548 #address-cells = <1>;
550 compatible = "altr,socfpga-dw-mshc";
551 reg = <0xff808000 0x1000>;
552 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
553 fifo-depth = <0x400>;
554 clocks = <&l4_mp_clk>, <&sdmmc_free_clk>;
555 clock-names = "biu", "ciu";
559 ocram: sram@ffe00000 {
560 compatible = "mmio-sram";
561 reg = <0xffe00000 0x40000>;
564 rst: rstmgr@ffd05000 {
566 compatible = "altr,rst-mgr";
567 reg = <0xffd05000 0x100>;
570 sysmgr: sysmgr@ffd06000 {
571 compatible = "altr,sys-mgr", "syscon";
572 reg = <0xffd06000 0x300>;
573 cpu1-start-addr = <0xffd06230>;
578 compatible = "arm,cortex-a9-twd-timer";
579 reg = <0xffffc600 0x100>;
580 interrupts = <1 13 0xf04>;
581 clocks = <&mpu_periph_clk>;
584 timer0: timer0@ffc02700 {
585 compatible = "snps,dw-apb-timer";
586 interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
587 reg = <0xffc02700 0x100>;
588 clocks = <&l4_sp_clk>;
589 clock-names = "timer";
592 timer1: timer1@ffc02800 {
593 compatible = "snps,dw-apb-timer";
594 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
595 reg = <0xffc02800 0x100>;
596 clocks = <&l4_sp_clk>;
597 clock-names = "timer";
600 timer2: timer2@ffd00000 {
601 compatible = "snps,dw-apb-timer";
602 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
603 reg = <0xffd00000 0x100>;
604 clocks = <&l4_sys_free_clk>;
605 clock-names = "timer";
608 timer3: timer3@ffd00100 {
609 compatible = "snps,dw-apb-timer";
610 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
611 reg = <0xffd01000 0x100>;
612 clocks = <&l4_sys_free_clk>;
613 clock-names = "timer";
616 uart0: serial0@ffc02000 {
617 compatible = "snps,dw-apb-uart";
618 reg = <0xffc02000 0x100>;
619 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
625 uart1: serial1@ffc02100 {
626 compatible = "snps,dw-apb-uart";
627 reg = <0xffc02100 0x100>;
628 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
631 clocks = <&l4_sp_clk>;
637 compatible = "usb-nop-xceiv";
642 compatible = "snps,dwc2";
643 reg = <0xffb00000 0xffff>;
644 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
648 phy-names = "usb2-phy";
653 compatible = "snps,dwc2";
654 reg = <0xffb40000 0xffff>;
655 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
657 phy-names = "usb2-phy";
661 watchdog0: watchdog@ffd00200 {
662 compatible = "snps,dw-wdt";
663 reg = <0xffd00200 0x100>;
664 interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
665 clocks = <&l4_sys_free_clk>;
669 watchdog1: watchdog@ffd00300 {
670 compatible = "snps,dw-wdt";
671 reg = <0xffd00300 0x100>;
672 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
673 clocks = <&l4_sys_free_clk>;