arch/arm/boot/dts/socfpga_arria10.dtsi

   1 /*
   2  * Copyright Altera Corporation (C) 2014. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include "skeleton.dtsi"
  18 #include <dt-bindings/interrupt-controller/arm-gic.h>
  19
  20 / {
  21         #address-cells = <1>;
  22         #size-cells = <1>;
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27
  28                 cpu@0 {
  29                         compatible = "arm,cortex-a9";
  30                         device_type = "cpu";
  31                         reg = <0>;
  32                         next-level-cache = <&L2>;
  33                 };
  34                 cpu@1 {
  35                         compatible = "arm,cortex-a9";
  36                         device_type = "cpu";
  37                         reg = <1>;
  38                         next-level-cache = <&L2>;
  39                 };
  40         };
  41
  42         intc: intc@ffffd000 {
  43                 compatible = "arm,cortex-a9-gic";
  44                 #interrupt-cells = <3>;
  45                 interrupt-controller;
  46                 reg = <0xffffd000 0x1000>,
  47                       <0xffffc100 0x100>;
  48         };
  49
  50         soc {
  51                 #address-cells = <1>;
  52                 #size-cells = <1>;
  53                 compatible = "simple-bus";
  54                 device_type = "soc";
  55                 interrupt-parent = <&intc>;
  56                 ranges;
  57
  58                 amba {
  59                         compatible = "arm,amba-bus";
  60                         #address-cells = <1>;
  61                         #size-cells = <1>;
  62                         ranges;
  63
  64                         pdma: pdma@ffda1000 {
  65                                 compatible = "arm,pl330", "arm,primecell";
  66                                 reg = <0xffda1000 0x1000>;
  67                                 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>,
  68                                              <0 84 IRQ_TYPE_LEVEL_HIGH>,
  69                                              <0 85 IRQ_TYPE_LEVEL_HIGH>,
  70                                              <0 86 IRQ_TYPE_LEVEL_HIGH>,
  71                                              <0 87 IRQ_TYPE_LEVEL_HIGH>,
  72                                              <0 88 IRQ_TYPE_LEVEL_HIGH>,
  73                                              <0 89 IRQ_TYPE_LEVEL_HIGH>,
  74                                              <0 90 IRQ_TYPE_LEVEL_HIGH>;
  75                                 #dma-cells = <1>;
  76                                 #dma-channels = <8>;
  77                                 #dma-requests = <32>;
  78                         };
  79                 };
  80
  81                 clkmgr@ffd04000 {
  82                                 compatible = "altr,clk-mgr";
  83                                 reg = <0xffd04000 0x1000>;
  84
  85                                 clocks {
  86                                         #address-cells = <1>;
  87                                         #size-cells = <0>;
  88
  89                                         cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk {
  90                                                 #clock-cells = <0>;
  91                                                 compatible = "fixed-clock";
  92                                         };
  93
  94                                         cb_intosc_ls_clk: cb_intosc_ls_clk {
  95                                                 #clock-cells = <0>;
  96                                                 compatible = "fixed-clock";
  97                                         };
  98
  99                                         f2s_free_clk: f2s_free_clk {
 100                                                 #clock-cells = <0>;
 101                                                 compatible = "fixed-clock";
 102                                         };
 103
 104                                         osc1: osc1 {
 105                                                 #clock-cells = <0>;
 106                                                 compatible = "fixed-clock";
 107                                         };
 108
 109                                         main_pll: main_pll {
 110                                                 #address-cells = <1>;
 111                                                 #size-cells = <0>;
 112                                                 #clock-cells = <0>;
 113                                                 compatible = "altr,socfpga-a10-pll-clock";
 114                                                 clocks = <&osc1>, <&cb_intosc_ls_clk>,
 115                                                          <&f2s_free_clk>;
 116                                                 reg = <0x40>;
 117
 118                                                 main_mpu_base_clk: main_mpu_base_clk {
 119                                                         #clock-cells = <0>;
 120                                                         compatible = "altr,socfpga-a10-perip-clk";
 121                                                         clocks = <&main_pll>;
 122                                                         div-reg = <0x140 0 11>;
 123                                                 };
 124
 125                                                 main_noc_base_clk: main_noc_base_clk {
 126                                                         #clock-cells = <0>;
 127                                                         compatible = "altr,socfpga-a10-perip-clk";
 128                                                         clocks = <&main_pll>;
 129                                                         div-reg = <0x144 0 11>;
 130                                                 };
 131
 132                                                 main_emaca_clk: main_emaca_clk {
 133                                                         #clock-cells = <0>;
 134                                                         compatible = "altr,socfpga-a10-perip-clk";
 135                                                         clocks = <&main_pll>;
 136                                                         reg = <0x68>;
 137                                                 };
 138
 139                                                 main_emacb_clk: main_emacb_clk {
 140                                                         #clock-cells = <0>;
 141                                                         compatible = "altr,socfpga-a10-perip-clk";
 142                                                         clocks = <&main_pll>;
 143                                                         reg = <0x6C>;
 144                                                 };
 145
 146                                                 main_emac_ptp_clk: main_emac_ptp_clk {
 147                                                         #clock-cells = <0>;
 148                                                         compatible = "altr,socfpga-a10-perip-clk";
 149                                                         clocks = <&main_pll>;
 150                                                         reg = <0x70>;
 151                                                 };
 152
 153                                                 main_gpio_db_clk: main_gpio_db_clk {
 154                                                         #clock-cells = <0>;
 155                                                         compatible = "altr,socfpga-a10-perip-clk";
 156                                                         clocks = <&main_pll>;
 157                                                         reg = <0x74>;
 158                                                 };
 159
 160                                                 main_sdmmc_clk: main_sdmmc_clk {
 161                                                         #clock-cells = <0>;
 162                                                         compatible = "altr,socfpga-a10-perip-clk"
 163 ;
 164                                                         clocks = <&main_pll>;
 165                                                         reg = <0x78>;
 166                                                 };
 167
 168                                                 main_s2f_usr0_clk: main_s2f_usr0_clk {
 169                                                         #clock-cells = <0>;
 170                                                         compatible = "altr,socfpga-a10-perip-clk";
 171                                                         clocks = <&main_pll>;
 172                                                         reg = <0x7C>;
 173                                                 };
 174
 175                                                 main_s2f_usr1_clk: main_s2f_usr1_clk {
 176                                                         #clock-cells = <0>;
 177                                                         compatible = "altr,socfpga-a10-perip-clk";
 178                                                         clocks = <&main_pll>;
 179                                                         reg = <0x80>;
 180                                                 };
 181
 182                                                 main_hmc_pll_ref_clk: main_hmc_pll_ref_clk {
 183                                                         #clock-cells = <0>;
 184                                                         compatible = "altr,socfpga-a10-perip-clk";
 185                                                         clocks = <&main_pll>;
 186                                                         reg = <0x84>;
 187                                                 };
 188
 189                                                 main_periph_ref_clk: main_periph_ref_clk {
 190                                                         #clock-cells = <0>;
 191                                                         compatible = "altr,socfpga-a10-perip-clk";
 192                                                         clocks = <&main_pll>;
 193                                                         reg = <0x9C>;
 194                                                 };
 195                                         };
 196
 197                                         periph_pll: periph_pll {
 198                                                 #address-cells = <1>;
 199                                                 #size-cells = <0>;
 200                                                 #clock-cells = <0>;
 201                                                 compatible = "altr,socfpga-a10-pll-clock";
 202                                                 clocks = <&osc1>, <&cb_intosc_ls_clk>,
 203                                                          <&f2s_free_clk>, <&main_periph_ref_clk>;
 204                                                 reg = <0xC0>;
 205
 206                                                 peri_mpu_base_clk: peri_mpu_base_clk {
 207                                                         #clock-cells = <0>;
 208                                                         compatible = "altr,socfpga-a10-perip-clk";
 209                                                         clocks = <&periph_pll>;
 210                                                         div-reg = <0x140 16 11>;
 211                                                 };
 212
 213                                                 peri_noc_base_clk: peri_noc_base_clk {
 214                                                         #clock-cells = <0>;
 215                                                         compatible = "altr,socfpga-a10-perip-clk";
 216                                                         clocks = <&periph_pll>;
 217                                                         div-reg = <0x144 16 11>;
 218                                                 };
 219
 220                                                 peri_emaca_clk: peri_emaca_clk {
 221                                                         #clock-cells = <0>;
 222                                                         compatible = "altr,socfpga-a10-perip-clk";
 223                                                         clocks = <&periph_pll>;
 224                                                         reg = <0xE8>;
 225                                                 };
 226
 227                                                 peri_emacb_clk: peri_emacb_clk {
 228                                                         #clock-cells = <0>;
 229                                                         compatible = "altr,socfpga-a10-perip-clk";
 230                                                         clocks = <&periph_pll>;
 231                                                         reg = <0xEC>;
 232                                                 };
 233
 234                                                 peri_emac_ptp_clk: peri_emac_ptp_clk {
 235                                                         #clock-cells = <0>;
 236                                                         compatible = "altr,socfpga-a10-perip-clk";
 237                                                         clocks = <&periph_pll>;
 238                                                         reg = <0xF0>;
 239                                                 };
 240
 241                                                 peri_gpio_db_clk: peri_gpio_db_clk {
 242                                                         #clock-cells = <0>;
 243                                                         compatible = "altr,socfpga-a10-perip-clk";
 244                                                         clocks = <&periph_pll>;
 245                                                         reg = <0xF4>;
 246                                                 };
 247
 248                                                 peri_sdmmc_clk: peri_sdmmc_clk {
 249                                                         #clock-cells = <0>;
 250                                                         compatible = "altr,socfpga-a10-perip-clk";
 251                                                         clocks = <&periph_pll>;
 252                                                         reg = <0xF8>;
 253                                                 };
 254
 255                                                 peri_s2f_usr0_clk: peri_s2f_usr0_clk {
 256                                                         #clock-cells = <0>;
 257                                                         compatible = "altr,socfpga-a10-perip-clk";
 258                                                         clocks = <&periph_pll>;
 259                                                         reg = <0xFC>;
 260                                                 };
 261
 262                                                 peri_s2f_usr1_clk: peri_s2f_usr1_clk {
 263                                                         #clock-cells = <0>;
 264                                                         compatible = "altr,socfpga-a10-perip-clk";
 265                                                         clocks = <&periph_pll>;
 266                                                         reg = <0x100>;
 267                                                 };
 268
 269                                                 peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk {
 270                                                         #clock-cells = <0>;
 271                                                         compatible = "altr,socfpga-a10-perip-clk";
 272                                                         clocks = <&periph_pll>;
 273                                                         reg = <0x104>;
 274                                                 };
 275                                         };
 276
 277                                         mpu_free_clk: mpu_free_clk {
 278                                                 #clock-cells = <0>;
 279                                                 compatible = "altr,socfpga-a10-perip-clk";
 280                                                 clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>,
 281                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 282                                                          <&f2s_free_clk>;
 283                                                 reg = <0x60>;
 284                                         };
 285
 286                                         noc_free_clk: noc_free_clk {
 287                                                 #clock-cells = <0>;
 288                                                 compatible = "altr,socfpga-a10-perip-clk";
 289                                                 clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>,
 290                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 291                                                          <&f2s_free_clk>;
 292                                                 reg = <0x64>;
 293                                         };
 294
 295                                         s2f_user1_free_clk: s2f_user1_free_clk {
 296                                                 #clock-cells = <0>;
 297                                                 compatible = "altr,socfpga-a10-perip-clk";
 298                                                 clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>,
 299                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 300                                                          <&f2s_free_clk>;
 301                                                 reg = <0x104>;
 302                                         };
 303
 304                                         sdmmc_free_clk: sdmmc_free_clk {
 305                                                 #clock-cells = <0>;
 306                                                 compatible = "altr,socfpga-a10-perip-clk";
 307                                                 clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>,
 308                                                          <&osc1>, <&cb_intosc_hs_div2_clk>,
 309                                                          <&f2s_free_clk>;
 310                                                 fixed-divider = <4>;
 311                                                 reg = <0xF8>;
 312                                         };
 313
 314                                         l4_sys_free_clk: l4_sys_free_clk {
 315                                                 #clock-cells = <0>;
 316                                                 compatible = "altr,socfpga-a10-perip-clk";
 317                                                 clocks = <&noc_free_clk>;
 318                                                 fixed-divider = <4>;
 319                                         };
 320
 321                                         l4_main_clk: l4_main_clk {
 322                                                 #clock-cells = <0>;
 323                                                 compatible = "altr,socfpga-a10-gate-clk";
 324                                                 clocks = <&noc_free_clk>;
 325                                                 div-reg = <0xA8 0 2>;
 326                                                 clk-gate = <0x48 1>;
 327                                         };
 328
 329                                         l4_mp_clk: l4_mp_clk {
 330                                                 #clock-cells = <0>;
 331                                                 compatible = "altr,socfpga-a10-gate-clk";
 332                                                 clocks = <&noc_free_clk>;
 333                                                 div-reg = <0xA8 8 2>;
 334                                                 clk-gate = <0x48 2>;
 335                                         };
 336
 337                                         l4_sp_clk: l4_sp_clk {
 338                                                 #clock-cells = <0>;
 339                                                 compatible = "altr,socfpga-a10-gate-clk";
 340                                                 clocks = <&noc_free_clk>;
 341                                                 div-reg = <0xA8 16 2>;
 342                                                 clk-gate = <0x48 3>;
 343                                         };
 344
 345                                         mpu_periph_clk: mpu_periph_clk {
 346                                                 #clock-cells = <0>;
 347                                                 compatible = "altr,socfpga-a10-gate-clk";
 348                                                 clocks = <&mpu_free_clk>;
 349                                                 fixed-divider = <4>;
 350                                                 clk-gate = <0x48 0>;
 351                                         };
 352
 353                                         sdmmc_clk: sdmmc_clk {
 354                                                 #clock-cells = <0>;
 355                                                 compatible = "altr,socfpga-a10-gate-clk";
 356                                                 clocks = <&sdmmc_free_clk>;
 357                                                 clk-gate = <0xC8 5>;
 358                                         };
 359
 360                                         qspi_clk: qspi_clk {
 361                                                 #clock-cells = <0>;
 362                                                 compatible = "altr,socfpga-a10-gate-clk";
 363                                                 clocks = <&l4_main_clk>;
 364                                                 clk-gate = <0xC8 11>;
 365                                         };
 366
 367                                         nand_clk: nand_clk {
 368                                                 #clock-cells = <0>;
 369                                                 compatible = "altr,socfpga-a10-gate-clk";
 370                                                 clocks = <&l4_mp_clk>;
 371                                                 clk-gate = <0xC8 10>;
 372                                         };
 373
 374                                         spi_m_clk: spi_m_clk {
 375                                                 #clock-cells = <0>;
 376                                                 compatible = "altr,socfpga-a10-gate-clk";
 377                                                 clocks = <&l4_main_clk>;
 378                                                 clk-gate = <0xC8 9>;
 379                                         };
 380
 381                                         usb_clk: usb_clk {
 382                                                 #clock-cells = <0>;
 383                                                 compatible = "altr,socfpga-a10-gate-clk";
 384                                                 clocks = <&l4_mp_clk>;
 385                                                 clk-gate = <0xC8 8>;
 386                                         };
 387
 388                                         s2f_usr1_clk: s2f_usr1_clk {
 389                                                 #clock-cells = <0>;
 390                                                 compatible = "altr,socfpga-a10-gate-clk";
 391                                                 clocks = <&peri_s2f_usr1_clk>;
 392                                                 clk-gate = <0xC8 6>;
 393                                         };
 394                                 };
 395                 };
 396
 397                 gmac0: ethernet@ff800000 {
 398                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
 399                         reg = <0xff800000 0x2000>;
 400                         interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
 401                         interrupt-names = "macirq";
 402                         /* Filled in by bootloader */
 403                         mac-address = [00 00 00 00 00 00];
 404                         snps,multicast-filter-bins = <256>;
 405                         snps,perfect-filter-entries = <128>;
 406                         status = "disabled";
 407                 };
 408
 409                 gmac1: ethernet@ff802000 {
 410                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
 411                         reg = <0xff802000 0x2000>;
 412                         interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
 413                         interrupt-names = "macirq";
 414                         /* Filled in by bootloader */
 415                         mac-address = [00 00 00 00 00 00];
 416                         snps,multicast-filter-bins = <256>;
 417                         snps,perfect-filter-entries = <128>;
 418                         tx-fifo-depth = <4096>;
 419                         rx-fifo-depth = <16384>;
 420                         status = "disabled";
 421                 };
 422
 423                 gmac2: ethernet@ff804000 {
 424                         compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac";
 425                         reg = <0xff804000 0x2000>;
 426                         interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
 427                         interrupt-names = "macirq";
 428                         /* Filled in by bootloader */
 429                         mac-address = [00 00 00 00 00 00];
 430                         snps,multicast-filter-bins = <256>;
 431                         snps,perfect-filter-entries = <128>;
 432                         tx-fifo-depth = <4096>;
 433                         rx-fifo-depth = <16384>;
 434                         status = "disabled";
 435                 };
 436
 437                 gpio0: gpio@ffc02900 {
 438                         #address-cells = <1>;
 439                         #size-cells = <0>;
 440                         compatible = "snps,dw-apb-gpio";
 441                         reg = <0xffc02900 0x100>;
 442                         status = "disabled";
 443
 444                         porta: gpio-controller@0 {
 445                                 compatible = "snps,dw-apb-gpio-port";
 446                                 gpio-controller;
 447                                 #gpio-cells = <2>;
 448                                 snps,nr-gpios = <29>;
 449                                 reg = <0>;
 450                                 interrupt-controller;
 451                                 #interrupt-cells = <2>;
 452                                 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
 453                         };
 454                 };
 455
 456                 gpio1: gpio@ffc02a00 {
 457                         #address-cells = <1>;
 458                         #size-cells = <0>;
 459                         compatible = "snps,dw-apb-gpio";
 460                         reg = <0xffc02a00 0x100>;
 461                         status = "disabled";
 462
 463                         portb: gpio-controller@0 {
 464                                 compatible = "snps,dw-apb-gpio-port";
 465                                 gpio-controller;
 466                                 #gpio-cells = <2>;
 467                                 snps,nr-gpios = <29>;
 468                                 reg = <0>;
 469                                 interrupt-controller;
 470                                 #interrupt-cells = <2>;
 471                                 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
 472                         };
 473                 };
 474
 475                 gpio2: gpio@ffc02b00 {
 476                         #address-cells = <1>;
 477                         #size-cells = <0>;
 478                         compatible = "snps,dw-apb-gpio";
 479                         reg = <0xffc02b00 0x100>;
 480                         status = "disabled";
 481
 482                         portc: gpio-controller@0 {
 483                                 compatible = "snps,dw-apb-gpio-port";
 484                                 gpio-controller;
 485                                 #gpio-cells = <2>;
 486                                 snps,nr-gpios = <27>;
 487                                 reg = <0>;
 488                                 interrupt-controller;
 489                                 #interrupt-cells = <2>;
 490                                 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>;
 491                         };
 492                 };
 493
 494                 i2c0: i2c@ffc02200 {
 495                         #address-cells = <1>;
 496                         #size-cells = <0>;
 497                         compatible = "snps,designware-i2c";
 498                         reg = <0xffc02200 0x100>;
 499                         interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
 500                         status = "disabled";
 501                 };
 502
 503                 i2c1: i2c@ffc02300 {
 504                         #address-cells = <1>;
 505                         #size-cells = <0>;
 506                         compatible = "snps,designware-i2c";
 507                         reg = <0xffc02300 0x100>;
 508                         interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
 509                         status = "disabled";
 510                 };
 511
 512                 i2c2: i2c@ffc02400 {
 513                         #address-cells = <1>;
 514                         #size-cells = <0>;
 515                         compatible = "snps,designware-i2c";
 516                         reg = <0xffc02400 0x100>;
 517                         interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
 518                         status = "disabled";
 519                 };
 520
 521                 i2c3: i2c@ffc02500 {
 522                         #address-cells = <1>;
 523                         #size-cells = <0>;
 524                         compatible = "snps,designware-i2c";
 525                         reg = <0xffc02500 0x100>;
 526                         interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
 527                         status = "disabled";
 528                 };
 529
 530                 i2c4: i2c@ffc02600 {
 531                         #address-cells = <1>;
 532                         #size-cells = <0>;
 533                         compatible = "snps,designware-i2c";
 534                         reg = <0xffc02600 0x100>;
 535                         interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
 536                         status = "disabled";
 537                 };
 538
 539                 L2: l2-cache@fffff000 {
 540                         compatible = "arm,pl310-cache";
 541                         reg = <0xfffff000 0x1000>;
 542                         interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
 543                         cache-unified;
 544                         cache-level = <2>;
 545                 };
 546
 547                 mmc: dwmmc0@ff808000 {
 548                         #address-cells = <1>;
 549                         #size-cells = <0>;
 550                         compatible = "altr,socfpga-dw-mshc";
 551                         reg = <0xff808000 0x1000>;
 552                         interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
 553                         fifo-depth = <0x400>;
 554                         clocks = <&l4_mp_clk>, <&sdmmc_free_clk>;
 555                         clock-names = "biu", "ciu";
 556                         status = "disabled";
 557                 };
 558
 559                 ocram: sram@ffe00000 {
 560                         compatible = "mmio-sram";
 561                         reg = <0xffe00000 0x40000>;
 562                 };
 563
 564                 rst: rstmgr@ffd05000 {
 565                         #reset-cells = <1>;
 566                         compatible = "altr,rst-mgr";
 567                         reg = <0xffd05000 0x100>;
 568                 };
 569
 570                 sysmgr: sysmgr@ffd06000 {
 571                         compatible = "altr,sys-mgr", "syscon";
 572                         reg = <0xffd06000 0x300>;
 573                         cpu1-start-addr = <0xffd06230>;
 574                 };
 575
 576                 /* Local timer */
 577                 timer@ffffc600 {
 578                         compatible = "arm,cortex-a9-twd-timer";
 579                         reg = <0xffffc600 0x100>;
 580                         interrupts = <1 13 0xf04>;
 581                         clocks = <&mpu_periph_clk>;
 582                 };
 583
 584                 timer0: timer0@ffc02700 {
 585                         compatible = "snps,dw-apb-timer";
 586                         interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>;
 587                         reg = <0xffc02700 0x100>;
 588                         clocks = <&l4_sp_clk>;
 589                         clock-names = "timer";
 590                 };
 591
 592                 timer1: timer1@ffc02800 {
 593                         compatible = "snps,dw-apb-timer";
 594                         interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>;
 595                         reg = <0xffc02800 0x100>;
 596                         clocks = <&l4_sp_clk>;
 597                         clock-names = "timer";
 598                 };
 599
 600                 timer2: timer2@ffd00000 {
 601                         compatible = "snps,dw-apb-timer";
 602                         interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>;
 603                         reg = <0xffd00000 0x100>;
 604                         clocks = <&l4_sys_free_clk>;
 605                         clock-names = "timer";
 606                 };
 607
 608                 timer3: timer3@ffd00100 {
 609                         compatible = "snps,dw-apb-timer";
 610                         interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>;
 611                         reg = <0xffd01000 0x100>;
 612                         clocks = <&l4_sys_free_clk>;
 613                         clock-names = "timer";
 614                 };
 615
 616                 uart0: serial0@ffc02000 {
 617                         compatible = "snps,dw-apb-uart";
 618                         reg = <0xffc02000 0x100>;
 619                         interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
 620                         reg-shift = <2>;
 621                         reg-io-width = <4>;
 622                         status = "disabled";
 623                 };
 624
 625                 uart1: serial1@ffc02100 {
 626                         compatible = "snps,dw-apb-uart";
 627                         reg = <0xffc02100 0x100>;
 628                         interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
 629                         reg-shift = <2>;
 630                         reg-io-width = <4>;
 631                         clocks = <&l4_sp_clk>;
 632                         status = "disabled";
 633                 };
 634
 635                 usbphy0: usbphy@0 {
 636                         #phy-cells = <0>;
 637                         compatible = "usb-nop-xceiv";
 638                         status = "okay";
 639                 };
 640
 641                 usb0: usb@ffb00000 {
 642                         compatible = "snps,dwc2";
 643                         reg = <0xffb00000 0xffff>;
 644                         interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
 645                         clocks = <&usb_clk>;
 646                         clock-names = "otg";
 647                         phys = <&usbphy0>;
 648                         phy-names = "usb2-phy";
 649                         status = "disabled";
 650                 };
 651
 652                 usb1: usb@ffb40000 {
 653                         compatible = "snps,dwc2";
 654                         reg = <0xffb40000 0xffff>;
 655                         interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
 656                         phys = <&usbphy0>;
 657                         phy-names = "usb2-phy";
 658                         status = "disabled";
 659                 };
 660
 661                 watchdog0: watchdog@ffd00200 {
 662                         compatible = "snps,dw-wdt";
 663                         reg = <0xffd00200 0x100>;
 664                         interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
 665                         clocks = <&l4_sys_free_clk>;
 666                         status = "disabled";
 667                 };
 668
 669                 watchdog1: watchdog@ffd00300 {
 670                         compatible = "snps,dw-wdt";
 671                         reg = <0xffd00300 0x100>;
 672                         interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
 673                         clocks = <&l4_sys_free_clk>;
 674                         status = "disabled";
 675                 };
 676         };
 677 };