2 * DTS file for all SPEAr13xx SoCs
4 * Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 /include/ "skeleton.dtsi"
17 interrupt-parent = <&gic>;
24 compatible = "arm,cortex-a9";
27 next-level-cache = <&L2>;
31 compatible = "arm,cortex-a9";
34 next-level-cache = <&L2>;
38 gic: interrupt-controller@ec801000 {
39 compatible = "arm,cortex-a9-gic";
41 #interrupt-cells = <3>;
42 reg = < 0xec801000 0x1000 >,
43 < 0xec800100 0x0100 >;
47 compatible = "arm,cortex-a9-pmu";
48 interrupts = <0 6 0x04
53 compatible = "arm,pl310-cache";
54 reg = <0xed000000 0x1000>;
61 device_type = "memory";
66 bootargs = "console=ttyAMA0,115200";
70 compatible = "st,cpufreq-spear";
71 cpufreq_tbl = < 166000
84 compatible = "simple-bus";
85 ranges = <0x50000000 0x50000000 0x10000000
86 0xb0000000 0xb0000000 0x10000000
87 0xd0000000 0xd0000000 0x02000000
88 0xd8000000 0xd8000000 0x01000000
89 0xe0000000 0xe0000000 0x10000000>;
92 compatible = "st,sdhci-spear";
93 reg = <0xb3000000 0x100>;
94 interrupts = <0 28 0x4>;
99 compatible = "arasan,cf-spear1340";
100 reg = <0xb2800000 0x1000>;
101 interrupts = <0 29 0x4>;
103 dmas = <&dwdma0 0 0 0 0>;
107 dwdma0: dma@ea800000 {
108 compatible = "snps,dma-spear1340";
109 reg = <0xea800000 0x1000>;
110 interrupts = <0 19 0x4>;
116 chan_allocation_order = <1>;
118 block_size = <0xfff>;
120 data_width = <3 3 0 0>;
124 compatible = "snps,dma-spear1340";
125 reg = <0xeb000000 0x1000>;
126 interrupts = <0 59 0x4>;
133 chan_allocation_order = <1>;
135 block_size = <0xfff>;
136 data_width = <3 3 0 0>;
139 fsmc: flash@b0000000 {
140 compatible = "st,spear600-fsmc-nand";
141 #address-cells = <1>;
143 reg = <0xb0000000 0x1000 /* FSMC Register*/
144 0xb0800000 0x0010 /* NAND Base DATA */
145 0xb0820000 0x0010 /* NAND Base ADDR */
146 0xb0810000 0x0010>; /* NAND Base CMD */
147 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
148 interrupts = <0 20 0x4
156 gmac0: eth@e2000000 {
157 compatible = "st,spear600-gmac";
158 reg = <0xe2000000 0x8000>;
159 interrupts = <0 33 0x4
161 interrupt-names = "macirq", "eth_wake_irq";
166 compatible = "st,pcm-audio";
167 #address-cells = <0>;
172 smi: flash@ea000000 {
173 compatible = "st,spear600-smi";
174 #address-cells = <1>;
176 reg = <0xea000000 0x1000>;
177 interrupts = <0 30 0x4>;
182 compatible = "st,spear600-ehci", "usb-ehci";
183 reg = <0xe4800000 0x1000>;
184 interrupts = <0 64 0x4>;
190 compatible = "st,spear600-ehci", "usb-ehci";
191 reg = <0xe5800000 0x1000>;
192 interrupts = <0 66 0x4>;
198 compatible = "st,spear600-ohci", "usb-ohci";
199 reg = <0xe4000000 0x1000>;
200 interrupts = <0 65 0x4>;
206 compatible = "st,spear600-ohci", "usb-ohci";
207 reg = <0xe5000000 0x1000>;
208 interrupts = <0 67 0x4>;
214 #address-cells = <1>;
216 compatible = "simple-bus";
217 ranges = <0x50000000 0x50000000 0x10000000
218 0xb0000000 0xb0000000 0x10000000
219 0xd0000000 0xd0000000 0x02000000
220 0xd8000000 0xd8000000 0x01000000
221 0xe0000000 0xe0000000 0x10000000>;
223 gpio0: gpio@e0600000 {
224 compatible = "arm,pl061", "arm,primecell";
225 reg = <0xe0600000 0x1000>;
226 interrupts = <0 24 0x4>;
229 interrupt-controller;
230 #interrupt-cells = <2>;
234 gpio1: gpio@e0680000 {
235 compatible = "arm,pl061", "arm,primecell";
236 reg = <0xe0680000 0x1000>;
237 interrupts = <0 25 0x4>;
240 interrupt-controller;
241 #interrupt-cells = <2>;
246 compatible = "st,spear300-kbd";
247 reg = <0xe0300000 0x1000>;
248 interrupts = <0 52 0x4>;
253 #address-cells = <1>;
255 compatible = "snps,designware-i2c";
256 reg = <0xe0280000 0x1000>;
257 interrupts = <0 41 0x4>;
262 compatible = "st,designware-i2s";
263 reg = <0xe0180000 0x1000>;
264 interrupt-names = "play_irq", "record_irq";
265 interrupts = <0 10 0x4
271 compatible = "st,designware-i2s";
272 reg = <0xe0200000 0x1000>;
273 interrupt-names = "play_irq", "record_irq";
274 interrupts = <0 26 0x4
280 compatible = "arm,pl022", "arm,primecell";
281 reg = <0xe0100000 0x1000>;
282 #address-cells = <1>;
284 interrupts = <0 31 0x4>;
286 dmas = <&dwdma0 0x2000 0 0 0>, /* 0x4 << 11 */
287 <&dwdma0 0x0280 0 0 0>; /* 0x5 << 7 */
288 dma-names = "tx", "rx";
292 compatible = "st,spear600-rtc";
293 reg = <0xe0580000 0x1000>;
294 interrupts = <0 36 0x4>;
299 compatible = "arm,pl011", "arm,primecell";
300 reg = <0xe0000000 0x1000>;
301 interrupts = <0 35 0x4>;
306 compatible = "st,spear600-adc";
307 reg = <0xe0080000 0x1000>;
308 interrupts = <0 12 0x4>;
313 compatible = "st,spear-timer";
314 reg = <0xe0380000 0x400>;
315 interrupts = <0 37 0x4>;
319 compatible = "arm,cortex-a9-twd-timer";
320 reg = <0xec800600 0x20>;
321 interrupts = <1 13 0x4>;
326 compatible = "arm,cortex-a9-twd-wdt";
327 reg = <0xec800620 0x20>;
332 compatible = "st,thermal-spear1340";
333 reg = <0xe07008c4 0x4>;
334 thermal_flags = <0x7000>;