2 * Copyright (C) 2014 STMicroelectronics Limited.
3 * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * publishhed by the Free Software Foundation.
9 #include "stih407-clock.dtsi"
10 #include "stih407-pinctrl.dtsi"
20 compatible = "arm,cortex-a9";
25 compatible = "arm,cortex-a9";
30 intc: interrupt-controller@08761000 {
31 compatible = "arm,cortex-a9-gic";
32 #interrupt-cells = <3>;
34 reg = <0x08761000 0x1000>, <0x08760100 0x100>;
38 compatible = "arm,cortex-a9-scu";
39 reg = <0x08760000 0x1000>;
43 interrupt-parent = <&intc>;
44 compatible = "arm,cortex-a9-global-timer";
45 reg = <0x08760200 0x100>;
46 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
47 clocks = <&arm_periph_clk>;
50 l2: cache-controller {
51 compatible = "arm,pl310-cache";
52 reg = <0x08762000 0x1000>;
53 arm,data-latency = <3 3 3>;
54 arm,tag-latency = <2 2 2>;
62 interrupt-parent = <&intc>;
64 compatible = "simple-bus";
66 syscfg_sbc: sbc-syscfg@9620000 {
67 compatible = "st,stih407-sbc-syscfg", "syscon";
68 reg = <0x9620000 0x1000>;
71 syscfg_front: front-syscfg@9280000 {
72 compatible = "st,stih407-front-syscfg", "syscon";
73 reg = <0x9280000 0x1000>;
76 syscfg_rear: rear-syscfg@9290000 {
77 compatible = "st,stih407-rear-syscfg", "syscon";
78 reg = <0x9290000 0x1000>;
81 syscfg_flash: flash-syscfg@92a0000 {
82 compatible = "st,stih407-flash-syscfg", "syscon";
83 reg = <0x92a0000 0x1000>;
86 syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
87 compatible = "st,stih407-sbc-reg-syscfg", "syscon";
88 reg = <0x9600000 0x1000>;
91 syscfg_core: core-syscfg@92b0000 {
92 compatible = "st,stih407-core-syscfg", "syscon";
93 reg = <0x92b0000 0x1000>;
96 syscfg_lpm: lpm-syscfg@94b5100 {
97 compatible = "st,stih407-lpm-syscfg", "syscon";
98 reg = <0x94b5100 0x1000>;
102 compatible = "st,asc";
103 reg = <0x9830000 0x2c>;
104 interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_serial0>;
107 clocks = <&clk_ext2f_a9>;
113 compatible = "st,asc";
114 reg = <0x9831000 0x2c>;
115 interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_serial1>;
118 clocks = <&clk_ext2f_a9>;
124 compatible = "st,asc";
125 reg = <0x9832000 0x2c>;
126 interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
127 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_serial2>;
129 clocks = <&clk_ext2f_a9>;
134 /* SBC_ASC0 - UART10 */
135 sbc_serial0: serial@9530000 {
136 compatible = "st,asc";
137 reg = <0x9530000 0x2c>;
138 interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_sbc_serial0>;
141 clocks = <&clk_sysin>;
147 compatible = "st,asc";
148 reg = <0x9531000 0x2c>;
149 interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_sbc_serial1>;
152 clocks = <&clk_sysin>;
158 compatible = "st,comms-ssc4-i2c";
159 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
160 reg = <0x9840000 0x110>;
161 clocks = <&clk_ext2f_a9>;
163 clock-frequency = <400000>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_i2c0_default>;
171 compatible = "st,comms-ssc4-i2c";
172 reg = <0x9841000 0x110>;
173 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
174 clocks = <&clk_ext2f_a9>;
176 clock-frequency = <400000>;
177 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_i2c1_default>;
184 compatible = "st,comms-ssc4-i2c";
185 reg = <0x9842000 0x110>;
186 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
187 clocks = <&clk_ext2f_a9>;
189 clock-frequency = <400000>;
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_i2c2_default>;
197 compatible = "st,comms-ssc4-i2c";
198 reg = <0x9843000 0x110>;
199 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&clk_ext2f_a9>;
202 clock-frequency = <400000>;
203 pinctrl-names = "default";
204 pinctrl-0 = <&pinctrl_i2c3_default>;
210 compatible = "st,comms-ssc4-i2c";
211 reg = <0x9844000 0x110>;
212 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&clk_ext2f_a9>;
215 clock-frequency = <400000>;
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_i2c4_default>;
223 compatible = "st,comms-ssc4-i2c";
224 reg = <0x9845000 0x110>;
225 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
226 clocks = <&clk_ext2f_a9>;
228 clock-frequency = <400000>;
229 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_i2c5_default>;
238 compatible = "st,comms-ssc4-i2c";
239 reg = <0x9540000 0x110>;
240 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&clk_sysin>;
243 clock-frequency = <400000>;
244 pinctrl-names = "default";
245 pinctrl-0 = <&pinctrl_i2c10_default>;
251 compatible = "st,comms-ssc4-i2c";
252 reg = <0x9541000 0x110>;
253 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
254 clocks = <&clk_sysin>;
256 clock-frequency = <400000>;
257 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_i2c11_default>;