2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public
21 * License along with this library; if not, write to the Free
22 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
27 * b) Permission is hereby granted, free of charge, to any person
28 * obtaining a copy of this software and associated documentation
29 * files (the "Software"), to deal in the Software without
30 * restriction, including without limitation the rights to use,
31 * copy, modify, merge, publish, distribute, sublicense, and/or
32 * sell copies of the Software, and to permit persons to whom the
33 * Software is furnished to do so, subject to the following
36 * The above copyright notice and this permission notice shall be
37 * included in all copies or substantial portions of the Software.
39 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
41 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
42 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
43 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
44 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
45 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
46 * OTHER DEALINGS IN THE SOFTWARE.
49 #include "skeleton.dtsi"
51 #include <dt-bindings/thermal/thermal.h>
53 #include <dt-bindings/dma/sun4i-a10.h>
54 #include <dt-bindings/pinctrl/sun4i-a10.h>
57 interrupt-parent = <&intc>;
69 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
70 allwinner,pipeline = "de_be0-lcd0-hdmi";
71 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
77 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
78 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
79 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
80 <&ahb_gates 44>, <&ahb_gates 46>;
85 compatible = "allwinner,simple-framebuffer",
87 allwinner,pipeline = "de_fe0-de_be0-lcd0";
88 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
94 compatible = "allwinner,simple-framebuffer",
96 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
97 clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
98 <&ahb_gates 44>, <&ahb_gates 46>;
104 #address-cells = <1>;
108 compatible = "arm,cortex-a8";
111 clock-latency = <244144>; /* 8 32k periods */
119 #cooling-cells = <2>;
120 cooling-min-level = <0>;
121 cooling-max-level = <3>;
128 polling-delay-passive = <250>;
129 polling-delay = <1000>;
130 thermal-sensors = <&rtp>;
134 trip = <&cpu_alert0>;
135 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
140 cpu_alert0: cpu_alert0 {
142 temperature = <850000>;
149 temperature = <100000>;
158 reg = <0x40000000 0x80000000>;
162 #address-cells = <1>;
167 * This is a dummy clock, to be used as placeholder on
168 * other mux clocks when a specific parent clock is not
169 * yet implemented. It should be dropped when the driver
174 compatible = "fixed-clock";
175 clock-frequency = <0>;
178 osc24M: clk@01c20050 {
180 compatible = "allwinner,sun4i-a10-osc-clk";
181 reg = <0x01c20050 0x4>;
182 clock-frequency = <24000000>;
183 clock-output-names = "osc24M";
188 compatible = "fixed-clock";
189 clock-frequency = <32768>;
190 clock-output-names = "osc32k";
195 compatible = "allwinner,sun4i-a10-pll1-clk";
196 reg = <0x01c20000 0x4>;
198 clock-output-names = "pll1";
203 compatible = "allwinner,sun4i-a10-pll1-clk";
204 reg = <0x01c20018 0x4>;
206 clock-output-names = "pll4";
211 compatible = "allwinner,sun4i-a10-pll5-clk";
212 reg = <0x01c20020 0x4>;
214 clock-output-names = "pll5_ddr", "pll5_other";
219 compatible = "allwinner,sun4i-a10-pll6-clk";
220 reg = <0x01c20028 0x4>;
222 clock-output-names = "pll6_sata", "pll6_other", "pll6";
228 compatible = "allwinner,sun4i-a10-cpu-clk";
229 reg = <0x01c20054 0x4>;
230 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
231 clock-output-names = "cpu";
236 compatible = "allwinner,sun4i-a10-axi-clk";
237 reg = <0x01c20054 0x4>;
239 clock-output-names = "axi";
242 axi_gates: clk@01c2005c {
244 compatible = "allwinner,sun4i-a10-axi-gates-clk";
245 reg = <0x01c2005c 0x4>;
247 clock-output-names = "axi_dram";
252 compatible = "allwinner,sun4i-a10-ahb-clk";
253 reg = <0x01c20054 0x4>;
255 clock-output-names = "ahb";
258 ahb_gates: clk@01c20060 {
260 compatible = "allwinner,sun4i-a10-ahb-gates-clk";
261 reg = <0x01c20060 0x8>;
263 clock-output-names = "ahb_usb0", "ahb_ehci0",
264 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
265 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
266 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
267 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
268 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
269 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
270 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
271 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
272 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
273 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
276 apb0: apb0@01c20054 {
278 compatible = "allwinner,sun4i-a10-apb0-clk";
279 reg = <0x01c20054 0x4>;
281 clock-output-names = "apb0";
284 apb0_gates: clk@01c20068 {
286 compatible = "allwinner,sun4i-a10-apb0-gates-clk";
287 reg = <0x01c20068 0x4>;
289 clock-output-names = "apb0_codec", "apb0_spdif",
290 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
291 "apb0_ir1", "apb0_keypad";
296 compatible = "allwinner,sun4i-a10-apb1-clk";
297 reg = <0x01c20058 0x4>;
298 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
299 clock-output-names = "apb1";
302 apb1_gates: clk@01c2006c {
304 compatible = "allwinner,sun4i-a10-apb1-gates-clk";
305 reg = <0x01c2006c 0x4>;
307 clock-output-names = "apb1_i2c0", "apb1_i2c1",
308 "apb1_i2c2", "apb1_can", "apb1_scr",
309 "apb1_ps20", "apb1_ps21", "apb1_uart0",
310 "apb1_uart1", "apb1_uart2", "apb1_uart3",
311 "apb1_uart4", "apb1_uart5", "apb1_uart6",
315 nand_clk: clk@01c20080 {
317 compatible = "allwinner,sun4i-a10-mod0-clk";
318 reg = <0x01c20080 0x4>;
319 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
320 clock-output-names = "nand";
323 ms_clk: clk@01c20084 {
325 compatible = "allwinner,sun4i-a10-mod0-clk";
326 reg = <0x01c20084 0x4>;
327 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
328 clock-output-names = "ms";
331 mmc0_clk: clk@01c20088 {
333 compatible = "allwinner,sun4i-a10-mmc-clk";
334 reg = <0x01c20088 0x4>;
335 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
336 clock-output-names = "mmc0",
341 mmc1_clk: clk@01c2008c {
343 compatible = "allwinner,sun4i-a10-mmc-clk";
344 reg = <0x01c2008c 0x4>;
345 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
346 clock-output-names = "mmc1",
351 mmc2_clk: clk@01c20090 {
353 compatible = "allwinner,sun4i-a10-mmc-clk";
354 reg = <0x01c20090 0x4>;
355 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
356 clock-output-names = "mmc2",
361 mmc3_clk: clk@01c20094 {
363 compatible = "allwinner,sun4i-a10-mmc-clk";
364 reg = <0x01c20094 0x4>;
365 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
366 clock-output-names = "mmc3",
371 ts_clk: clk@01c20098 {
373 compatible = "allwinner,sun4i-a10-mod0-clk";
374 reg = <0x01c20098 0x4>;
375 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
376 clock-output-names = "ts";
379 ss_clk: clk@01c2009c {
381 compatible = "allwinner,sun4i-a10-mod0-clk";
382 reg = <0x01c2009c 0x4>;
383 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
384 clock-output-names = "ss";
387 spi0_clk: clk@01c200a0 {
389 compatible = "allwinner,sun4i-a10-mod0-clk";
390 reg = <0x01c200a0 0x4>;
391 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
392 clock-output-names = "spi0";
395 spi1_clk: clk@01c200a4 {
397 compatible = "allwinner,sun4i-a10-mod0-clk";
398 reg = <0x01c200a4 0x4>;
399 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
400 clock-output-names = "spi1";
403 spi2_clk: clk@01c200a8 {
405 compatible = "allwinner,sun4i-a10-mod0-clk";
406 reg = <0x01c200a8 0x4>;
407 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
408 clock-output-names = "spi2";
411 pata_clk: clk@01c200ac {
413 compatible = "allwinner,sun4i-a10-mod0-clk";
414 reg = <0x01c200ac 0x4>;
415 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
416 clock-output-names = "pata";
419 ir0_clk: clk@01c200b0 {
421 compatible = "allwinner,sun4i-a10-mod0-clk";
422 reg = <0x01c200b0 0x4>;
423 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
424 clock-output-names = "ir0";
427 ir1_clk: clk@01c200b4 {
429 compatible = "allwinner,sun4i-a10-mod0-clk";
430 reg = <0x01c200b4 0x4>;
431 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
432 clock-output-names = "ir1";
435 usb_clk: clk@01c200cc {
438 compatible = "allwinner,sun4i-a10-usb-clk";
439 reg = <0x01c200cc 0x4>;
441 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
444 spi3_clk: clk@01c200d4 {
446 compatible = "allwinner,sun4i-a10-mod0-clk";
447 reg = <0x01c200d4 0x4>;
448 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
449 clock-output-names = "spi3";
454 compatible = "simple-bus";
455 #address-cells = <1>;
459 dma: dma-controller@01c02000 {
460 compatible = "allwinner,sun4i-a10-dma";
461 reg = <0x01c02000 0x1000>;
463 clocks = <&ahb_gates 6>;
468 compatible = "allwinner,sun4i-a10-spi";
469 reg = <0x01c05000 0x1000>;
471 clocks = <&ahb_gates 20>, <&spi0_clk>;
472 clock-names = "ahb", "mod";
473 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
474 <&dma SUN4I_DMA_DEDICATED 26>;
475 dma-names = "rx", "tx";
477 #address-cells = <1>;
482 compatible = "allwinner,sun4i-a10-spi";
483 reg = <0x01c06000 0x1000>;
485 clocks = <&ahb_gates 21>, <&spi1_clk>;
486 clock-names = "ahb", "mod";
487 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
488 <&dma SUN4I_DMA_DEDICATED 8>;
489 dma-names = "rx", "tx";
491 #address-cells = <1>;
495 emac: ethernet@01c0b000 {
496 compatible = "allwinner,sun4i-a10-emac";
497 reg = <0x01c0b000 0x1000>;
499 clocks = <&ahb_gates 17>;
503 mdio: mdio@01c0b080 {
504 compatible = "allwinner,sun4i-a10-mdio";
505 reg = <0x01c0b080 0x14>;
507 #address-cells = <1>;
512 compatible = "allwinner,sun4i-a10-mmc";
513 reg = <0x01c0f000 0x1000>;
514 clocks = <&ahb_gates 8>,
527 compatible = "allwinner,sun4i-a10-mmc";
528 reg = <0x01c10000 0x1000>;
529 clocks = <&ahb_gates 9>,
542 compatible = "allwinner,sun4i-a10-mmc";
543 reg = <0x01c11000 0x1000>;
544 clocks = <&ahb_gates 10>,
557 compatible = "allwinner,sun4i-a10-mmc";
558 reg = <0x01c12000 0x1000>;
559 clocks = <&ahb_gates 11>,
571 usbphy: phy@01c13400 {
573 compatible = "allwinner,sun4i-a10-usb-phy";
574 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
575 reg-names = "phy_ctrl", "pmu1", "pmu2";
576 clocks = <&usb_clk 8>;
577 clock-names = "usb_phy";
578 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
579 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
583 ehci0: usb@01c14000 {
584 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
585 reg = <0x01c14000 0x100>;
587 clocks = <&ahb_gates 1>;
593 ohci0: usb@01c14400 {
594 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
595 reg = <0x01c14400 0x100>;
597 clocks = <&usb_clk 6>, <&ahb_gates 2>;
604 compatible = "allwinner,sun4i-a10-spi";
605 reg = <0x01c17000 0x1000>;
607 clocks = <&ahb_gates 22>, <&spi2_clk>;
608 clock-names = "ahb", "mod";
609 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
610 <&dma SUN4I_DMA_DEDICATED 28>;
611 dma-names = "rx", "tx";
613 #address-cells = <1>;
617 ahci: sata@01c18000 {
618 compatible = "allwinner,sun4i-a10-ahci";
619 reg = <0x01c18000 0x1000>;
621 clocks = <&pll6 0>, <&ahb_gates 25>;
625 ehci1: usb@01c1c000 {
626 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
627 reg = <0x01c1c000 0x100>;
629 clocks = <&ahb_gates 3>;
635 ohci1: usb@01c1c400 {
636 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
637 reg = <0x01c1c400 0x100>;
639 clocks = <&usb_clk 7>, <&ahb_gates 4>;
646 compatible = "allwinner,sun4i-a10-spi";
647 reg = <0x01c1f000 0x1000>;
649 clocks = <&ahb_gates 23>, <&spi3_clk>;
650 clock-names = "ahb", "mod";
651 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
652 <&dma SUN4I_DMA_DEDICATED 30>;
653 dma-names = "rx", "tx";
655 #address-cells = <1>;
659 intc: interrupt-controller@01c20400 {
660 compatible = "allwinner,sun4i-a10-ic";
661 reg = <0x01c20400 0x400>;
662 interrupt-controller;
663 #interrupt-cells = <1>;
666 pio: pinctrl@01c20800 {
667 compatible = "allwinner,sun4i-a10-pinctrl";
668 reg = <0x01c20800 0x400>;
670 clocks = <&apb0_gates 5>;
672 interrupt-controller;
673 #interrupt-cells = <2>;
677 pwm0_pins_a: pwm0@0 {
678 allwinner,pins = "PB2";
679 allwinner,function = "pwm";
680 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
681 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
684 pwm1_pins_a: pwm1@0 {
685 allwinner,pins = "PI3";
686 allwinner,function = "pwm";
687 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
688 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
691 uart0_pins_a: uart0@0 {
692 allwinner,pins = "PB22", "PB23";
693 allwinner,function = "uart0";
694 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
695 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
698 uart0_pins_b: uart0@1 {
699 allwinner,pins = "PF2", "PF4";
700 allwinner,function = "uart0";
701 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
702 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
705 uart1_pins_a: uart1@0 {
706 allwinner,pins = "PA10", "PA11";
707 allwinner,function = "uart1";
708 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
709 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
712 i2c0_pins_a: i2c0@0 {
713 allwinner,pins = "PB0", "PB1";
714 allwinner,function = "i2c0";
715 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
716 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
719 i2c1_pins_a: i2c1@0 {
720 allwinner,pins = "PB18", "PB19";
721 allwinner,function = "i2c1";
722 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
723 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
726 i2c2_pins_a: i2c2@0 {
727 allwinner,pins = "PB20", "PB21";
728 allwinner,function = "i2c2";
729 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
730 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
733 emac_pins_a: emac0@0 {
734 allwinner,pins = "PA0", "PA1", "PA2",
735 "PA3", "PA4", "PA5", "PA6",
736 "PA7", "PA8", "PA9", "PA10",
737 "PA11", "PA12", "PA13", "PA14",
739 allwinner,function = "emac";
740 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
741 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
744 mmc0_pins_a: mmc0@0 {
745 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
746 allwinner,function = "mmc0";
747 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
748 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
751 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
752 allwinner,pins = "PH1";
753 allwinner,function = "gpio_in";
754 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
755 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
759 allwinner,pins = "PB3","PB4";
760 allwinner,function = "ir0";
761 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
762 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
766 allwinner,pins = "PB22","PB23";
767 allwinner,function = "ir1";
768 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
769 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
772 spi0_pins_a: spi0@0 {
773 allwinner,pins = "PI10", "PI11", "PI12", "PI13";
774 allwinner,function = "spi0";
775 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
776 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
779 spi1_pins_a: spi1@0 {
780 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
781 allwinner,function = "spi1";
782 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
783 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
786 spi2_pins_a: spi2@0 {
787 allwinner,pins = "PB14", "PB15", "PB16", "PB17";
788 allwinner,function = "spi2";
789 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
790 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
793 spi2_pins_b: spi2@1 {
794 allwinner,pins = "PC19", "PC20", "PC21", "PC22";
795 allwinner,function = "spi2";
796 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
797 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
800 ps20_pins_a: ps20@0 {
801 allwinner,pins = "PI20", "PI21";
802 allwinner,function = "ps2";
803 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
804 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
807 ps21_pins_a: ps21@0 {
808 allwinner,pins = "PH12", "PH13";
809 allwinner,function = "ps2";
810 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
811 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
816 compatible = "allwinner,sun4i-a10-timer";
817 reg = <0x01c20c00 0x90>;
822 wdt: watchdog@01c20c90 {
823 compatible = "allwinner,sun4i-a10-wdt";
824 reg = <0x01c20c90 0x10>;
828 compatible = "allwinner,sun4i-a10-rtc";
829 reg = <0x01c20d00 0x20>;
834 compatible = "allwinner,sun4i-a10-pwm";
835 reg = <0x01c20e00 0xc>;
842 compatible = "allwinner,sun4i-a10-ir";
843 clocks = <&apb0_gates 6>, <&ir0_clk>;
844 clock-names = "apb", "ir";
846 reg = <0x01c21800 0x40>;
851 compatible = "allwinner,sun4i-a10-ir";
852 clocks = <&apb0_gates 7>, <&ir1_clk>;
853 clock-names = "apb", "ir";
855 reg = <0x01c21c00 0x40>;
859 lradc: lradc@01c22800 {
860 compatible = "allwinner,sun4i-a10-lradc-keys";
861 reg = <0x01c22800 0x100>;
866 sid: eeprom@01c23800 {
867 compatible = "allwinner,sun4i-a10-sid";
868 reg = <0x01c23800 0x10>;
872 compatible = "allwinner,sun4i-a10-ts";
873 reg = <0x01c25000 0x100>;
875 #thermal-sensor-cells = <0>;
878 uart0: serial@01c28000 {
879 compatible = "snps,dw-apb-uart";
880 reg = <0x01c28000 0x400>;
884 clocks = <&apb1_gates 16>;
888 uart1: serial@01c28400 {
889 compatible = "snps,dw-apb-uart";
890 reg = <0x01c28400 0x400>;
894 clocks = <&apb1_gates 17>;
898 uart2: serial@01c28800 {
899 compatible = "snps,dw-apb-uart";
900 reg = <0x01c28800 0x400>;
904 clocks = <&apb1_gates 18>;
908 uart3: serial@01c28c00 {
909 compatible = "snps,dw-apb-uart";
910 reg = <0x01c28c00 0x400>;
914 clocks = <&apb1_gates 19>;
918 uart4: serial@01c29000 {
919 compatible = "snps,dw-apb-uart";
920 reg = <0x01c29000 0x400>;
924 clocks = <&apb1_gates 20>;
928 uart5: serial@01c29400 {
929 compatible = "snps,dw-apb-uart";
930 reg = <0x01c29400 0x400>;
934 clocks = <&apb1_gates 21>;
938 uart6: serial@01c29800 {
939 compatible = "snps,dw-apb-uart";
940 reg = <0x01c29800 0x400>;
944 clocks = <&apb1_gates 22>;
948 uart7: serial@01c29c00 {
949 compatible = "snps,dw-apb-uart";
950 reg = <0x01c29c00 0x400>;
954 clocks = <&apb1_gates 23>;
959 compatible = "allwinner,sun4i-a10-i2c";
960 reg = <0x01c2ac00 0x400>;
962 clocks = <&apb1_gates 0>;
964 #address-cells = <1>;
969 compatible = "allwinner,sun4i-a10-i2c";
970 reg = <0x01c2b000 0x400>;
972 clocks = <&apb1_gates 1>;
974 #address-cells = <1>;
979 compatible = "allwinner,sun4i-a10-i2c";
980 reg = <0x01c2b400 0x400>;
982 clocks = <&apb1_gates 2>;
984 #address-cells = <1>;
989 compatible = "allwinner,sun4i-a10-ps2";
990 reg = <0x01c2a000 0x400>;
992 clocks = <&apb1_gates 6>;
997 compatible = "allwinner,sun4i-a10-ps2";
998 reg = <0x01c2a400 0x400>;
1000 clocks = <&apb1_gates 7>;
1001 status = "disabled";