2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include "skeleton.dtsi"
15 #include <dt-bindings/thermal/thermal.h>
17 #include <dt-bindings/dma/sun4i-a10.h>
18 #include <dt-bindings/pinctrl/sun4i-a10.h>
21 interrupt-parent = <&intc>;
33 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
34 allwinner,pipeline = "de_be0-lcd0-hdmi";
35 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
41 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
42 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
43 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
44 <&ahb_gates 44>, <&ahb_gates 46>;
49 compatible = "allwinner,simple-framebuffer",
51 allwinner,pipeline = "de_fe0-de_be0-lcd0";
52 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
58 compatible = "allwinner,simple-framebuffer",
60 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
61 clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
62 <&ahb_gates 44>, <&ahb_gates 46>;
72 compatible = "arm,cortex-a8";
75 clock-latency = <244144>; /* 8 32k periods */
84 cooling-min-level = <0>;
85 cooling-max-level = <3>;
92 polling-delay-passive = <250>;
93 polling-delay = <1000>;
94 thermal-sensors = <&rtp>;
99 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
104 cpu_alert0: cpu_alert0 {
106 temperature = <850000>;
113 temperature = <100000>;
122 reg = <0x40000000 0x80000000>;
126 #address-cells = <1>;
131 * This is a dummy clock, to be used as placeholder on
132 * other mux clocks when a specific parent clock is not
133 * yet implemented. It should be dropped when the driver
138 compatible = "fixed-clock";
139 clock-frequency = <0>;
142 osc24M: clk@01c20050 {
144 compatible = "allwinner,sun4i-a10-osc-clk";
145 reg = <0x01c20050 0x4>;
146 clock-frequency = <24000000>;
147 clock-output-names = "osc24M";
152 compatible = "fixed-clock";
153 clock-frequency = <32768>;
154 clock-output-names = "osc32k";
159 compatible = "allwinner,sun4i-a10-pll1-clk";
160 reg = <0x01c20000 0x4>;
162 clock-output-names = "pll1";
167 compatible = "allwinner,sun4i-a10-pll1-clk";
168 reg = <0x01c20018 0x4>;
170 clock-output-names = "pll4";
175 compatible = "allwinner,sun4i-a10-pll5-clk";
176 reg = <0x01c20020 0x4>;
178 clock-output-names = "pll5_ddr", "pll5_other";
183 compatible = "allwinner,sun4i-a10-pll6-clk";
184 reg = <0x01c20028 0x4>;
186 clock-output-names = "pll6_sata", "pll6_other", "pll6";
192 compatible = "allwinner,sun4i-a10-cpu-clk";
193 reg = <0x01c20054 0x4>;
194 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
195 clock-output-names = "cpu";
200 compatible = "allwinner,sun4i-a10-axi-clk";
201 reg = <0x01c20054 0x4>;
203 clock-output-names = "axi";
206 axi_gates: clk@01c2005c {
208 compatible = "allwinner,sun4i-a10-axi-gates-clk";
209 reg = <0x01c2005c 0x4>;
211 clock-output-names = "axi_dram";
216 compatible = "allwinner,sun4i-a10-ahb-clk";
217 reg = <0x01c20054 0x4>;
219 clock-output-names = "ahb";
222 ahb_gates: clk@01c20060 {
224 compatible = "allwinner,sun4i-a10-ahb-gates-clk";
225 reg = <0x01c20060 0x8>;
227 clock-output-names = "ahb_usb0", "ahb_ehci0",
228 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
229 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
230 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
231 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
232 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
233 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
234 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
235 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
236 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
237 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
240 apb0: apb0@01c20054 {
242 compatible = "allwinner,sun4i-a10-apb0-clk";
243 reg = <0x01c20054 0x4>;
245 clock-output-names = "apb0";
248 apb0_gates: clk@01c20068 {
250 compatible = "allwinner,sun4i-a10-apb0-gates-clk";
251 reg = <0x01c20068 0x4>;
253 clock-output-names = "apb0_codec", "apb0_spdif",
254 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
255 "apb0_ir1", "apb0_keypad";
260 compatible = "allwinner,sun4i-a10-apb1-clk";
261 reg = <0x01c20058 0x4>;
262 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
263 clock-output-names = "apb1";
266 apb1_gates: clk@01c2006c {
268 compatible = "allwinner,sun4i-a10-apb1-gates-clk";
269 reg = <0x01c2006c 0x4>;
271 clock-output-names = "apb1_i2c0", "apb1_i2c1",
272 "apb1_i2c2", "apb1_can", "apb1_scr",
273 "apb1_ps20", "apb1_ps21", "apb1_uart0",
274 "apb1_uart1", "apb1_uart2", "apb1_uart3",
275 "apb1_uart4", "apb1_uart5", "apb1_uart6",
279 nand_clk: clk@01c20080 {
281 compatible = "allwinner,sun4i-a10-mod0-clk";
282 reg = <0x01c20080 0x4>;
283 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
284 clock-output-names = "nand";
287 ms_clk: clk@01c20084 {
289 compatible = "allwinner,sun4i-a10-mod0-clk";
290 reg = <0x01c20084 0x4>;
291 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
292 clock-output-names = "ms";
295 mmc0_clk: clk@01c20088 {
297 compatible = "allwinner,sun4i-a10-mmc-clk";
298 reg = <0x01c20088 0x4>;
299 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
300 clock-output-names = "mmc0",
305 mmc1_clk: clk@01c2008c {
307 compatible = "allwinner,sun4i-a10-mmc-clk";
308 reg = <0x01c2008c 0x4>;
309 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
310 clock-output-names = "mmc1",
315 mmc2_clk: clk@01c20090 {
317 compatible = "allwinner,sun4i-a10-mmc-clk";
318 reg = <0x01c20090 0x4>;
319 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
320 clock-output-names = "mmc2",
325 mmc3_clk: clk@01c20094 {
327 compatible = "allwinner,sun4i-a10-mmc-clk";
328 reg = <0x01c20094 0x4>;
329 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
330 clock-output-names = "mmc3",
335 ts_clk: clk@01c20098 {
337 compatible = "allwinner,sun4i-a10-mod0-clk";
338 reg = <0x01c20098 0x4>;
339 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
340 clock-output-names = "ts";
343 ss_clk: clk@01c2009c {
345 compatible = "allwinner,sun4i-a10-mod0-clk";
346 reg = <0x01c2009c 0x4>;
347 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
348 clock-output-names = "ss";
351 spi0_clk: clk@01c200a0 {
353 compatible = "allwinner,sun4i-a10-mod0-clk";
354 reg = <0x01c200a0 0x4>;
355 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
356 clock-output-names = "spi0";
359 spi1_clk: clk@01c200a4 {
361 compatible = "allwinner,sun4i-a10-mod0-clk";
362 reg = <0x01c200a4 0x4>;
363 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
364 clock-output-names = "spi1";
367 spi2_clk: clk@01c200a8 {
369 compatible = "allwinner,sun4i-a10-mod0-clk";
370 reg = <0x01c200a8 0x4>;
371 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
372 clock-output-names = "spi2";
375 pata_clk: clk@01c200ac {
377 compatible = "allwinner,sun4i-a10-mod0-clk";
378 reg = <0x01c200ac 0x4>;
379 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
380 clock-output-names = "pata";
383 ir0_clk: clk@01c200b0 {
385 compatible = "allwinner,sun4i-a10-mod0-clk";
386 reg = <0x01c200b0 0x4>;
387 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
388 clock-output-names = "ir0";
391 ir1_clk: clk@01c200b4 {
393 compatible = "allwinner,sun4i-a10-mod0-clk";
394 reg = <0x01c200b4 0x4>;
395 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
396 clock-output-names = "ir1";
399 usb_clk: clk@01c200cc {
402 compatible = "allwinner,sun4i-a10-usb-clk";
403 reg = <0x01c200cc 0x4>;
405 clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy";
408 spi3_clk: clk@01c200d4 {
410 compatible = "allwinner,sun4i-a10-mod0-clk";
411 reg = <0x01c200d4 0x4>;
412 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
413 clock-output-names = "spi3";
418 compatible = "simple-bus";
419 #address-cells = <1>;
423 dma: dma-controller@01c02000 {
424 compatible = "allwinner,sun4i-a10-dma";
425 reg = <0x01c02000 0x1000>;
427 clocks = <&ahb_gates 6>;
432 compatible = "allwinner,sun4i-a10-spi";
433 reg = <0x01c05000 0x1000>;
435 clocks = <&ahb_gates 20>, <&spi0_clk>;
436 clock-names = "ahb", "mod";
437 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
438 <&dma SUN4I_DMA_DEDICATED 26>;
439 dma-names = "rx", "tx";
441 #address-cells = <1>;
446 compatible = "allwinner,sun4i-a10-spi";
447 reg = <0x01c06000 0x1000>;
449 clocks = <&ahb_gates 21>, <&spi1_clk>;
450 clock-names = "ahb", "mod";
451 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
452 <&dma SUN4I_DMA_DEDICATED 8>;
453 dma-names = "rx", "tx";
455 #address-cells = <1>;
459 emac: ethernet@01c0b000 {
460 compatible = "allwinner,sun4i-a10-emac";
461 reg = <0x01c0b000 0x1000>;
463 clocks = <&ahb_gates 17>;
467 mdio: mdio@01c0b080 {
468 compatible = "allwinner,sun4i-a10-mdio";
469 reg = <0x01c0b080 0x14>;
471 #address-cells = <1>;
476 compatible = "allwinner,sun4i-a10-mmc";
477 reg = <0x01c0f000 0x1000>;
478 clocks = <&ahb_gates 8>,
491 compatible = "allwinner,sun4i-a10-mmc";
492 reg = <0x01c10000 0x1000>;
493 clocks = <&ahb_gates 9>,
506 compatible = "allwinner,sun4i-a10-mmc";
507 reg = <0x01c11000 0x1000>;
508 clocks = <&ahb_gates 10>,
521 compatible = "allwinner,sun4i-a10-mmc";
522 reg = <0x01c12000 0x1000>;
523 clocks = <&ahb_gates 11>,
535 usbphy: phy@01c13400 {
537 compatible = "allwinner,sun4i-a10-usb-phy";
538 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
539 reg-names = "phy_ctrl", "pmu1", "pmu2";
540 clocks = <&usb_clk 8>;
541 clock-names = "usb_phy";
542 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
543 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
547 ehci0: usb@01c14000 {
548 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
549 reg = <0x01c14000 0x100>;
551 clocks = <&ahb_gates 1>;
557 ohci0: usb@01c14400 {
558 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
559 reg = <0x01c14400 0x100>;
561 clocks = <&usb_clk 6>, <&ahb_gates 2>;
568 compatible = "allwinner,sun4i-a10-spi";
569 reg = <0x01c17000 0x1000>;
571 clocks = <&ahb_gates 22>, <&spi2_clk>;
572 clock-names = "ahb", "mod";
573 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
574 <&dma SUN4I_DMA_DEDICATED 28>;
575 dma-names = "rx", "tx";
577 #address-cells = <1>;
581 ahci: sata@01c18000 {
582 compatible = "allwinner,sun4i-a10-ahci";
583 reg = <0x01c18000 0x1000>;
585 clocks = <&pll6 0>, <&ahb_gates 25>;
589 ehci1: usb@01c1c000 {
590 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
591 reg = <0x01c1c000 0x100>;
593 clocks = <&ahb_gates 3>;
599 ohci1: usb@01c1c400 {
600 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
601 reg = <0x01c1c400 0x100>;
603 clocks = <&usb_clk 7>, <&ahb_gates 4>;
610 compatible = "allwinner,sun4i-a10-spi";
611 reg = <0x01c1f000 0x1000>;
613 clocks = <&ahb_gates 23>, <&spi3_clk>;
614 clock-names = "ahb", "mod";
615 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
616 <&dma SUN4I_DMA_DEDICATED 30>;
617 dma-names = "rx", "tx";
619 #address-cells = <1>;
623 intc: interrupt-controller@01c20400 {
624 compatible = "allwinner,sun4i-a10-ic";
625 reg = <0x01c20400 0x400>;
626 interrupt-controller;
627 #interrupt-cells = <1>;
630 pio: pinctrl@01c20800 {
631 compatible = "allwinner,sun4i-a10-pinctrl";
632 reg = <0x01c20800 0x400>;
634 clocks = <&apb0_gates 5>;
636 interrupt-controller;
637 #interrupt-cells = <2>;
641 pwm0_pins_a: pwm0@0 {
642 allwinner,pins = "PB2";
643 allwinner,function = "pwm";
644 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
645 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
648 pwm1_pins_a: pwm1@0 {
649 allwinner,pins = "PI3";
650 allwinner,function = "pwm";
651 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
652 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
655 uart0_pins_a: uart0@0 {
656 allwinner,pins = "PB22", "PB23";
657 allwinner,function = "uart0";
658 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
659 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
662 uart0_pins_b: uart0@1 {
663 allwinner,pins = "PF2", "PF4";
664 allwinner,function = "uart0";
665 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
666 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
669 uart1_pins_a: uart1@0 {
670 allwinner,pins = "PA10", "PA11";
671 allwinner,function = "uart1";
672 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
673 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
676 i2c0_pins_a: i2c0@0 {
677 allwinner,pins = "PB0", "PB1";
678 allwinner,function = "i2c0";
679 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
680 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
683 i2c1_pins_a: i2c1@0 {
684 allwinner,pins = "PB18", "PB19";
685 allwinner,function = "i2c1";
686 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
687 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
690 i2c2_pins_a: i2c2@0 {
691 allwinner,pins = "PB20", "PB21";
692 allwinner,function = "i2c2";
693 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
694 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
697 emac_pins_a: emac0@0 {
698 allwinner,pins = "PA0", "PA1", "PA2",
699 "PA3", "PA4", "PA5", "PA6",
700 "PA7", "PA8", "PA9", "PA10",
701 "PA11", "PA12", "PA13", "PA14",
703 allwinner,function = "emac";
704 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
705 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
708 mmc0_pins_a: mmc0@0 {
709 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
710 allwinner,function = "mmc0";
711 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
712 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
715 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
716 allwinner,pins = "PH1";
717 allwinner,function = "gpio_in";
718 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
719 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
723 allwinner,pins = "PB3","PB4";
724 allwinner,function = "ir0";
725 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
726 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
730 allwinner,pins = "PB22","PB23";
731 allwinner,function = "ir1";
732 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
733 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
736 spi0_pins_a: spi0@0 {
737 allwinner,pins = "PI10", "PI11", "PI12", "PI13";
738 allwinner,function = "spi0";
739 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
740 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
743 spi1_pins_a: spi1@0 {
744 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
745 allwinner,function = "spi1";
746 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
747 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
750 spi2_pins_a: spi2@0 {
751 allwinner,pins = "PB14", "PB15", "PB16", "PB17";
752 allwinner,function = "spi2";
753 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
754 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
757 spi2_pins_b: spi2@1 {
758 allwinner,pins = "PC19", "PC20", "PC21", "PC22";
759 allwinner,function = "spi2";
760 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
761 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
764 ps20_pins_a: ps20@0 {
765 allwinner,pins = "PI20", "PI21";
766 allwinner,function = "ps2";
767 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
768 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
771 ps21_pins_a: ps21@0 {
772 allwinner,pins = "PH12", "PH13";
773 allwinner,function = "ps2";
774 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
775 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
780 compatible = "allwinner,sun4i-a10-timer";
781 reg = <0x01c20c00 0x90>;
786 wdt: watchdog@01c20c90 {
787 compatible = "allwinner,sun4i-a10-wdt";
788 reg = <0x01c20c90 0x10>;
792 compatible = "allwinner,sun4i-a10-rtc";
793 reg = <0x01c20d00 0x20>;
798 compatible = "allwinner,sun4i-a10-pwm";
799 reg = <0x01c20e00 0xc>;
806 compatible = "allwinner,sun4i-a10-ir";
807 clocks = <&apb0_gates 6>, <&ir0_clk>;
808 clock-names = "apb", "ir";
810 reg = <0x01c21800 0x40>;
815 compatible = "allwinner,sun4i-a10-ir";
816 clocks = <&apb0_gates 7>, <&ir1_clk>;
817 clock-names = "apb", "ir";
819 reg = <0x01c21c00 0x40>;
823 lradc: lradc@01c22800 {
824 compatible = "allwinner,sun4i-a10-lradc-keys";
825 reg = <0x01c22800 0x100>;
830 sid: eeprom@01c23800 {
831 compatible = "allwinner,sun4i-a10-sid";
832 reg = <0x01c23800 0x10>;
836 compatible = "allwinner,sun4i-a10-ts";
837 reg = <0x01c25000 0x100>;
839 #thermal-sensor-cells = <0>;
842 uart0: serial@01c28000 {
843 compatible = "snps,dw-apb-uart";
844 reg = <0x01c28000 0x400>;
848 clocks = <&apb1_gates 16>;
852 uart1: serial@01c28400 {
853 compatible = "snps,dw-apb-uart";
854 reg = <0x01c28400 0x400>;
858 clocks = <&apb1_gates 17>;
862 uart2: serial@01c28800 {
863 compatible = "snps,dw-apb-uart";
864 reg = <0x01c28800 0x400>;
868 clocks = <&apb1_gates 18>;
872 uart3: serial@01c28c00 {
873 compatible = "snps,dw-apb-uart";
874 reg = <0x01c28c00 0x400>;
878 clocks = <&apb1_gates 19>;
882 uart4: serial@01c29000 {
883 compatible = "snps,dw-apb-uart";
884 reg = <0x01c29000 0x400>;
888 clocks = <&apb1_gates 20>;
892 uart5: serial@01c29400 {
893 compatible = "snps,dw-apb-uart";
894 reg = <0x01c29400 0x400>;
898 clocks = <&apb1_gates 21>;
902 uart6: serial@01c29800 {
903 compatible = "snps,dw-apb-uart";
904 reg = <0x01c29800 0x400>;
908 clocks = <&apb1_gates 22>;
912 uart7: serial@01c29c00 {
913 compatible = "snps,dw-apb-uart";
914 reg = <0x01c29c00 0x400>;
918 clocks = <&apb1_gates 23>;
923 compatible = "allwinner,sun4i-a10-i2c";
924 reg = <0x01c2ac00 0x400>;
926 clocks = <&apb1_gates 0>;
928 #address-cells = <1>;
933 compatible = "allwinner,sun4i-a10-i2c";
934 reg = <0x01c2b000 0x400>;
936 clocks = <&apb1_gates 1>;
938 #address-cells = <1>;
943 compatible = "allwinner,sun4i-a10-i2c";
944 reg = <0x01c2b400 0x400>;
946 clocks = <&apb1_gates 2>;
948 #address-cells = <1>;
953 compatible = "allwinner,sun4i-a10-ps2";
954 reg = <0x01c2a000 0x400>;
956 clocks = <&apb1_gates 6>;
961 compatible = "allwinner,sun4i-a10-ps2";
962 reg = <0x01c2a400 0x400>;
964 clocks = <&apb1_gates 7>;