2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
22 * b) Permission is hereby granted, free of charge, to any person
23 * obtaining a copy of this software and associated documentation
24 * files (the "Software"), to deal in the Software without
25 * restriction, including without limitation the rights to use,
26 * copy, modify, merge, publish, distribute, sublicense, and/or
27 * sell copies of the Software, and to permit persons to whom the
28 * Software is furnished to do so, subject to the following
31 * The above copyright notice and this permission notice shall be
32 * included in all copies or substantial portions of the Software.
34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 * OTHER DEALINGS IN THE SOFTWARE.
44 #include "skeleton.dtsi"
46 #include <dt-bindings/thermal/thermal.h>
48 #include <dt-bindings/dma/sun4i-a10.h>
49 #include <dt-bindings/pinctrl/sun4i-a10.h>
52 interrupt-parent = <&intc>;
64 compatible = "allwinner,simple-framebuffer",
66 allwinner,pipeline = "de_be0-lcd0-hdmi";
67 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
73 compatible = "allwinner,simple-framebuffer",
75 allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
76 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
77 <&ahb_gates 44>, <&ahb_gates 46>;
82 compatible = "allwinner,simple-framebuffer",
84 allwinner,pipeline = "de_fe0-de_be0-lcd0";
85 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>,
91 compatible = "allwinner,simple-framebuffer",
93 allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
94 clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>,
95 <&ahb_gates 44>, <&ahb_gates 46>;
101 #address-cells = <1>;
105 compatible = "arm,cortex-a8";
108 clock-latency = <244144>; /* 8 32k periods */
116 #cooling-cells = <2>;
117 cooling-min-level = <0>;
118 cooling-max-level = <3>;
125 polling-delay-passive = <250>;
126 polling-delay = <1000>;
127 thermal-sensors = <&rtp>;
131 trip = <&cpu_alert0>;
132 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
137 cpu_alert0: cpu_alert0 {
139 temperature = <850000>;
146 temperature = <100000>;
155 reg = <0x40000000 0x80000000>;
159 #address-cells = <1>;
164 * This is a dummy clock, to be used as placeholder on
165 * other mux clocks when a specific parent clock is not
166 * yet implemented. It should be dropped when the driver
171 compatible = "fixed-clock";
172 clock-frequency = <0>;
175 osc24M: clk@01c20050 {
177 compatible = "allwinner,sun4i-a10-osc-clk";
178 reg = <0x01c20050 0x4>;
179 clock-frequency = <24000000>;
180 clock-output-names = "osc24M";
185 compatible = "fixed-clock";
186 clock-frequency = <32768>;
187 clock-output-names = "osc32k";
192 compatible = "allwinner,sun4i-a10-pll1-clk";
193 reg = <0x01c20000 0x4>;
195 clock-output-names = "pll1";
200 compatible = "allwinner,sun4i-a10-pll1-clk";
201 reg = <0x01c20018 0x4>;
203 clock-output-names = "pll4";
208 compatible = "allwinner,sun4i-a10-pll5-clk";
209 reg = <0x01c20020 0x4>;
211 clock-output-names = "pll5_ddr", "pll5_other";
216 compatible = "allwinner,sun4i-a10-pll6-clk";
217 reg = <0x01c20028 0x4>;
219 clock-output-names = "pll6_sata", "pll6_other", "pll6";
225 compatible = "allwinner,sun4i-a10-cpu-clk";
226 reg = <0x01c20054 0x4>;
227 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
228 clock-output-names = "cpu";
233 compatible = "allwinner,sun4i-a10-axi-clk";
234 reg = <0x01c20054 0x4>;
236 clock-output-names = "axi";
239 axi_gates: clk@01c2005c {
241 compatible = "allwinner,sun4i-a10-axi-gates-clk";
242 reg = <0x01c2005c 0x4>;
244 clock-output-names = "axi_dram";
249 compatible = "allwinner,sun4i-a10-ahb-clk";
250 reg = <0x01c20054 0x4>;
252 clock-output-names = "ahb";
255 ahb_gates: clk@01c20060 {
257 compatible = "allwinner,sun4i-a10-ahb-gates-clk";
258 reg = <0x01c20060 0x8>;
260 clock-output-names = "ahb_usb0", "ahb_ehci0",
261 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
262 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
263 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
264 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
265 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
266 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
267 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
268 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
269 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
270 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
273 apb0: apb0@01c20054 {
275 compatible = "allwinner,sun4i-a10-apb0-clk";
276 reg = <0x01c20054 0x4>;
278 clock-output-names = "apb0";
281 apb0_gates: clk@01c20068 {
283 compatible = "allwinner,sun4i-a10-apb0-gates-clk";
284 reg = <0x01c20068 0x4>;
286 clock-output-names = "apb0_codec", "apb0_spdif",
287 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
288 "apb0_ir1", "apb0_keypad";
293 compatible = "allwinner,sun4i-a10-apb1-clk";
294 reg = <0x01c20058 0x4>;
295 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
296 clock-output-names = "apb1";
299 apb1_gates: clk@01c2006c {
301 compatible = "allwinner,sun4i-a10-apb1-gates-clk";
302 reg = <0x01c2006c 0x4>;
304 clock-output-names = "apb1_i2c0", "apb1_i2c1",
305 "apb1_i2c2", "apb1_can", "apb1_scr",
306 "apb1_ps20", "apb1_ps21", "apb1_uart0",
307 "apb1_uart1", "apb1_uart2", "apb1_uart3",
308 "apb1_uart4", "apb1_uart5", "apb1_uart6",
312 nand_clk: clk@01c20080 {
314 compatible = "allwinner,sun4i-a10-mod0-clk";
315 reg = <0x01c20080 0x4>;
316 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
317 clock-output-names = "nand";
320 ms_clk: clk@01c20084 {
322 compatible = "allwinner,sun4i-a10-mod0-clk";
323 reg = <0x01c20084 0x4>;
324 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
325 clock-output-names = "ms";
328 mmc0_clk: clk@01c20088 {
330 compatible = "allwinner,sun4i-a10-mmc-clk";
331 reg = <0x01c20088 0x4>;
332 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
333 clock-output-names = "mmc0",
338 mmc1_clk: clk@01c2008c {
340 compatible = "allwinner,sun4i-a10-mmc-clk";
341 reg = <0x01c2008c 0x4>;
342 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
343 clock-output-names = "mmc1",
348 mmc2_clk: clk@01c20090 {
350 compatible = "allwinner,sun4i-a10-mmc-clk";
351 reg = <0x01c20090 0x4>;
352 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
353 clock-output-names = "mmc2",
358 mmc3_clk: clk@01c20094 {
360 compatible = "allwinner,sun4i-a10-mmc-clk";
361 reg = <0x01c20094 0x4>;
362 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
363 clock-output-names = "mmc3",
368 ts_clk: clk@01c20098 {
370 compatible = "allwinner,sun4i-a10-mod0-clk";
371 reg = <0x01c20098 0x4>;
372 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
373 clock-output-names = "ts";
376 ss_clk: clk@01c2009c {
378 compatible = "allwinner,sun4i-a10-mod0-clk";
379 reg = <0x01c2009c 0x4>;
380 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
381 clock-output-names = "ss";
384 spi0_clk: clk@01c200a0 {
386 compatible = "allwinner,sun4i-a10-mod0-clk";
387 reg = <0x01c200a0 0x4>;
388 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
389 clock-output-names = "spi0";
392 spi1_clk: clk@01c200a4 {
394 compatible = "allwinner,sun4i-a10-mod0-clk";
395 reg = <0x01c200a4 0x4>;
396 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
397 clock-output-names = "spi1";
400 spi2_clk: clk@01c200a8 {
402 compatible = "allwinner,sun4i-a10-mod0-clk";
403 reg = <0x01c200a8 0x4>;
404 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
405 clock-output-names = "spi2";
408 pata_clk: clk@01c200ac {
410 compatible = "allwinner,sun4i-a10-mod0-clk";
411 reg = <0x01c200ac 0x4>;
412 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
413 clock-output-names = "pata";
416 ir0_clk: clk@01c200b0 {
418 compatible = "allwinner,sun4i-a10-mod0-clk";
419 reg = <0x01c200b0 0x4>;
420 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
421 clock-output-names = "ir0";
424 ir1_clk: clk@01c200b4 {
426 compatible = "allwinner,sun4i-a10-mod0-clk";
427 reg = <0x01c200b4 0x4>;
428 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
429 clock-output-names = "ir1";
432 usb_clk: clk@01c200cc {
435 compatible = "allwinner,sun4i-a10-usb-clk";
436 reg = <0x01c200cc 0x4>;
438 clock-output-names = "usb_ohci0", "usb_ohci1",
442 spi3_clk: clk@01c200d4 {
444 compatible = "allwinner,sun4i-a10-mod0-clk";
445 reg = <0x01c200d4 0x4>;
446 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
447 clock-output-names = "spi3";
452 * Note we use the address where the mmio registers start, not where
453 * the SRAM blocks start, this cannot be changed because that would be
454 * a devicetree ABI change.
457 compatible = "simple-bus";
458 #address-cells = <1>;
463 compatible = "allwinner,sun4i-a10-sram";
464 reg = <0x00000000 0x4000>;
465 allwinner,sram-name = "A1";
469 compatible = "allwinner,sun4i-a10-sram";
470 reg = <0x00004000 0x4000>;
471 allwinner,sram-name = "A2";
475 compatible = "allwinner,sun4i-a10-sram";
476 reg = <0x00008000 0x4000>;
477 allwinner,sram-name = "A3-A4";
481 compatible = "allwinner,sun4i-a10-sram";
482 reg = <0x00010000 0x1000>;
483 allwinner,sram-name = "D";
486 sram-controller@01c00000 {
487 compatible = "allwinner,sun4i-a10-sram-controller";
488 reg = <0x01c00000 0x30>;
491 dma: dma-controller@01c02000 {
492 compatible = "allwinner,sun4i-a10-dma";
493 reg = <0x01c02000 0x1000>;
495 clocks = <&ahb_gates 6>;
500 compatible = "allwinner,sun4i-a10-spi";
501 reg = <0x01c05000 0x1000>;
503 clocks = <&ahb_gates 20>, <&spi0_clk>;
504 clock-names = "ahb", "mod";
505 dmas = <&dma SUN4I_DMA_DEDICATED 27>,
506 <&dma SUN4I_DMA_DEDICATED 26>;
507 dma-names = "rx", "tx";
509 #address-cells = <1>;
514 compatible = "allwinner,sun4i-a10-spi";
515 reg = <0x01c06000 0x1000>;
517 clocks = <&ahb_gates 21>, <&spi1_clk>;
518 clock-names = "ahb", "mod";
519 dmas = <&dma SUN4I_DMA_DEDICATED 9>,
520 <&dma SUN4I_DMA_DEDICATED 8>;
521 dma-names = "rx", "tx";
523 #address-cells = <1>;
527 emac: ethernet@01c0b000 {
528 compatible = "allwinner,sun4i-a10-emac";
529 reg = <0x01c0b000 0x1000>;
531 clocks = <&ahb_gates 17>;
535 mdio: mdio@01c0b080 {
536 compatible = "allwinner,sun4i-a10-mdio";
537 reg = <0x01c0b080 0x14>;
539 #address-cells = <1>;
544 compatible = "allwinner,sun4i-a10-mmc";
545 reg = <0x01c0f000 0x1000>;
546 clocks = <&ahb_gates 8>,
556 #address-cells = <1>;
561 compatible = "allwinner,sun4i-a10-mmc";
562 reg = <0x01c10000 0x1000>;
563 clocks = <&ahb_gates 9>,
573 #address-cells = <1>;
578 compatible = "allwinner,sun4i-a10-mmc";
579 reg = <0x01c11000 0x1000>;
580 clocks = <&ahb_gates 10>,
590 #address-cells = <1>;
595 compatible = "allwinner,sun4i-a10-mmc";
596 reg = <0x01c12000 0x1000>;
597 clocks = <&ahb_gates 11>,
607 #address-cells = <1>;
611 usbphy: phy@01c13400 {
613 compatible = "allwinner,sun4i-a10-usb-phy";
614 reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
615 reg-names = "phy_ctrl", "pmu1", "pmu2";
616 clocks = <&usb_clk 8>;
617 clock-names = "usb_phy";
618 resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
619 reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
623 ehci0: usb@01c14000 {
624 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
625 reg = <0x01c14000 0x100>;
627 clocks = <&ahb_gates 1>;
633 ohci0: usb@01c14400 {
634 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
635 reg = <0x01c14400 0x100>;
637 clocks = <&usb_clk 6>, <&ahb_gates 2>;
644 compatible = "allwinner,sun4i-a10-spi";
645 reg = <0x01c17000 0x1000>;
647 clocks = <&ahb_gates 22>, <&spi2_clk>;
648 clock-names = "ahb", "mod";
649 dmas = <&dma SUN4I_DMA_DEDICATED 29>,
650 <&dma SUN4I_DMA_DEDICATED 28>;
651 dma-names = "rx", "tx";
653 #address-cells = <1>;
657 ahci: sata@01c18000 {
658 compatible = "allwinner,sun4i-a10-ahci";
659 reg = <0x01c18000 0x1000>;
661 clocks = <&pll6 0>, <&ahb_gates 25>;
665 ehci1: usb@01c1c000 {
666 compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
667 reg = <0x01c1c000 0x100>;
669 clocks = <&ahb_gates 3>;
675 ohci1: usb@01c1c400 {
676 compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
677 reg = <0x01c1c400 0x100>;
679 clocks = <&usb_clk 7>, <&ahb_gates 4>;
686 compatible = "allwinner,sun4i-a10-spi";
687 reg = <0x01c1f000 0x1000>;
689 clocks = <&ahb_gates 23>, <&spi3_clk>;
690 clock-names = "ahb", "mod";
691 dmas = <&dma SUN4I_DMA_DEDICATED 31>,
692 <&dma SUN4I_DMA_DEDICATED 30>;
693 dma-names = "rx", "tx";
695 #address-cells = <1>;
699 intc: interrupt-controller@01c20400 {
700 compatible = "allwinner,sun4i-a10-ic";
701 reg = <0x01c20400 0x400>;
702 interrupt-controller;
703 #interrupt-cells = <1>;
706 pio: pinctrl@01c20800 {
707 compatible = "allwinner,sun4i-a10-pinctrl";
708 reg = <0x01c20800 0x400>;
710 clocks = <&apb0_gates 5>;
712 interrupt-controller;
713 #interrupt-cells = <2>;
717 pwm0_pins_a: pwm0@0 {
718 allwinner,pins = "PB2";
719 allwinner,function = "pwm";
720 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
721 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
724 pwm1_pins_a: pwm1@0 {
725 allwinner,pins = "PI3";
726 allwinner,function = "pwm";
727 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
728 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
731 uart0_pins_a: uart0@0 {
732 allwinner,pins = "PB22", "PB23";
733 allwinner,function = "uart0";
734 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
735 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
738 uart0_pins_b: uart0@1 {
739 allwinner,pins = "PF2", "PF4";
740 allwinner,function = "uart0";
741 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
742 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
745 uart1_pins_a: uart1@0 {
746 allwinner,pins = "PA10", "PA11";
747 allwinner,function = "uart1";
748 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
749 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
752 i2c0_pins_a: i2c0@0 {
753 allwinner,pins = "PB0", "PB1";
754 allwinner,function = "i2c0";
755 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
756 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
759 i2c1_pins_a: i2c1@0 {
760 allwinner,pins = "PB18", "PB19";
761 allwinner,function = "i2c1";
762 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
763 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
766 i2c2_pins_a: i2c2@0 {
767 allwinner,pins = "PB20", "PB21";
768 allwinner,function = "i2c2";
769 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
770 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
773 emac_pins_a: emac0@0 {
774 allwinner,pins = "PA0", "PA1", "PA2",
775 "PA3", "PA4", "PA5", "PA6",
776 "PA7", "PA8", "PA9", "PA10",
777 "PA11", "PA12", "PA13", "PA14",
779 allwinner,function = "emac";
780 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
781 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
784 mmc0_pins_a: mmc0@0 {
785 allwinner,pins = "PF0", "PF1", "PF2",
787 allwinner,function = "mmc0";
788 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
789 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
792 mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
793 allwinner,pins = "PH1";
794 allwinner,function = "gpio_in";
795 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
796 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
799 ir0_rx_pins_a: ir0@0 {
800 allwinner,pins = "PB4";
801 allwinner,function = "ir0";
802 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
803 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
806 ir0_tx_pins_a: ir0@1 {
807 allwinner,pins = "PB3";
808 allwinner,function = "ir0";
809 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
810 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
813 ir1_rx_pins_a: ir1@0 {
814 allwinner,pins = "PB23";
815 allwinner,function = "ir1";
816 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
817 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
820 ir1_tx_pins_a: ir1@1 {
821 allwinner,pins = "PB22";
822 allwinner,function = "ir1";
823 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
824 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
827 spi0_pins_a: spi0@0 {
828 allwinner,pins = "PI11", "PI12", "PI13";
829 allwinner,function = "spi0";
830 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
831 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
834 spi0_cs0_pins_a: spi0_cs0@0 {
835 allwinner,pins = "PI10";
836 allwinner,function = "spi0";
837 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
838 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
841 spi1_pins_a: spi1@0 {
842 allwinner,pins = "PI17", "PI18", "PI19";
843 allwinner,function = "spi1";
844 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
845 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
848 spi1_cs0_pins_a: spi1_cs0@0 {
849 allwinner,pins = "PI16";
850 allwinner,function = "spi1";
851 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
852 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
855 spi2_pins_a: spi2@0 {
856 allwinner,pins = "PC20", "PC21", "PC22";
857 allwinner,function = "spi2";
858 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
859 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
862 spi2_pins_b: spi2@1 {
863 allwinner,pins = "PB15", "PB16", "PB17";
864 allwinner,function = "spi2";
865 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
866 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
869 spi2_cs0_pins_a: spi2_cs0@0 {
870 allwinner,pins = "PC19";
871 allwinner,function = "spi2";
872 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
873 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
876 spi2_cs0_pins_b: spi2_cs0@1 {
877 allwinner,pins = "PB14";
878 allwinner,function = "spi2";
879 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
880 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
883 ps20_pins_a: ps20@0 {
884 allwinner,pins = "PI20", "PI21";
885 allwinner,function = "ps2";
886 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
887 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
890 ps21_pins_a: ps21@0 {
891 allwinner,pins = "PH12", "PH13";
892 allwinner,function = "ps2";
893 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
894 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
899 compatible = "allwinner,sun4i-a10-timer";
900 reg = <0x01c20c00 0x90>;
905 wdt: watchdog@01c20c90 {
906 compatible = "allwinner,sun4i-a10-wdt";
907 reg = <0x01c20c90 0x10>;
911 compatible = "allwinner,sun4i-a10-rtc";
912 reg = <0x01c20d00 0x20>;
917 compatible = "allwinner,sun4i-a10-pwm";
918 reg = <0x01c20e00 0xc>;
925 compatible = "allwinner,sun4i-a10-ir";
926 clocks = <&apb0_gates 6>, <&ir0_clk>;
927 clock-names = "apb", "ir";
929 reg = <0x01c21800 0x40>;
934 compatible = "allwinner,sun4i-a10-ir";
935 clocks = <&apb0_gates 7>, <&ir1_clk>;
936 clock-names = "apb", "ir";
938 reg = <0x01c21c00 0x40>;
942 lradc: lradc@01c22800 {
943 compatible = "allwinner,sun4i-a10-lradc-keys";
944 reg = <0x01c22800 0x100>;
949 sid: eeprom@01c23800 {
950 compatible = "allwinner,sun4i-a10-sid";
951 reg = <0x01c23800 0x10>;
955 compatible = "allwinner,sun4i-a10-ts";
956 reg = <0x01c25000 0x100>;
958 #thermal-sensor-cells = <0>;
961 uart0: serial@01c28000 {
962 compatible = "snps,dw-apb-uart";
963 reg = <0x01c28000 0x400>;
967 clocks = <&apb1_gates 16>;
971 uart1: serial@01c28400 {
972 compatible = "snps,dw-apb-uart";
973 reg = <0x01c28400 0x400>;
977 clocks = <&apb1_gates 17>;
981 uart2: serial@01c28800 {
982 compatible = "snps,dw-apb-uart";
983 reg = <0x01c28800 0x400>;
987 clocks = <&apb1_gates 18>;
991 uart3: serial@01c28c00 {
992 compatible = "snps,dw-apb-uart";
993 reg = <0x01c28c00 0x400>;
997 clocks = <&apb1_gates 19>;
1001 uart4: serial@01c29000 {
1002 compatible = "snps,dw-apb-uart";
1003 reg = <0x01c29000 0x400>;
1007 clocks = <&apb1_gates 20>;
1008 status = "disabled";
1011 uart5: serial@01c29400 {
1012 compatible = "snps,dw-apb-uart";
1013 reg = <0x01c29400 0x400>;
1017 clocks = <&apb1_gates 21>;
1018 status = "disabled";
1021 uart6: serial@01c29800 {
1022 compatible = "snps,dw-apb-uart";
1023 reg = <0x01c29800 0x400>;
1027 clocks = <&apb1_gates 22>;
1028 status = "disabled";
1031 uart7: serial@01c29c00 {
1032 compatible = "snps,dw-apb-uart";
1033 reg = <0x01c29c00 0x400>;
1037 clocks = <&apb1_gates 23>;
1038 status = "disabled";
1041 i2c0: i2c@01c2ac00 {
1042 compatible = "allwinner,sun4i-a10-i2c";
1043 reg = <0x01c2ac00 0x400>;
1045 clocks = <&apb1_gates 0>;
1046 status = "disabled";
1047 #address-cells = <1>;
1051 i2c1: i2c@01c2b000 {
1052 compatible = "allwinner,sun4i-a10-i2c";
1053 reg = <0x01c2b000 0x400>;
1055 clocks = <&apb1_gates 1>;
1056 status = "disabled";
1057 #address-cells = <1>;
1061 i2c2: i2c@01c2b400 {
1062 compatible = "allwinner,sun4i-a10-i2c";
1063 reg = <0x01c2b400 0x400>;
1065 clocks = <&apb1_gates 2>;
1066 status = "disabled";
1067 #address-cells = <1>;
1071 ps20: ps2@01c2a000 {
1072 compatible = "allwinner,sun4i-a10-ps2";
1073 reg = <0x01c2a000 0x400>;
1075 clocks = <&apb1_gates 6>;
1076 status = "disabled";
1079 ps21: ps2@01c2a400 {
1080 compatible = "allwinner,sun4i-a10-ps2";
1081 reg = <0x01c2a400 0x400>;
1083 clocks = <&apb1_gates 7>;
1084 status = "disabled";