2 * Copyright 2012 Stefan Roese
3 * Stefan Roese <sr@denx.de>
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 /include/ "skeleton.dtsi"
16 interrupt-parent = <&intc>;
23 compatible = "arm,cortex-a8";
29 reg = <0x40000000 0x80000000>;
38 * This is a dummy clock, to be used as placeholder on
39 * other mux clocks when a specific parent clock is not
40 * yet implemented. It should be dropped when the driver
45 compatible = "fixed-clock";
46 clock-frequency = <0>;
49 osc24M: osc24M@01c20050 {
51 compatible = "allwinner,sun4i-osc-clk";
52 reg = <0x01c20050 0x4>;
53 clock-frequency = <24000000>;
58 compatible = "fixed-clock";
59 clock-frequency = <32768>;
64 compatible = "allwinner,sun4i-pll1-clk";
65 reg = <0x01c20000 0x4>;
72 compatible = "allwinner,sun4i-cpu-clk";
73 reg = <0x01c20054 0x4>;
74 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
79 compatible = "allwinner,sun4i-axi-clk";
80 reg = <0x01c20054 0x4>;
84 axi_gates: axi_gates@01c2005c {
86 compatible = "allwinner,sun4i-axi-gates-clk";
87 reg = <0x01c2005c 0x4>;
89 clock-output-names = "axi_dram";
94 compatible = "allwinner,sun4i-ahb-clk";
95 reg = <0x01c20054 0x4>;
99 ahb_gates: ahb_gates@01c20060 {
101 compatible = "allwinner,sun4i-ahb-gates-clk";
102 reg = <0x01c20060 0x8>;
104 clock-output-names = "ahb_usb0", "ahb_ehci0",
105 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
106 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
107 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
108 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
109 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
110 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
111 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
112 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
113 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
114 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
117 apb0: apb0@01c20054 {
119 compatible = "allwinner,sun4i-apb0-clk";
120 reg = <0x01c20054 0x4>;
124 apb0_gates: apb0_gates@01c20068 {
126 compatible = "allwinner,sun4i-apb0-gates-clk";
127 reg = <0x01c20068 0x4>;
129 clock-output-names = "apb0_codec", "apb0_spdif",
130 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
131 "apb0_ir1", "apb0_keypad";
135 apb1_mux: apb1_mux@01c20058 {
137 compatible = "allwinner,sun4i-apb1-mux-clk";
138 reg = <0x01c20058 0x4>;
139 clocks = <&osc24M>, <&dummy>, <&osc32k>;
142 apb1: apb1@01c20058 {
144 compatible = "allwinner,sun4i-apb1-clk";
145 reg = <0x01c20058 0x4>;
146 clocks = <&apb1_mux>;
149 apb1_gates: apb1_gates@01c2006c {
151 compatible = "allwinner,sun4i-apb1-gates-clk";
152 reg = <0x01c2006c 0x4>;
154 clock-output-names = "apb1_i2c0", "apb1_i2c1",
155 "apb1_i2c2", "apb1_can", "apb1_scr",
156 "apb1_ps20", "apb1_ps21", "apb1_uart0",
157 "apb1_uart1", "apb1_uart2", "apb1_uart3",
158 "apb1_uart4", "apb1_uart5", "apb1_uart6",
164 compatible = "simple-bus";
165 #address-cells = <1>;
167 reg = <0x01c20000 0x300000>;
170 intc: interrupt-controller@01c20400 {
171 compatible = "allwinner,sun4i-ic";
172 reg = <0x01c20400 0x400>;
173 interrupt-controller;
174 #interrupt-cells = <1>;
177 pio: pinctrl@01c20800 {
178 compatible = "allwinner,sun4i-a10-pinctrl";
179 reg = <0x01c20800 0x400>;
181 clocks = <&apb0_gates 5>;
183 interrupt-controller;
184 #address-cells = <1>;
188 uart0_pins_a: uart0@0 {
189 allwinner,pins = "PB22", "PB23";
190 allwinner,function = "uart0";
191 allwinner,drive = <0>;
192 allwinner,pull = <0>;
195 uart0_pins_b: uart0@1 {
196 allwinner,pins = "PF2", "PF4";
197 allwinner,function = "uart0";
198 allwinner,drive = <0>;
199 allwinner,pull = <0>;
202 uart1_pins_a: uart1@0 {
203 allwinner,pins = "PA10", "PA11";
204 allwinner,function = "uart1";
205 allwinner,drive = <0>;
206 allwinner,pull = <0>;
209 i2c0_pins_a: i2c0@0 {
210 allwinner,pins = "PB0", "PB1";
211 allwinner,function = "i2c0";
212 allwinner,drive = <0>;
213 allwinner,pull = <0>;
216 i2c1_pins_a: i2c1@0 {
217 allwinner,pins = "PB18", "PB19";
218 allwinner,function = "i2c1";
219 allwinner,drive = <0>;
220 allwinner,pull = <0>;
223 i2c2_pins_a: i2c2@0 {
224 allwinner,pins = "PB20", "PB21";
225 allwinner,function = "i2c2";
226 allwinner,drive = <0>;
227 allwinner,pull = <0>;
232 compatible = "allwinner,sun4i-timer";
233 reg = <0x01c20c00 0x90>;
238 wdt: watchdog@01c20c90 {
239 compatible = "allwinner,sun4i-wdt";
240 reg = <0x01c20c90 0x10>;
243 uart0: serial@01c28000 {
244 compatible = "snps,dw-apb-uart";
245 reg = <0x01c28000 0x400>;
249 clocks = <&apb1_gates 16>;
253 uart1: serial@01c28400 {
254 compatible = "snps,dw-apb-uart";
255 reg = <0x01c28400 0x400>;
259 clocks = <&apb1_gates 17>;
263 uart2: serial@01c28800 {
264 compatible = "snps,dw-apb-uart";
265 reg = <0x01c28800 0x400>;
269 clocks = <&apb1_gates 18>;
273 uart3: serial@01c28c00 {
274 compatible = "snps,dw-apb-uart";
275 reg = <0x01c28c00 0x400>;
279 clocks = <&apb1_gates 19>;
283 uart4: serial@01c29000 {
284 compatible = "snps,dw-apb-uart";
285 reg = <0x01c29000 0x400>;
289 clocks = <&apb1_gates 20>;
293 uart5: serial@01c29400 {
294 compatible = "snps,dw-apb-uart";
295 reg = <0x01c29400 0x400>;
299 clocks = <&apb1_gates 21>;
303 uart6: serial@01c29800 {
304 compatible = "snps,dw-apb-uart";
305 reg = <0x01c29800 0x400>;
309 clocks = <&apb1_gates 22>;
313 uart7: serial@01c29c00 {
314 compatible = "snps,dw-apb-uart";
315 reg = <0x01c29c00 0x400>;
319 clocks = <&apb1_gates 23>;
324 compatible = "allwinner,sun4i-i2c";
325 reg = <0x01c2ac00 0x400>;
327 clocks = <&apb1_gates 0>;
328 clock-frequency = <100000>;
333 compatible = "allwinner,sun4i-i2c";
334 reg = <0x01c2b000 0x400>;
336 clocks = <&apb1_gates 1>;
337 clock-frequency = <100000>;
342 compatible = "allwinner,sun4i-i2c";
343 reg = <0x01c2b400 0x400>;
345 clocks = <&apb1_gates 2>;
346 clock-frequency = <100000>;