arch/arm/boot/dts/sun5i-a10s.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&intc>;
  18
  19         aliases {
  20                 ethernet0 = &emac;
  21                 serial0 = &uart0;
  22                 serial1 = &uart1;
  23                 serial2 = &uart2;
  24                 serial3 = &uart3;
  25         };
  26
  27         cpus {
  28                 cpu@0 {
  29                         compatible = "arm,cortex-a8";
  30                 };
  31         };
  32
  33         memory {
  34                 reg = <0x40000000 0x20000000>;
  35         };
  36
  37         clocks {
  38                 #address-cells = <1>;
  39                 #size-cells = <1>;
  40                 ranges;
  41
  42                 /*
  43                  * This is a dummy clock, to be used as placeholder on
  44                  * other mux clocks when a specific parent clock is not
  45                  * yet implemented. It should be dropped when the driver
  46                  * is complete.
  47                  */
  48                 dummy: dummy {
  49                         #clock-cells = <0>;
  50                         compatible = "fixed-clock";
  51                         clock-frequency = <0>;
  52                 };
  53
  54                 osc24M: clk@01c20050 {
  55                         #clock-cells = <0>;
  56                         compatible = "allwinner,sun4i-a10-osc-clk";
  57                         reg = <0x01c20050 0x4>;
  58                         clock-frequency = <24000000>;
  59                         clock-output-names = "osc24M";
  60                 };
  61
  62                 osc32k: clk@0 {
  63                         #clock-cells = <0>;
  64                         compatible = "fixed-clock";
  65                         clock-frequency = <32768>;
  66                         clock-output-names = "osc32k";
  67                 };
  68
  69                 pll1: clk@01c20000 {
  70                         #clock-cells = <0>;
  71                         compatible = "allwinner,sun4i-a10-pll1-clk";
  72                         reg = <0x01c20000 0x4>;
  73                         clocks = <&osc24M>;
  74                         clock-output-names = "pll1";
  75                 };
  76
  77                 pll4: clk@01c20018 {
  78                         #clock-cells = <0>;
  79                         compatible = "allwinner,sun4i-a10-pll1-clk";
  80                         reg = <0x01c20018 0x4>;
  81                         clocks = <&osc24M>;
  82                         clock-output-names = "pll4";
  83                 };
  84
  85                 pll5: clk@01c20020 {
  86                         #clock-cells = <1>;
  87                         compatible = "allwinner,sun4i-a10-pll5-clk";
  88                         reg = <0x01c20020 0x4>;
  89                         clocks = <&osc24M>;
  90                         clock-output-names = "pll5_ddr", "pll5_other";
  91                 };
  92
  93                 pll6: clk@01c20028 {
  94                         #clock-cells = <1>;
  95                         compatible = "allwinner,sun4i-a10-pll6-clk";
  96                         reg = <0x01c20028 0x4>;
  97                         clocks = <&osc24M>;
  98                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
  99                 };
 100
 101                 /* dummy is 200M */
 102                 cpu: cpu@01c20054 {
 103                         #clock-cells = <0>;
 104                         compatible = "allwinner,sun4i-a10-cpu-clk";
 105                         reg = <0x01c20054 0x4>;
 106                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 107                         clock-output-names = "cpu";
 108                 };
 109
 110                 axi: axi@01c20054 {
 111                         #clock-cells = <0>;
 112                         compatible = "allwinner,sun4i-a10-axi-clk";
 113                         reg = <0x01c20054 0x4>;
 114                         clocks = <&cpu>;
 115                         clock-output-names = "axi";
 116                 };
 117
 118                 axi_gates: clk@01c2005c {
 119                         #clock-cells = <1>;
 120                         compatible = "allwinner,sun4i-a10-axi-gates-clk";
 121                         reg = <0x01c2005c 0x4>;
 122                         clocks = <&axi>;
 123                         clock-output-names = "axi_dram";
 124                 };
 125
 126                 ahb: ahb@01c20054 {
 127                         #clock-cells = <0>;
 128                         compatible = "allwinner,sun4i-a10-ahb-clk";
 129                         reg = <0x01c20054 0x4>;
 130                         clocks = <&axi>;
 131                         clock-output-names = "ahb";
 132                 };
 133
 134                 ahb_gates: clk@01c20060 {
 135                         #clock-cells = <1>;
 136                         compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
 137                         reg = <0x01c20060 0x8>;
 138                         clocks = <&ahb>;
 139                         clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
 140                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
 141                                 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
 142                                 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
 143                                 "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",
 144                                 "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",
 145                                 "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
 146                 };
 147
 148                 apb0: apb0@01c20054 {
 149                         #clock-cells = <0>;
 150                         compatible = "allwinner,sun4i-a10-apb0-clk";
 151                         reg = <0x01c20054 0x4>;
 152                         clocks = <&ahb>;
 153                         clock-output-names = "apb0";
 154                 };
 155
 156                 apb0_gates: clk@01c20068 {
 157                         #clock-cells = <1>;
 158                         compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
 159                         reg = <0x01c20068 0x4>;
 160                         clocks = <&apb0>;
 161                         clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",
 162                                 "apb0_ir", "apb0_keypad";
 163                 };
 164
 165                 apb1_mux: apb1_mux@01c20058 {
 166                         #clock-cells = <0>;
 167                         compatible = "allwinner,sun4i-a10-apb1-mux-clk";
 168                         reg = <0x01c20058 0x4>;
 169                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 170                         clock-output-names = "apb1_mux";
 171                 };
 172
 173                 apb1: apb1@01c20058 {
 174                         #clock-cells = <0>;
 175                         compatible = "allwinner,sun4i-a10-apb1-clk";
 176                         reg = <0x01c20058 0x4>;
 177                         clocks = <&apb1_mux>;
 178                         clock-output-names = "apb1";
 179                 };
 180
 181                 apb1_gates: clk@01c2006c {
 182                         #clock-cells = <1>;
 183                         compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
 184                         reg = <0x01c2006c 0x4>;
 185                         clocks = <&apb1>;
 186                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 187                                 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
 188                                 "apb1_uart2", "apb1_uart3";
 189                 };
 190
 191                 nand_clk: clk@01c20080 {
 192                         #clock-cells = <0>;
 193                         compatible = "allwinner,sun4i-a10-mod0-clk";
 194                         reg = <0x01c20080 0x4>;
 195                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 196                         clock-output-names = "nand";
 197                 };
 198
 199                 ms_clk: clk@01c20084 {
 200                         #clock-cells = <0>;
 201                         compatible = "allwinner,sun4i-a10-mod0-clk";
 202                         reg = <0x01c20084 0x4>;
 203                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 204                         clock-output-names = "ms";
 205                 };
 206
 207                 mmc0_clk: clk@01c20088 {
 208                         #clock-cells = <0>;
 209                         compatible = "allwinner,sun4i-a10-mod0-clk";
 210                         reg = <0x01c20088 0x4>;
 211                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 212                         clock-output-names = "mmc0";
 213                 };
 214
 215                 mmc1_clk: clk@01c2008c {
 216                         #clock-cells = <0>;
 217                         compatible = "allwinner,sun4i-a10-mod0-clk";
 218                         reg = <0x01c2008c 0x4>;
 219                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 220                         clock-output-names = "mmc1";
 221                 };
 222
 223                 mmc2_clk: clk@01c20090 {
 224                         #clock-cells = <0>;
 225                         compatible = "allwinner,sun4i-a10-mod0-clk";
 226                         reg = <0x01c20090 0x4>;
 227                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 228                         clock-output-names = "mmc2";
 229                 };
 230
 231                 ts_clk: clk@01c20098 {
 232                         #clock-cells = <0>;
 233                         compatible = "allwinner,sun4i-a10-mod0-clk";
 234                         reg = <0x01c20098 0x4>;
 235                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 236                         clock-output-names = "ts";
 237                 };
 238
 239                 ss_clk: clk@01c2009c {
 240                         #clock-cells = <0>;
 241                         compatible = "allwinner,sun4i-a10-mod0-clk";
 242                         reg = <0x01c2009c 0x4>;
 243                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 244                         clock-output-names = "ss";
 245                 };
 246
 247                 spi0_clk: clk@01c200a0 {
 248                         #clock-cells = <0>;
 249                         compatible = "allwinner,sun4i-a10-mod0-clk";
 250                         reg = <0x01c200a0 0x4>;
 251                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 252                         clock-output-names = "spi0";
 253                 };
 254
 255                 spi1_clk: clk@01c200a4 {
 256                         #clock-cells = <0>;
 257                         compatible = "allwinner,sun4i-a10-mod0-clk";
 258                         reg = <0x01c200a4 0x4>;
 259                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 260                         clock-output-names = "spi1";
 261                 };
 262
 263                 spi2_clk: clk@01c200a8 {
 264                         #clock-cells = <0>;
 265                         compatible = "allwinner,sun4i-a10-mod0-clk";
 266                         reg = <0x01c200a8 0x4>;
 267                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 268                         clock-output-names = "spi2";
 269                 };
 270
 271                 ir0_clk: clk@01c200b0 {
 272                         #clock-cells = <0>;
 273                         compatible = "allwinner,sun4i-a10-mod0-clk";
 274                         reg = <0x01c200b0 0x4>;
 275                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 276                         clock-output-names = "ir0";
 277                 };
 278
 279                 usb_clk: clk@01c200cc {
 280                         #clock-cells = <1>;
 281                         #reset-cells = <1>;
 282                         compatible = "allwinner,sun5i-a13-usb-clk";
 283                         reg = <0x01c200cc 0x4>;
 284                         clocks = <&pll6 1>;
 285                         clock-output-names = "usb_ohci0", "usb_phy";
 286                 };
 287
 288                 mbus_clk: clk@01c2015c {
 289                         #clock-cells = <0>;
 290                         compatible = "allwinner,sun4i-a10-mod0-clk";
 291                         reg = <0x01c2015c 0x4>;
 292                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 293                         clock-output-names = "mbus";
 294                 };
 295         };
 296
 297         soc@01c00000 {
 298                 compatible = "simple-bus";
 299                 #address-cells = <1>;
 300                 #size-cells = <1>;
 301                 ranges;
 302
 303                 emac: ethernet@01c0b000 {
 304                         compatible = "allwinner,sun4i-emac";
 305                         reg = <0x01c0b000 0x1000>;
 306                         interrupts = <55>;
 307                         clocks = <&ahb_gates 17>;
 308                         status = "disabled";
 309                 };
 310
 311                 mdio@01c0b080 {
 312                         compatible = "allwinner,sun4i-mdio";
 313                         reg = <0x01c0b080 0x14>;
 314                         status = "disabled";
 315                         #address-cells = <1>;
 316                         #size-cells = <0>;
 317                 };
 318
 319                 intc: interrupt-controller@01c20400 {
 320                         compatible = "allwinner,sun4i-ic";
 321                         reg = <0x01c20400 0x400>;
 322                         interrupt-controller;
 323                         #interrupt-cells = <1>;
 324                 };
 325
 326                 pio: pinctrl@01c20800 {
 327                         compatible = "allwinner,sun5i-a10s-pinctrl";
 328                         reg = <0x01c20800 0x400>;
 329                         interrupts = <28>;
 330                         clocks = <&apb0_gates 5>;
 331                         gpio-controller;
 332                         interrupt-controller;
 333                         #address-cells = <1>;
 334                         #size-cells = <0>;
 335                         #gpio-cells = <3>;
 336
 337                         uart0_pins_a: uart0@0 {
 338                                 allwinner,pins = "PB19", "PB20";
 339                                 allwinner,function = "uart0";
 340                                 allwinner,drive = <0>;
 341                                 allwinner,pull = <0>;
 342                         };
 343
 344                         uart2_pins_a: uart2@0 {
 345                                 allwinner,pins = "PC18", "PC19";
 346                                 allwinner,function = "uart2";
 347                                 allwinner,drive = <0>;
 348                                 allwinner,pull = <0>;
 349                         };
 350
 351                         uart3_pins_a: uart3@0 {
 352                                 allwinner,pins = "PG9", "PG10";
 353                                 allwinner,function = "uart3";
 354                                 allwinner,drive = <0>;
 355                                 allwinner,pull = <0>;
 356                         };
 357
 358                         emac_pins_a: emac0@0 {
 359                                 allwinner,pins = "PA0", "PA1", "PA2",
 360                                                 "PA3", "PA4", "PA5", "PA6",
 361                                                 "PA7", "PA8", "PA9", "PA10",
 362                                                 "PA11", "PA12", "PA13", "PA14",
 363                                                 "PA15", "PA16";
 364                                 allwinner,function = "emac";
 365                                 allwinner,drive = <0>;
 366                                 allwinner,pull = <0>;
 367                         };
 368
 369                         i2c0_pins_a: i2c0@0 {
 370                                 allwinner,pins = "PB0", "PB1";
 371                                 allwinner,function = "i2c0";
 372                                 allwinner,drive = <0>;
 373                                 allwinner,pull = <0>;
 374                         };
 375
 376                         i2c1_pins_a: i2c1@0 {
 377                                 allwinner,pins = "PB15", "PB16";
 378                                 allwinner,function = "i2c1";
 379                                 allwinner,drive = <0>;
 380                                 allwinner,pull = <0>;
 381                         };
 382
 383                         i2c2_pins_a: i2c2@0 {
 384                                 allwinner,pins = "PB17", "PB18";
 385                                 allwinner,function = "i2c2";
 386                                 allwinner,drive = <0>;
 387                                 allwinner,pull = <0>;
 388                         };
 389                 };
 390
 391                 timer@01c20c00 {
 392                         compatible = "allwinner,sun4i-timer";
 393                         reg = <0x01c20c00 0x90>;
 394                         interrupts = <22>;
 395                         clocks = <&osc24M>;
 396                 };
 397
 398                 wdt: watchdog@01c20c90 {
 399                         compatible = "allwinner,sun4i-wdt";
 400                         reg = <0x01c20c90 0x10>;
 401                 };
 402
 403                 sid: eeprom@01c23800 {
 404                         compatible = "allwinner,sun4i-sid";
 405                         reg = <0x01c23800 0x10>;
 406                 };
 407
 408                 rtp: rtp@01c25000 {
 409                         compatible = "allwinner,sun4i-ts";
 410                         reg = <0x01c25000 0x100>;
 411                         interrupts = <29>;
 412                 };
 413
 414                 uart0: serial@01c28000 {
 415                         compatible = "snps,dw-apb-uart";
 416                         reg = <0x01c28000 0x400>;
 417                         interrupts = <1>;
 418                         reg-shift = <2>;
 419                         reg-io-width = <4>;
 420                         clocks = <&apb1_gates 16>;
 421                         status = "disabled";
 422                 };
 423
 424                 uart1: serial@01c28400 {
 425                         compatible = "snps,dw-apb-uart";
 426                         reg = <0x01c28400 0x400>;
 427                         interrupts = <2>;
 428                         reg-shift = <2>;
 429                         reg-io-width = <4>;
 430                         clocks = <&apb1_gates 17>;
 431                         status = "disabled";
 432                 };
 433
 434                 uart2: serial@01c28800 {
 435                         compatible = "snps,dw-apb-uart";
 436                         reg = <0x01c28800 0x400>;
 437                         interrupts = <3>;
 438                         reg-shift = <2>;
 439                         reg-io-width = <4>;
 440                         clocks = <&apb1_gates 18>;
 441                         status = "disabled";
 442                 };
 443
 444                 uart3: serial@01c28c00 {
 445                         compatible = "snps,dw-apb-uart";
 446                         reg = <0x01c28c00 0x400>;
 447                         interrupts = <4>;
 448                         reg-shift = <2>;
 449                         reg-io-width = <4>;
 450                         clocks = <&apb1_gates 19>;
 451                         status = "disabled";
 452                 };
 453
 454                 i2c0: i2c@01c2ac00 {
 455                         #address-cells = <1>;
 456                         #size-cells = <0>;
 457                         compatible = "allwinner,sun4i-i2c";
 458                         reg = <0x01c2ac00 0x400>;
 459                         interrupts = <7>;
 460                         clocks = <&apb1_gates 0>;
 461                         clock-frequency = <100000>;
 462                         status = "disabled";
 463                 };
 464
 465                 i2c1: i2c@01c2b000 {
 466                         #address-cells = <1>;
 467                         #size-cells = <0>;
 468                         compatible = "allwinner,sun4i-i2c";
 469                         reg = <0x01c2b000 0x400>;
 470                         interrupts = <8>;
 471                         clocks = <&apb1_gates 1>;
 472                         clock-frequency = <100000>;
 473                         status = "disabled";
 474                 };
 475
 476                 i2c2: i2c@01c2b400 {
 477                         #address-cells = <1>;
 478                         #size-cells = <0>;
 479                         compatible = "allwinner,sun4i-i2c";
 480                         reg = <0x01c2b400 0x400>;
 481                         interrupts = <9>;
 482                         clocks = <&apb1_gates 2>;
 483                         clock-frequency = <100000>;
 484                         status = "disabled";
 485                 };
 486
 487                 timer@01c60000 {
 488                         compatible = "allwinner,sun5i-a13-hstimer";
 489                         reg = <0x01c60000 0x1000>;
 490                         interrupts = <82>, <83>;
 491                         clocks = <&ahb_gates 28>;
 492                 };
 493         };
 494 };