2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 /include/ "skeleton.dtsi"
17 interrupt-parent = <&intc>;
21 compatible = "arm,cortex-a8";
26 reg = <0x40000000 0x20000000>;
35 * This is a dummy clock, to be used as placeholder on
36 * other mux clocks when a specific parent clock is not
37 * yet implemented. It should be dropped when the driver
42 compatible = "fixed-clock";
43 clock-frequency = <0>;
46 osc24M: osc24M@01c20050 {
48 compatible = "allwinner,sun4i-osc-clk";
49 reg = <0x01c20050 0x4>;
50 clock-frequency = <24000000>;
55 compatible = "fixed-clock";
56 clock-frequency = <32768>;
61 compatible = "allwinner,sun4i-pll1-clk";
62 reg = <0x01c20000 0x4>;
69 compatible = "allwinner,sun4i-cpu-clk";
70 reg = <0x01c20054 0x4>;
71 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
76 compatible = "allwinner,sun4i-axi-clk";
77 reg = <0x01c20054 0x4>;
81 axi_gates: axi_gates@01c2005c {
83 compatible = "allwinner,sun4i-axi-gates-clk";
84 reg = <0x01c2005c 0x4>;
86 clock-output-names = "axi_dram";
91 compatible = "allwinner,sun4i-ahb-clk";
92 reg = <0x01c20054 0x4>;
96 ahb_gates: ahb_gates@01c20060 {
98 compatible = "allwinner,sun4i-ahb-gates-clk";
99 reg = <0x01c20060 0x8>;
101 clock-output-names = "ahb_usb0", "ahb_ehci0",
102 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
103 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
104 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
105 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
106 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
107 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
108 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
109 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
110 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
111 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
114 apb0: apb0@01c20054 {
116 compatible = "allwinner,sun4i-apb0-clk";
117 reg = <0x01c20054 0x4>;
121 apb0_gates: apb0_gates@01c20068 {
123 compatible = "allwinner,sun4i-apb0-gates-clk";
124 reg = <0x01c20068 0x4>;
126 clock-output-names = "apb0_codec", "apb0_spdif",
127 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
128 "apb0_ir1", "apb0_keypad";
132 apb1_mux: apb1_mux@01c20058 {
134 compatible = "allwinner,sun4i-apb1-mux-clk";
135 reg = <0x01c20058 0x4>;
136 clocks = <&osc24M>, <&dummy>, <&osc32k>;
139 apb1: apb1@01c20058 {
141 compatible = "allwinner,sun4i-apb1-clk";
142 reg = <0x01c20058 0x4>;
143 clocks = <&apb1_mux>;
146 apb1_gates: apb1_gates@01c2006c {
148 compatible = "allwinner,sun4i-apb1-gates-clk";
149 reg = <0x01c2006c 0x4>;
151 clock-output-names = "apb1_i2c0", "apb1_i2c1",
152 "apb1_i2c2", "apb1_can", "apb1_scr",
153 "apb1_ps20", "apb1_ps21", "apb1_uart0",
154 "apb1_uart1", "apb1_uart2", "apb1_uart3",
155 "apb1_uart4", "apb1_uart5", "apb1_uart6",
161 compatible = "simple-bus";
162 #address-cells = <1>;
166 emac: ethernet@01c0b000 {
167 compatible = "allwinner,sun4i-emac";
168 reg = <0x01c0b000 0x1000>;
170 clocks = <&ahb_gates 17>;
175 compatible = "allwinner,sun4i-mdio";
176 reg = <0x01c0b080 0x14>;
178 #address-cells = <1>;
182 intc: interrupt-controller@01c20400 {
183 compatible = "allwinner,sun4i-ic";
184 reg = <0x01c20400 0x400>;
185 interrupt-controller;
186 #interrupt-cells = <1>;
189 pio: pinctrl@01c20800 {
190 compatible = "allwinner,sun5i-a10s-pinctrl";
191 reg = <0x01c20800 0x400>;
193 clocks = <&apb0_gates 5>;
195 interrupt-controller;
196 #address-cells = <1>;
200 uart0_pins_a: uart0@0 {
201 allwinner,pins = "PB19", "PB20";
202 allwinner,function = "uart0";
203 allwinner,drive = <0>;
204 allwinner,pull = <0>;
207 uart2_pins_a: uart2@0 {
208 allwinner,pins = "PC18", "PC19";
209 allwinner,function = "uart2";
210 allwinner,drive = <0>;
211 allwinner,pull = <0>;
214 uart3_pins_a: uart3@0 {
215 allwinner,pins = "PG9", "PG10";
216 allwinner,function = "uart3";
217 allwinner,drive = <0>;
218 allwinner,pull = <0>;
221 emac_pins_a: emac0@0 {
222 allwinner,pins = "PA0", "PA1", "PA2",
223 "PA3", "PA4", "PA5", "PA6",
224 "PA7", "PA8", "PA9", "PA10",
225 "PA11", "PA12", "PA13", "PA14",
227 allwinner,function = "emac";
228 allwinner,drive = <0>;
229 allwinner,pull = <0>;
232 i2c0_pins_a: i2c0@0 {
233 allwinner,pins = "PB0", "PB1";
234 allwinner,function = "i2c0";
235 allwinner,drive = <0>;
236 allwinner,pull = <0>;
239 i2c1_pins_a: i2c1@0 {
240 allwinner,pins = "PB15", "PB16";
241 allwinner,function = "i2c1";
242 allwinner,drive = <0>;
243 allwinner,pull = <0>;
246 i2c2_pins_a: i2c2@0 {
247 allwinner,pins = "PB17", "PB18";
248 allwinner,function = "i2c2";
249 allwinner,drive = <0>;
250 allwinner,pull = <0>;
255 compatible = "allwinner,sun4i-timer";
256 reg = <0x01c20c00 0x90>;
261 wdt: watchdog@01c20c90 {
262 compatible = "allwinner,sun4i-wdt";
263 reg = <0x01c20c90 0x10>;
266 uart0: serial@01c28000 {
267 compatible = "snps,dw-apb-uart";
268 reg = <0x01c28000 0x400>;
272 clocks = <&apb1_gates 16>;
276 uart1: serial@01c28400 {
277 compatible = "snps,dw-apb-uart";
278 reg = <0x01c28400 0x400>;
282 clocks = <&apb1_gates 17>;
286 uart2: serial@01c28800 {
287 compatible = "snps,dw-apb-uart";
288 reg = <0x01c28800 0x400>;
292 clocks = <&apb1_gates 18>;
296 uart3: serial@01c28c00 {
297 compatible = "snps,dw-apb-uart";
298 reg = <0x01c28c00 0x400>;
302 clocks = <&apb1_gates 19>;
307 #address-cells = <1>;
309 compatible = "allwinner,sun4i-i2c";
310 reg = <0x01c2ac00 0x400>;
312 clocks = <&apb1_gates 0>;
313 clock-frequency = <100000>;
318 #address-cells = <1>;
320 compatible = "allwinner,sun4i-i2c";
321 reg = <0x01c2b000 0x400>;
323 clocks = <&apb1_gates 1>;
324 clock-frequency = <100000>;
329 #address-cells = <1>;
331 compatible = "allwinner,sun4i-i2c";
332 reg = <0x01c2b400 0x400>;
334 clocks = <&apb1_gates 2>;
335 clock-frequency = <100000>;