2 * Copyright 2013 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 /include/ "skeleton.dtsi"
17 interrupt-parent = <&intc>;
33 compatible = "allwinner,simple-framebuffer", "simple-framebuffer";
34 allwinner,pipeline = "de_be0-lcd0-hdmi";
35 clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
43 compatible = "arm,cortex-a8";
48 reg = <0x40000000 0x20000000>;
57 * This is a dummy clock, to be used as placeholder on
58 * other mux clocks when a specific parent clock is not
59 * yet implemented. It should be dropped when the driver
64 compatible = "fixed-clock";
65 clock-frequency = <0>;
68 osc24M: clk@01c20050 {
70 compatible = "allwinner,sun4i-a10-osc-clk";
71 reg = <0x01c20050 0x4>;
72 clock-frequency = <24000000>;
73 clock-output-names = "osc24M";
78 compatible = "fixed-clock";
79 clock-frequency = <32768>;
80 clock-output-names = "osc32k";
85 compatible = "allwinner,sun4i-a10-pll1-clk";
86 reg = <0x01c20000 0x4>;
88 clock-output-names = "pll1";
93 compatible = "allwinner,sun4i-a10-pll1-clk";
94 reg = <0x01c20018 0x4>;
96 clock-output-names = "pll4";
101 compatible = "allwinner,sun4i-a10-pll5-clk";
102 reg = <0x01c20020 0x4>;
104 clock-output-names = "pll5_ddr", "pll5_other";
109 compatible = "allwinner,sun4i-a10-pll6-clk";
110 reg = <0x01c20028 0x4>;
112 clock-output-names = "pll6_sata", "pll6_other", "pll6";
118 compatible = "allwinner,sun4i-a10-cpu-clk";
119 reg = <0x01c20054 0x4>;
120 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
121 clock-output-names = "cpu";
126 compatible = "allwinner,sun4i-a10-axi-clk";
127 reg = <0x01c20054 0x4>;
129 clock-output-names = "axi";
132 axi_gates: clk@01c2005c {
134 compatible = "allwinner,sun4i-a10-axi-gates-clk";
135 reg = <0x01c2005c 0x4>;
137 clock-output-names = "axi_dram";
142 compatible = "allwinner,sun4i-a10-ahb-clk";
143 reg = <0x01c20054 0x4>;
145 clock-output-names = "ahb";
148 ahb_gates: clk@01c20060 {
150 compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
151 reg = <0x01c20060 0x8>;
153 clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
154 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
155 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
156 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
157 "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",
158 "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",
159 "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
162 apb0: apb0@01c20054 {
164 compatible = "allwinner,sun4i-a10-apb0-clk";
165 reg = <0x01c20054 0x4>;
167 clock-output-names = "apb0";
170 apb0_gates: clk@01c20068 {
172 compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
173 reg = <0x01c20068 0x4>;
175 clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",
176 "apb0_ir", "apb0_keypad";
179 apb1_mux: apb1_mux@01c20058 {
181 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
182 reg = <0x01c20058 0x4>;
183 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
184 clock-output-names = "apb1_mux";
187 apb1: apb1@01c20058 {
189 compatible = "allwinner,sun4i-a10-apb1-clk";
190 reg = <0x01c20058 0x4>;
191 clocks = <&apb1_mux>;
192 clock-output-names = "apb1";
195 apb1_gates: clk@01c2006c {
197 compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
198 reg = <0x01c2006c 0x4>;
200 clock-output-names = "apb1_i2c0", "apb1_i2c1",
201 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
202 "apb1_uart2", "apb1_uart3";
205 nand_clk: clk@01c20080 {
207 compatible = "allwinner,sun4i-a10-mod0-clk";
208 reg = <0x01c20080 0x4>;
209 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
210 clock-output-names = "nand";
213 ms_clk: clk@01c20084 {
215 compatible = "allwinner,sun4i-a10-mod0-clk";
216 reg = <0x01c20084 0x4>;
217 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
218 clock-output-names = "ms";
221 mmc0_clk: clk@01c20088 {
223 compatible = "allwinner,sun4i-a10-mod0-clk";
224 reg = <0x01c20088 0x4>;
225 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
226 clock-output-names = "mmc0";
229 mmc1_clk: clk@01c2008c {
231 compatible = "allwinner,sun4i-a10-mod0-clk";
232 reg = <0x01c2008c 0x4>;
233 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
234 clock-output-names = "mmc1";
237 mmc2_clk: clk@01c20090 {
239 compatible = "allwinner,sun4i-a10-mod0-clk";
240 reg = <0x01c20090 0x4>;
241 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
242 clock-output-names = "mmc2";
245 ts_clk: clk@01c20098 {
247 compatible = "allwinner,sun4i-a10-mod0-clk";
248 reg = <0x01c20098 0x4>;
249 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
250 clock-output-names = "ts";
253 ss_clk: clk@01c2009c {
255 compatible = "allwinner,sun4i-a10-mod0-clk";
256 reg = <0x01c2009c 0x4>;
257 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
258 clock-output-names = "ss";
261 spi0_clk: clk@01c200a0 {
263 compatible = "allwinner,sun4i-a10-mod0-clk";
264 reg = <0x01c200a0 0x4>;
265 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
266 clock-output-names = "spi0";
269 spi1_clk: clk@01c200a4 {
271 compatible = "allwinner,sun4i-a10-mod0-clk";
272 reg = <0x01c200a4 0x4>;
273 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
274 clock-output-names = "spi1";
277 spi2_clk: clk@01c200a8 {
279 compatible = "allwinner,sun4i-a10-mod0-clk";
280 reg = <0x01c200a8 0x4>;
281 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
282 clock-output-names = "spi2";
285 ir0_clk: clk@01c200b0 {
287 compatible = "allwinner,sun4i-a10-mod0-clk";
288 reg = <0x01c200b0 0x4>;
289 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
290 clock-output-names = "ir0";
293 usb_clk: clk@01c200cc {
296 compatible = "allwinner,sun5i-a13-usb-clk";
297 reg = <0x01c200cc 0x4>;
299 clock-output-names = "usb_ohci0", "usb_phy";
302 mbus_clk: clk@01c2015c {
304 compatible = "allwinner,sun5i-a13-mbus-clk";
305 reg = <0x01c2015c 0x4>;
306 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
307 clock-output-names = "mbus";
312 compatible = "simple-bus";
313 #address-cells = <1>;
317 dma: dma-controller@01c02000 {
318 compatible = "allwinner,sun4i-a10-dma";
319 reg = <0x01c02000 0x1000>;
321 clocks = <&ahb_gates 6>;
326 compatible = "allwinner,sun4i-a10-spi";
327 reg = <0x01c05000 0x1000>;
329 clocks = <&ahb_gates 20>, <&spi0_clk>;
330 clock-names = "ahb", "mod";
331 dmas = <&dma 1 27>, <&dma 1 26>;
332 dma-names = "rx", "tx";
334 #address-cells = <1>;
339 compatible = "allwinner,sun4i-a10-spi";
340 reg = <0x01c06000 0x1000>;
342 clocks = <&ahb_gates 21>, <&spi1_clk>;
343 clock-names = "ahb", "mod";
344 dmas = <&dma 1 9>, <&dma 1 8>;
345 dma-names = "rx", "tx";
347 #address-cells = <1>;
351 emac: ethernet@01c0b000 {
352 compatible = "allwinner,sun4i-a10-emac";
353 reg = <0x01c0b000 0x1000>;
355 clocks = <&ahb_gates 17>;
360 compatible = "allwinner,sun4i-a10-mdio";
361 reg = <0x01c0b080 0x14>;
363 #address-cells = <1>;
368 compatible = "allwinner,sun5i-a13-mmc";
369 reg = <0x01c0f000 0x1000>;
370 clocks = <&ahb_gates 8>, <&mmc0_clk>;
371 clock-names = "ahb", "mmc";
377 compatible = "allwinner,sun5i-a13-mmc";
378 reg = <0x01c10000 0x1000>;
379 clocks = <&ahb_gates 9>, <&mmc1_clk>;
380 clock-names = "ahb", "mmc";
386 compatible = "allwinner,sun5i-a13-mmc";
387 reg = <0x01c11000 0x1000>;
388 clocks = <&ahb_gates 10>, <&mmc2_clk>;
389 clock-names = "ahb", "mmc";
394 usbphy: phy@01c13400 {
396 compatible = "allwinner,sun5i-a13-usb-phy";
397 reg = <0x01c13400 0x10 0x01c14800 0x4>;
398 reg-names = "phy_ctrl", "pmu1";
399 clocks = <&usb_clk 8>;
400 clock-names = "usb_phy";
401 resets = <&usb_clk 1>;
402 reset-names = "usb1_reset";
406 ehci0: usb@01c14000 {
407 compatible = "allwinner,sun5i-a10s-ehci", "generic-ehci";
408 reg = <0x01c14000 0x100>;
410 clocks = <&ahb_gates 1>;
416 ohci0: usb@01c14400 {
417 compatible = "allwinner,sun5i-a10s-ohci", "generic-ohci";
418 reg = <0x01c14400 0x100>;
420 clocks = <&usb_clk 6>, <&ahb_gates 2>;
427 compatible = "allwinner,sun4i-a10-spi";
428 reg = <0x01c17000 0x1000>;
430 clocks = <&ahb_gates 22>, <&spi2_clk>;
431 clock-names = "ahb", "mod";
432 dmas = <&dma 1 29>, <&dma 1 28>;
433 dma-names = "rx", "tx";
435 #address-cells = <1>;
439 intc: interrupt-controller@01c20400 {
440 compatible = "allwinner,sun4i-a10-ic";
441 reg = <0x01c20400 0x400>;
442 interrupt-controller;
443 #interrupt-cells = <1>;
446 pio: pinctrl@01c20800 {
447 compatible = "allwinner,sun5i-a10s-pinctrl";
448 reg = <0x01c20800 0x400>;
450 clocks = <&apb0_gates 5>;
452 interrupt-controller;
453 #interrupt-cells = <2>;
457 uart0_pins_a: uart0@0 {
458 allwinner,pins = "PB19", "PB20";
459 allwinner,function = "uart0";
460 allwinner,drive = <0>;
461 allwinner,pull = <0>;
464 uart2_pins_a: uart2@0 {
465 allwinner,pins = "PC18", "PC19";
466 allwinner,function = "uart2";
467 allwinner,drive = <0>;
468 allwinner,pull = <0>;
471 uart3_pins_a: uart3@0 {
472 allwinner,pins = "PG9", "PG10";
473 allwinner,function = "uart3";
474 allwinner,drive = <0>;
475 allwinner,pull = <0>;
478 emac_pins_a: emac0@0 {
479 allwinner,pins = "PA0", "PA1", "PA2",
480 "PA3", "PA4", "PA5", "PA6",
481 "PA7", "PA8", "PA9", "PA10",
482 "PA11", "PA12", "PA13", "PA14",
484 allwinner,function = "emac";
485 allwinner,drive = <0>;
486 allwinner,pull = <0>;
489 i2c0_pins_a: i2c0@0 {
490 allwinner,pins = "PB0", "PB1";
491 allwinner,function = "i2c0";
492 allwinner,drive = <0>;
493 allwinner,pull = <0>;
496 i2c1_pins_a: i2c1@0 {
497 allwinner,pins = "PB15", "PB16";
498 allwinner,function = "i2c1";
499 allwinner,drive = <0>;
500 allwinner,pull = <0>;
503 i2c2_pins_a: i2c2@0 {
504 allwinner,pins = "PB17", "PB18";
505 allwinner,function = "i2c2";
506 allwinner,drive = <0>;
507 allwinner,pull = <0>;
510 mmc0_pins_a: mmc0@0 {
511 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
512 allwinner,function = "mmc0";
513 allwinner,drive = <2>;
514 allwinner,pull = <0>;
517 mmc1_pins_a: mmc1@0 {
518 allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8";
519 allwinner,function = "mmc1";
520 allwinner,drive = <2>;
521 allwinner,pull = <0>;
526 compatible = "allwinner,sun4i-a10-timer";
527 reg = <0x01c20c00 0x90>;
532 wdt: watchdog@01c20c90 {
533 compatible = "allwinner,sun4i-a10-wdt";
534 reg = <0x01c20c90 0x10>;
537 sid: eeprom@01c23800 {
538 compatible = "allwinner,sun4i-a10-sid";
539 reg = <0x01c23800 0x10>;
543 compatible = "allwinner,sun4i-a10-ts";
544 reg = <0x01c25000 0x100>;
548 uart0: serial@01c28000 {
549 compatible = "snps,dw-apb-uart";
550 reg = <0x01c28000 0x400>;
554 clocks = <&apb1_gates 16>;
558 uart1: serial@01c28400 {
559 compatible = "snps,dw-apb-uart";
560 reg = <0x01c28400 0x400>;
564 clocks = <&apb1_gates 17>;
568 uart2: serial@01c28800 {
569 compatible = "snps,dw-apb-uart";
570 reg = <0x01c28800 0x400>;
574 clocks = <&apb1_gates 18>;
578 uart3: serial@01c28c00 {
579 compatible = "snps,dw-apb-uart";
580 reg = <0x01c28c00 0x400>;
584 clocks = <&apb1_gates 19>;
589 #address-cells = <1>;
591 compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
592 reg = <0x01c2ac00 0x400>;
594 clocks = <&apb1_gates 0>;
599 #address-cells = <1>;
601 compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
602 reg = <0x01c2b000 0x400>;
604 clocks = <&apb1_gates 1>;
609 #address-cells = <1>;
611 compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c";
612 reg = <0x01c2b400 0x400>;
614 clocks = <&apb1_gates 2>;
619 compatible = "allwinner,sun5i-a13-hstimer";
620 reg = <0x01c60000 0x1000>;
621 interrupts = <82>, <83>;
622 clocks = <&ahb_gates 28>;