arch/arm/boot/dts/sun5i-a13.dtsi

   1 /*
   2  * Copyright 2012 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 /include/ "skeleton.dtsi"
  15
  16 / {
  17         interrupt-parent = <&intc>;
  18
  19         cpus {
  20                 cpu@0 {
  21                         device_type = "cpu";
  22                         compatible = "arm,cortex-a8";
  23                         reg = <0x0>;
  24                 };
  25         };
  26
  27         memory {
  28                 reg = <0x40000000 0x20000000>;
  29         };
  30
  31         clocks {
  32                 #address-cells = <1>;
  33                 #size-cells = <1>;
  34                 ranges;
  35
  36                 /*
  37                  * This is a dummy clock, to be used as placeholder on
  38                  * other mux clocks when a specific parent clock is not
  39                  * yet implemented. It should be dropped when the driver
  40                  * is complete.
  41                  */
  42                 dummy: dummy {
  43                         #clock-cells = <0>;
  44                         compatible = "fixed-clock";
  45                         clock-frequency = <0>;
  46                 };
  47
  48                 osc24M: osc24M@01c20050 {
  49                         #clock-cells = <0>;
  50                         compatible = "allwinner,sun4i-osc-clk";
  51                         reg = <0x01c20050 0x4>;
  52                         clock-frequency = <24000000>;
  53                 };
  54
  55                 osc32k: osc32k {
  56                         #clock-cells = <0>;
  57                         compatible = "fixed-clock";
  58                         clock-frequency = <32768>;
  59                 };
  60
  61                 pll1: pll1@01c20000 {
  62                         #clock-cells = <0>;
  63                         compatible = "allwinner,sun4i-pll1-clk";
  64                         reg = <0x01c20000 0x4>;
  65                         clocks = <&osc24M>;
  66                 };
  67
  68                 /* dummy is 200M */
  69                 cpu: cpu@01c20054 {
  70                         #clock-cells = <0>;
  71                         compatible = "allwinner,sun4i-cpu-clk";
  72                         reg = <0x01c20054 0x4>;
  73                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
  74                 };
  75
  76                 axi: axi@01c20054 {
  77                         #clock-cells = <0>;
  78                         compatible = "allwinner,sun4i-axi-clk";
  79                         reg = <0x01c20054 0x4>;
  80                         clocks = <&cpu>;
  81                 };
  82
  83                 axi_gates: axi_gates@01c2005c {
  84                         #clock-cells = <1>;
  85                         compatible = "allwinner,sun4i-axi-gates-clk";
  86                         reg = <0x01c2005c 0x4>;
  87                         clocks = <&axi>;
  88                         clock-output-names = "axi_dram";
  89                 };
  90
  91                 ahb: ahb@01c20054 {
  92                         #clock-cells = <0>;
  93                         compatible = "allwinner,sun4i-ahb-clk";
  94                         reg = <0x01c20054 0x4>;
  95                         clocks = <&axi>;
  96                 };
  97
  98                 ahb_gates: ahb_gates@01c20060 {
  99                         #clock-cells = <1>;
 100                         compatible = "allwinner,sun4i-ahb-gates-clk";
 101                         reg = <0x01c20060 0x8>;
 102                         clocks = <&ahb>;
 103                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 104                                 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
 105                                 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
 106                                 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
 107                                 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
 108                                 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
 109                                 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
 110                                 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
 111                                 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
 112                                 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
 113                                 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
 114                 };
 115
 116                 apb0: apb0@01c20054 {
 117                         #clock-cells = <0>;
 118                         compatible = "allwinner,sun4i-apb0-clk";
 119                         reg = <0x01c20054 0x4>;
 120                         clocks = <&ahb>;
 121                 };
 122
 123                 apb0_gates: apb0_gates@01c20068 {
 124                         #clock-cells = <1>;
 125                         compatible = "allwinner,sun4i-apb0-gates-clk";
 126                         reg = <0x01c20068 0x4>;
 127                         clocks = <&apb0>;
 128                         clock-output-names = "apb0_codec", "apb0_spdif",
 129                                 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
 130                                 "apb0_ir1", "apb0_keypad";
 131                 };
 132
 133                 /* dummy is pll62 */
 134                 apb1_mux: apb1_mux@01c20058 {
 135                         #clock-cells = <0>;
 136                         compatible = "allwinner,sun4i-apb1-mux-clk";
 137                         reg = <0x01c20058 0x4>;
 138                         clocks = <&osc24M>, <&dummy>, <&osc32k>;
 139                 };
 140
 141                 apb1: apb1@01c20058 {
 142                         #clock-cells = <0>;
 143                         compatible = "allwinner,sun4i-apb1-clk";
 144                         reg = <0x01c20058 0x4>;
 145                         clocks = <&apb1_mux>;
 146                 };
 147
 148                 apb1_gates: apb1_gates@01c2006c {
 149                         #clock-cells = <1>;
 150                         compatible = "allwinner,sun4i-apb1-gates-clk";
 151                         reg = <0x01c2006c 0x4>;
 152                         clocks = <&apb1>;
 153                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 154                                 "apb1_i2c2", "apb1_can", "apb1_scr",
 155                                 "apb1_ps20", "apb1_ps21", "apb1_uart0",
 156                                 "apb1_uart1", "apb1_uart2", "apb1_uart3",
 157                                 "apb1_uart4", "apb1_uart5", "apb1_uart6",
 158                                 "apb1_uart7";
 159                 };
 160         };
 161
 162         soc@01c20000 {
 163                 compatible = "simple-bus";
 164                 #address-cells = <1>;
 165                 #size-cells = <1>;
 166                 reg = <0x01c20000 0x300000>;
 167                 ranges;
 168
 169                 intc: interrupt-controller@01c20400 {
 170                         compatible = "allwinner,sun4i-ic";
 171                         reg = <0x01c20400 0x400>;
 172                         interrupt-controller;
 173                         #interrupt-cells = <1>;
 174                 };
 175
 176                 pio: pinctrl@01c20800 {
 177                         compatible = "allwinner,sun5i-a13-pinctrl";
 178                         reg = <0x01c20800 0x400>;
 179                         clocks = <&apb0_gates 5>;
 180                         gpio-controller;
 181                         #address-cells = <1>;
 182                         #size-cells = <0>;
 183                         #gpio-cells = <3>;
 184
 185                         uart1_pins_a: uart1@0 {
 186                                 allwinner,pins = "PE10", "PE11";
 187                                 allwinner,function = "uart1";
 188                                 allwinner,drive = <0>;
 189                                 allwinner,pull = <0>;
 190                         };
 191
 192                         uart1_pins_b: uart1@1 {
 193                                 allwinner,pins = "PG3", "PG4";
 194                                 allwinner,function = "uart1";
 195                                 allwinner,drive = <0>;
 196                                 allwinner,pull = <0>;
 197                         };
 198                 };
 199
 200                 timer@01c20c00 {
 201                         compatible = "allwinner,sun4i-timer";
 202                         reg = <0x01c20c00 0x90>;
 203                         interrupts = <22>;
 204                         clocks = <&osc24M>;
 205                 };
 206
 207                 wdt: watchdog@01c20c90 {
 208                         compatible = "allwinner,sun4i-wdt";
 209                         reg = <0x01c20c90 0x10>;
 210                 };
 211
 212                 uart1: serial@01c28400 {
 213                         compatible = "snps,dw-apb-uart";
 214                         reg = <0x01c28400 0x400>;
 215                         interrupts = <2>;
 216                         reg-shift = <2>;
 217                         reg-io-width = <4>;
 218                         clocks = <&apb1_gates 17>;
 219                         status = "disabled";
 220                 };
 221
 222                 uart3: serial@01c28c00 {
 223                         compatible = "snps,dw-apb-uart";
 224                         reg = <0x01c28c00 0x400>;
 225                         interrupts = <4>;
 226                         reg-shift = <2>;
 227                         reg-io-width = <4>;
 228                         clocks = <&apb1_gates 19>;
 229                         status = "disabled";
 230                 };
 231         };
 232 };