2 * Copyright 2012 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 /include/ "skeleton.dtsi"
17 interrupt-parent = <&intc>;
29 compatible = "arm,cortex-a8";
35 reg = <0x40000000 0x20000000>;
44 * This is a dummy clock, to be used as placeholder on
45 * other mux clocks when a specific parent clock is not
46 * yet implemented. It should be dropped when the driver
51 compatible = "fixed-clock";
52 clock-frequency = <0>;
55 osc24M: clk@01c20050 {
57 compatible = "allwinner,sun4i-a10-osc-clk";
58 reg = <0x01c20050 0x4>;
59 clock-frequency = <24000000>;
60 clock-output-names = "osc24M";
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
67 clock-output-names = "osc32k";
72 compatible = "allwinner,sun4i-a10-pll1-clk";
73 reg = <0x01c20000 0x4>;
75 clock-output-names = "pll1";
80 compatible = "allwinner,sun4i-a10-pll1-clk";
81 reg = <0x01c20018 0x4>;
83 clock-output-names = "pll4";
88 compatible = "allwinner,sun4i-a10-pll5-clk";
89 reg = <0x01c20020 0x4>;
91 clock-output-names = "pll5_ddr", "pll5_other";
96 compatible = "allwinner,sun4i-a10-pll6-clk";
97 reg = <0x01c20028 0x4>;
99 clock-output-names = "pll6_sata", "pll6_other", "pll6";
105 compatible = "allwinner,sun4i-a10-cpu-clk";
106 reg = <0x01c20054 0x4>;
107 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
108 clock-output-names = "cpu";
113 compatible = "allwinner,sun4i-a10-axi-clk";
114 reg = <0x01c20054 0x4>;
116 clock-output-names = "axi";
119 axi_gates: clk@01c2005c {
121 compatible = "allwinner,sun4i-a10-axi-gates-clk";
122 reg = <0x01c2005c 0x4>;
124 clock-output-names = "axi_dram";
129 compatible = "allwinner,sun4i-a10-ahb-clk";
130 reg = <0x01c20054 0x4>;
132 clock-output-names = "ahb";
135 ahb_gates: clk@01c20060 {
137 compatible = "allwinner,sun5i-a13-ahb-gates-clk";
138 reg = <0x01c20060 0x8>;
140 clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
141 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
142 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
143 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
144 "ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
145 "ahb_de_fe", "ahb_iep", "ahb_mali400";
148 apb0: apb0@01c20054 {
150 compatible = "allwinner,sun4i-a10-apb0-clk";
151 reg = <0x01c20054 0x4>;
153 clock-output-names = "apb0";
156 apb0_gates: clk@01c20068 {
158 compatible = "allwinner,sun5i-a13-apb0-gates-clk";
159 reg = <0x01c20068 0x4>;
161 clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
166 compatible = "allwinner,sun4i-a10-apb1-clk";
167 reg = <0x01c20058 0x4>;
168 clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
169 clock-output-names = "apb1";
172 apb1_gates: clk@01c2006c {
174 compatible = "allwinner,sun5i-a13-apb1-gates-clk";
175 reg = <0x01c2006c 0x4>;
177 clock-output-names = "apb1_i2c0", "apb1_i2c1",
178 "apb1_i2c2", "apb1_uart1", "apb1_uart3";
181 nand_clk: clk@01c20080 {
183 compatible = "allwinner,sun4i-a10-mod0-clk";
184 reg = <0x01c20080 0x4>;
185 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
186 clock-output-names = "nand";
189 ms_clk: clk@01c20084 {
191 compatible = "allwinner,sun4i-a10-mod0-clk";
192 reg = <0x01c20084 0x4>;
193 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
194 clock-output-names = "ms";
197 mmc0_clk: clk@01c20088 {
199 compatible = "allwinner,sun4i-a10-mod0-clk";
200 reg = <0x01c20088 0x4>;
201 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
202 clock-output-names = "mmc0";
205 mmc1_clk: clk@01c2008c {
207 compatible = "allwinner,sun4i-a10-mod0-clk";
208 reg = <0x01c2008c 0x4>;
209 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
210 clock-output-names = "mmc1";
213 mmc2_clk: clk@01c20090 {
215 compatible = "allwinner,sun4i-a10-mod0-clk";
216 reg = <0x01c20090 0x4>;
217 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
218 clock-output-names = "mmc2";
221 ts_clk: clk@01c20098 {
223 compatible = "allwinner,sun4i-a10-mod0-clk";
224 reg = <0x01c20098 0x4>;
225 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
226 clock-output-names = "ts";
229 ss_clk: clk@01c2009c {
231 compatible = "allwinner,sun4i-a10-mod0-clk";
232 reg = <0x01c2009c 0x4>;
233 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
234 clock-output-names = "ss";
237 spi0_clk: clk@01c200a0 {
239 compatible = "allwinner,sun4i-a10-mod0-clk";
240 reg = <0x01c200a0 0x4>;
241 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
242 clock-output-names = "spi0";
245 spi1_clk: clk@01c200a4 {
247 compatible = "allwinner,sun4i-a10-mod0-clk";
248 reg = <0x01c200a4 0x4>;
249 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
250 clock-output-names = "spi1";
253 spi2_clk: clk@01c200a8 {
255 compatible = "allwinner,sun4i-a10-mod0-clk";
256 reg = <0x01c200a8 0x4>;
257 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
258 clock-output-names = "spi2";
261 ir0_clk: clk@01c200b0 {
263 compatible = "allwinner,sun4i-a10-mod0-clk";
264 reg = <0x01c200b0 0x4>;
265 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
266 clock-output-names = "ir0";
269 usb_clk: clk@01c200cc {
272 compatible = "allwinner,sun5i-a13-usb-clk";
273 reg = <0x01c200cc 0x4>;
275 clock-output-names = "usb_ohci0", "usb_phy";
278 mbus_clk: clk@01c2015c {
280 compatible = "allwinner,sun5i-a13-mbus-clk";
281 reg = <0x01c2015c 0x4>;
282 clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
283 clock-output-names = "mbus";
288 compatible = "simple-bus";
289 #address-cells = <1>;
293 dma: dma-controller@01c02000 {
294 compatible = "allwinner,sun4i-a10-dma";
295 reg = <0x01c02000 0x1000>;
297 clocks = <&ahb_gates 6>;
302 compatible = "allwinner,sun4i-a10-spi";
303 reg = <0x01c05000 0x1000>;
305 clocks = <&ahb_gates 20>, <&spi0_clk>;
306 clock-names = "ahb", "mod";
307 dmas = <&dma 1 27>, <&dma 1 26>;
308 dma-names = "rx", "tx";
310 #address-cells = <1>;
315 compatible = "allwinner,sun4i-a10-spi";
316 reg = <0x01c06000 0x1000>;
318 clocks = <&ahb_gates 21>, <&spi1_clk>;
319 clock-names = "ahb", "mod";
320 dmas = <&dma 1 9>, <&dma 1 8>;
321 dma-names = "rx", "tx";
323 #address-cells = <1>;
328 compatible = "allwinner,sun5i-a13-mmc";
329 reg = <0x01c0f000 0x1000>;
330 clocks = <&ahb_gates 8>, <&mmc0_clk>;
331 clock-names = "ahb", "mmc";
337 compatible = "allwinner,sun5i-a13-mmc";
338 reg = <0x01c11000 0x1000>;
339 clocks = <&ahb_gates 10>, <&mmc2_clk>;
340 clock-names = "ahb", "mmc";
345 usbphy: phy@01c13400 {
347 compatible = "allwinner,sun5i-a13-usb-phy";
348 reg = <0x01c13400 0x10 0x01c14800 0x4>;
349 reg-names = "phy_ctrl", "pmu1";
350 clocks = <&usb_clk 8>;
351 clock-names = "usb_phy";
352 resets = <&usb_clk 1>;
353 reset-names = "usb1_reset";
357 ehci0: usb@01c14000 {
358 compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
359 reg = <0x01c14000 0x100>;
361 clocks = <&ahb_gates 1>;
367 ohci0: usb@01c14400 {
368 compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
369 reg = <0x01c14400 0x100>;
371 clocks = <&usb_clk 6>, <&ahb_gates 2>;
378 compatible = "allwinner,sun4i-a10-spi";
379 reg = <0x01c17000 0x1000>;
381 clocks = <&ahb_gates 22>, <&spi2_clk>;
382 clock-names = "ahb", "mod";
383 dmas = <&dma 1 29>, <&dma 1 28>;
384 dma-names = "rx", "tx";
386 #address-cells = <1>;
390 intc: interrupt-controller@01c20400 {
391 compatible = "allwinner,sun4i-a10-ic";
392 reg = <0x01c20400 0x400>;
393 interrupt-controller;
394 #interrupt-cells = <1>;
397 pio: pinctrl@01c20800 {
398 compatible = "allwinner,sun5i-a13-pinctrl";
399 reg = <0x01c20800 0x400>;
401 clocks = <&apb0_gates 5>;
403 interrupt-controller;
404 #interrupt-cells = <2>;
408 uart1_pins_a: uart1@0 {
409 allwinner,pins = "PE10", "PE11";
410 allwinner,function = "uart1";
411 allwinner,drive = <0>;
412 allwinner,pull = <0>;
415 uart1_pins_b: uart1@1 {
416 allwinner,pins = "PG3", "PG4";
417 allwinner,function = "uart1";
418 allwinner,drive = <0>;
419 allwinner,pull = <0>;
422 i2c0_pins_a: i2c0@0 {
423 allwinner,pins = "PB0", "PB1";
424 allwinner,function = "i2c0";
425 allwinner,drive = <0>;
426 allwinner,pull = <0>;
429 i2c1_pins_a: i2c1@0 {
430 allwinner,pins = "PB15", "PB16";
431 allwinner,function = "i2c1";
432 allwinner,drive = <0>;
433 allwinner,pull = <0>;
436 i2c2_pins_a: i2c2@0 {
437 allwinner,pins = "PB17", "PB18";
438 allwinner,function = "i2c2";
439 allwinner,drive = <0>;
440 allwinner,pull = <0>;
443 mmc0_pins_a: mmc0@0 {
444 allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
445 allwinner,function = "mmc0";
446 allwinner,drive = <2>;
447 allwinner,pull = <0>;
452 compatible = "allwinner,sun4i-a10-timer";
453 reg = <0x01c20c00 0x90>;
458 wdt: watchdog@01c20c90 {
459 compatible = "allwinner,sun4i-a10-wdt";
460 reg = <0x01c20c90 0x10>;
463 sid: eeprom@01c23800 {
464 compatible = "allwinner,sun4i-a10-sid";
465 reg = <0x01c23800 0x10>;
469 compatible = "allwinner,sun4i-a10-ts";
470 reg = <0x01c25000 0x100>;
474 uart1: serial@01c28400 {
475 compatible = "snps,dw-apb-uart";
476 reg = <0x01c28400 0x400>;
480 clocks = <&apb1_gates 17>;
484 uart3: serial@01c28c00 {
485 compatible = "snps,dw-apb-uart";
486 reg = <0x01c28c00 0x400>;
490 clocks = <&apb1_gates 19>;
495 compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
496 reg = <0x01c2ac00 0x400>;
498 clocks = <&apb1_gates 0>;
500 #address-cells = <1>;
505 compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
506 reg = <0x01c2b000 0x400>;
508 clocks = <&apb1_gates 1>;
510 #address-cells = <1>;
515 compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
516 reg = <0x01c2b400 0x400>;
518 clocks = <&apb1_gates 2>;
520 #address-cells = <1>;
525 compatible = "allwinner,sun5i-a13-hstimer";
526 reg = <0x01c60000 0x1000>;
527 interrupts = <82>, <83>;
528 clocks = <&ahb_gates 28>;